JPS57203156A - Computer for control - Google Patents

Computer for control

Info

Publication number
JPS57203156A
JPS57203156A JP9009781A JP9009781A JPS57203156A JP S57203156 A JPS57203156 A JP S57203156A JP 9009781 A JP9009781 A JP 9009781A JP 9009781 A JP9009781 A JP 9009781A JP S57203156 A JPS57203156 A JP S57203156A
Authority
JP
Japan
Prior art keywords
word
output port
mask register
outputted
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9009781A
Other languages
Japanese (ja)
Inventor
Yoshimi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9009781A priority Critical patent/JPS57203156A/en
Publication of JPS57203156A publication Critical patent/JPS57203156A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To perform bit operation, word by word, through a mask register by performing the reading writing operation of an output port by several bits at every time at a control calculator equipped with an address decoder.
CONSTITUTION: For the modification of the part x2 of an output port 51, a CPU 1 sends an address and a control signal to an address decoder 8 having an incorporated flag register part so that data having (1) as the part x1 is outputted to a mask register 511, and sends a selection signal from the decoder 8 to the mask register 511. Then, the CPU 1 outputs a pattern 6x having desired data only at the part x2. Therefore, a pattern having the modified part x2 and unchanged part x1 is outputted to the output port 51 at this time, and bit operation is performed by using the mask register 511 as if word-by-word operation were performed, and a specific number of bits of an output port are read and written.
COPYRIGHT: (C)1982,JPO&Japio
JP9009781A 1981-06-09 1981-06-09 Computer for control Pending JPS57203156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9009781A JPS57203156A (en) 1981-06-09 1981-06-09 Computer for control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9009781A JPS57203156A (en) 1981-06-09 1981-06-09 Computer for control

Publications (1)

Publication Number Publication Date
JPS57203156A true JPS57203156A (en) 1982-12-13

Family

ID=13989011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9009781A Pending JPS57203156A (en) 1981-06-09 1981-06-09 Computer for control

Country Status (1)

Country Link
JP (1) JPS57203156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02267624A (en) * 1989-04-07 1990-11-01 Mitsubishi Electric Corp Microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02267624A (en) * 1989-04-07 1990-11-01 Mitsubishi Electric Corp Microcomputer

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