JPS57191764A - Storage device - Google Patents

Storage device

Info

Publication number
JPS57191764A
JPS57191764A JP56076942A JP7694281A JPS57191764A JP S57191764 A JPS57191764 A JP S57191764A JP 56076942 A JP56076942 A JP 56076942A JP 7694281 A JP7694281 A JP 7694281A JP S57191764 A JPS57191764 A JP S57191764A
Authority
JP
Japan
Prior art keywords
memory blocks
selecting
data exchange
area
selecting signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56076942A
Other languages
Japanese (ja)
Other versions
JPS61656B2 (en
Inventor
Hiroshi Kadota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56076942A priority Critical patent/JPS57191764A/en
Publication of JPS57191764A publication Critical patent/JPS57191764A/en
Publication of JPS61656B2 publication Critical patent/JPS61656B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To obtain a device where the function corresponding to double buffering is implemented with hardware, by providing a microprocessor private area and a data exchange area and exchanging the data exchange area by a selecting circuit. CONSTITUTION:A microprocessor private area and a data exchange area are provided, and the data exchange area is exchanged by a selecting circuit. For example, outputs from the first and the second counters 31 and 34 are inputted to the first and the second main memory blocks 33 and 36 respectively independently of the presence or the absence of a selecting signal on an instruction line 316, and outputs from the first and the second counters 31 and 34 are inputted to the first and the second memory blocks for exchange through a selecting means 37 in accordance with the presence or the absence of the selecting signal on the instruction line 316. When the selecting signal is absent, the first and the second main memory blocks 33 and 36 and the first and the second memory blocks 32 and 35 for exchange are arranged in the same address space; and when the selecting signal is present, the access to the first and the second memory blocks 32 and 35 for exchange is reversed.
JP56076942A 1981-05-21 1981-05-21 Storage device Granted JPS57191764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076942A JPS57191764A (en) 1981-05-21 1981-05-21 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076942A JPS57191764A (en) 1981-05-21 1981-05-21 Storage device

Publications (2)

Publication Number Publication Date
JPS57191764A true JPS57191764A (en) 1982-11-25
JPS61656B2 JPS61656B2 (en) 1986-01-10

Family

ID=13619791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076942A Granted JPS57191764A (en) 1981-05-21 1981-05-21 Storage device

Country Status (1)

Country Link
JP (1) JPS57191764A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197561A (en) * 1982-05-12 1983-11-17 Hitachi Cable Ltd Shared memory system
JPS6015757A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Memory control circuit
JPS60157655A (en) * 1984-01-28 1985-08-17 Fanuc Ltd Auxiliary storage device
JPS6371766A (en) * 1986-09-12 1988-04-01 Fuji Facom Corp Buffer transferring system
JPH04289955A (en) * 1990-11-01 1992-10-14 Internatl Business Mach Corp <Ibm> Link method for code segment in multiprocessor computor system, device having program code means therefor, link method and system for code segment and dynamic link method for code segmet

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197561A (en) * 1982-05-12 1983-11-17 Hitachi Cable Ltd Shared memory system
JPS6015757A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Memory control circuit
JPS60157655A (en) * 1984-01-28 1985-08-17 Fanuc Ltd Auxiliary storage device
JPH0340417B2 (en) * 1984-01-28 1991-06-18
JPS6371766A (en) * 1986-09-12 1988-04-01 Fuji Facom Corp Buffer transferring system
JPH04289955A (en) * 1990-11-01 1992-10-14 Internatl Business Mach Corp <Ibm> Link method for code segment in multiprocessor computor system, device having program code means therefor, link method and system for code segment and dynamic link method for code segmet

Also Published As

Publication number Publication date
JPS61656B2 (en) 1986-01-10

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