JPS5676548A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5676548A
JPS5676548A JP15402079A JP15402079A JPS5676548A JP S5676548 A JPS5676548 A JP S5676548A JP 15402079 A JP15402079 A JP 15402079A JP 15402079 A JP15402079 A JP 15402079A JP S5676548 A JPS5676548 A JP S5676548A
Authority
JP
Japan
Prior art keywords
layer
insulating film
melting point
wiring conductor
disconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15402079A
Other languages
Japanese (ja)
Inventor
Akira Abiru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15402079A priority Critical patent/JPS5676548A/en
Publication of JPS5676548A publication Critical patent/JPS5676548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To eliminate the disconnection of a wire in a semiconductor device by forming two and more layer wiring conductors at both sides of an insulating film, forming the insulating film of low melting point glass molten layer, thereby eliminating the stepwise difference of the interlayer insulating film of the device and flattening the wiring conductor films of the second layer and so forth. CONSTITUTION:An SiO2 film 2 is formed by a CVD on the surface of a semiconductor substrate 1 of Si or the like formed with an element such as a transistor, a window 3 is opened thereat, and a wiring conductor 4 such as aluminum or the like is formed thereon. A low melting point glass 5 such as, for example, glass having a melting point of 390 deg.C made of B2O3, PbO, LiO is sputter evaporated on the entire surface of the substrate. After a window 6 for connecting to the second layer wiring metal is opened, it is heated and molten, and there can be thus formed an insulating film having no stepwise difference on the surface but smooth surface. Thus, the wiring conductor on the second layer can be flattened without disconnection. Accordingly, it can improve the reliability thereof.
JP15402079A 1979-11-28 1979-11-28 Semiconductor device Pending JPS5676548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15402079A JPS5676548A (en) 1979-11-28 1979-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15402079A JPS5676548A (en) 1979-11-28 1979-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5676548A true JPS5676548A (en) 1981-06-24

Family

ID=15575145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15402079A Pending JPS5676548A (en) 1979-11-28 1979-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5676548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962063A (en) * 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
US5112776A (en) * 1988-11-10 1992-05-12 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
US5244841A (en) * 1988-11-10 1993-09-14 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962063A (en) * 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
US5112776A (en) * 1988-11-10 1992-05-12 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
US5244841A (en) * 1988-11-10 1993-09-14 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing

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