JPS56144572A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56144572A
JPS56144572A JP4721180A JP4721180A JPS56144572A JP S56144572 A JPS56144572 A JP S56144572A JP 4721180 A JP4721180 A JP 4721180A JP 4721180 A JP4721180 A JP 4721180A JP S56144572 A JPS56144572 A JP S56144572A
Authority
JP
Japan
Prior art keywords
polycrystalline
cmosic
multilayered
integration
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4721180A
Other languages
Japanese (ja)
Inventor
Shoichi Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP4721180A priority Critical patent/JPS56144572A/en
Publication of JPS56144572A publication Critical patent/JPS56144572A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make the wiring of a CMOSIC multilayered and increase the degree of integration by previously providing a Pt-Si alloy layer at the contact portion between polycrystalline Si and the diffused layer in a substrate in order to obtain an ohmic contact between the polycrystalline Si and the substrate. CONSTITUTION:In the conventional manner, a P well 1, a source 2, a drain 3, an inversion preventing layer 4, a field oxide film 5 and a gate oxide film 6 are provided, and connecting holes are formed. Then Pt or the like is deposited by evaporation and sintered to form a Pt-Si alloy layer 11, and the Pt is removed by using aqua regia. Then, a gate 8 and a wiring 13 are formed by using doped polycrystalline Si, coated with an interlayer insulating film 12 and selectively opened in order to form Al wirings 9. Then, this is coated with PSG to reach completion. By said constitution, the CMOSIC can be minutely miniaturized and multilayered at the same time, so that the degree of integration is increased as well as the power consumption is lowered and speeding up is attained.
JP4721180A 1980-04-10 1980-04-10 Semiconductor device Pending JPS56144572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4721180A JPS56144572A (en) 1980-04-10 1980-04-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4721180A JPS56144572A (en) 1980-04-10 1980-04-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56144572A true JPS56144572A (en) 1981-11-10

Family

ID=12768815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4721180A Pending JPS56144572A (en) 1980-04-10 1980-04-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56144572A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145955A2 (en) * 1983-11-29 1985-06-26 Kabushiki Kaisha Toshiba Read only semiconductor memory device and manufacturing method
JPS6472543A (en) * 1987-09-12 1989-03-17 Sony Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145955A2 (en) * 1983-11-29 1985-06-26 Kabushiki Kaisha Toshiba Read only semiconductor memory device and manufacturing method
US4649412A (en) * 1983-11-29 1987-03-10 Kabushiki Kaisha Toshiba Read only semiconductor memory device with polysilicon drain extensions
JPS6472543A (en) * 1987-09-12 1989-03-17 Sony Corp Manufacture of semiconductor device

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