JPS5537061A - Fault processing system - Google Patents
Fault processing systemInfo
- Publication number
- JPS5537061A JPS5537061A JP11031578A JP11031578A JPS5537061A JP S5537061 A JPS5537061 A JP S5537061A JP 11031578 A JP11031578 A JP 11031578A JP 11031578 A JP11031578 A JP 11031578A JP S5537061 A JPS5537061 A JP S5537061A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- fault
- access
- processors
- exchange
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/241—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for stored program controlled exchanges
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multi Processors (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Exchange Systems With Centralized Control (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To limit the effect of the fault for the multi-processor control exchange system by giving the fault processing through one of the central processors in case some fault occurs at the network control processor and performing the exchange process with other processors. CONSTITUTION:For instance, if some fault occurs at processor 2-1, the fault is informed to fault processor 3-0. And processor 3-0 sets up the blocking flag concerning processor 2-1 on the blocking flag holding register 14 at interface part 4. Thus the access to processor 2-1 is inhibited when the occupancy process is given for bus 6 in view of securing an access to processor 2-1 while the general exchange action is performed by central processor 3-j, 3-k and others. And the relation call process to processor 2-1 is held by queuing matrix buffer 15-j and others.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53110315A JPS5947908B2 (en) | 1978-09-08 | 1978-09-08 | Failure handling method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53110315A JPS5947908B2 (en) | 1978-09-08 | 1978-09-08 | Failure handling method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5537061A true JPS5537061A (en) | 1980-03-14 |
JPS5947908B2 JPS5947908B2 (en) | 1984-11-22 |
Family
ID=14532591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53110315A Expired JPS5947908B2 (en) | 1978-09-08 | 1978-09-08 | Failure handling method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5947908B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5750064A (en) * | 1980-07-11 | 1982-03-24 | Raytheon Co | Distribution signal processing system |
JPS5963851A (en) * | 1982-10-04 | 1984-04-11 | Matsushita Electric Ind Co Ltd | Electronic exchange |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6420518U (en) * | 1987-07-25 | 1989-02-01 |
-
1978
- 1978-09-08 JP JP53110315A patent/JPS5947908B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5750064A (en) * | 1980-07-11 | 1982-03-24 | Raytheon Co | Distribution signal processing system |
JPS636894B2 (en) * | 1980-07-11 | 1988-02-12 | Raytheon Co | |
JPS5963851A (en) * | 1982-10-04 | 1984-04-11 | Matsushita Electric Ind Co Ltd | Electronic exchange |
Also Published As
Publication number | Publication date |
---|---|
JPS5947908B2 (en) | 1984-11-22 |
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