JPS5534742A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5534742A
JPS5534742A JP10752378A JP10752378A JPS5534742A JP S5534742 A JPS5534742 A JP S5534742A JP 10752378 A JP10752378 A JP 10752378A JP 10752378 A JP10752378 A JP 10752378A JP S5534742 A JPS5534742 A JP S5534742A
Authority
JP
Japan
Prior art keywords
address
extension
basic
memory unit
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10752378A
Other languages
Japanese (ja)
Inventor
Kazuo Furukawa
Hiroshi Dewa
Takeshi Masuda
Keisuke Mise
Masakatsu Nunotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP10752378A priority Critical patent/JPS5534742A/en
Publication of JPS5534742A publication Critical patent/JPS5534742A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increse the number of constitutions to enhance random access capability by providing means, which convert address assignment, correspondingly to the number of extended units and receiving mount indication signals from an extension unit part and performing address assignment conversion in a basic part.
CONSTITUTION: Extension memory unit part 3 is added to the basic constitution consisting of memory control part 1 and basic memory unit part 2 at an extension time. As the addressing mode in the memory unit part, an addressing method is adopted where addresses are arranged in basic part 2 and extension part 3 alternately for every specific number of words at the extension time. Respective memory unit parts 2 and 3 can perform simultaneous independent operations. Then, address data from an external device is converted to an physical address (an address obtained by deciding data as a basic part address or an extension part address) through logical address register 11 by address conversion circuit 12. This conversion mode is different by mount indication signal 17.
COPYRIGHT: (C)1980,JPO&Japio
JP10752378A 1978-09-04 1978-09-04 Memory control system Pending JPS5534742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10752378A JPS5534742A (en) 1978-09-04 1978-09-04 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10752378A JPS5534742A (en) 1978-09-04 1978-09-04 Memory control system

Publications (1)

Publication Number Publication Date
JPS5534742A true JPS5534742A (en) 1980-03-11

Family

ID=14461342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10752378A Pending JPS5534742A (en) 1978-09-04 1978-09-04 Memory control system

Country Status (1)

Country Link
JP (1) JPS5534742A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131321A (en) * 1985-12-04 1987-06-13 Nec Corp Magnetic memory device
JPS62217319A (en) * 1986-03-18 1987-09-24 Nec Corp Access control system for disk device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131321A (en) * 1985-12-04 1987-06-13 Nec Corp Magnetic memory device
JPS62217319A (en) * 1986-03-18 1987-09-24 Nec Corp Access control system for disk device

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