JPS55117800A - Memory supervisory system - Google Patents

Memory supervisory system

Info

Publication number
JPS55117800A
JPS55117800A JP2498779A JP2498779A JPS55117800A JP S55117800 A JPS55117800 A JP S55117800A JP 2498779 A JP2498779 A JP 2498779A JP 2498779 A JP2498779 A JP 2498779A JP S55117800 A JPS55117800 A JP S55117800A
Authority
JP
Japan
Prior art keywords
memory
written
pattern
period
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2498779A
Other languages
Japanese (ja)
Inventor
Toshio Hanabatake
Hiroshi Yasuda
Yoshiichiro Inamura
Mitsuo Nishiwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2498779A priority Critical patent/JPS55117800A/en
Publication of JPS55117800A publication Critical patent/JPS55117800A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To enable a supervision over a memory in online mode by sequentially changing write addresses of a supervisory pattern by writing and reading the supervisory pattern in and from the memory.
CONSTITUTION: Into input data Din, frame synchronizing signal FS is inserted in each frame period F and when capacity M of memory 1 is l shorter than the length of data including signal FS, supervisory pattern SV is inserted at a signal FS position and written in memory 1. As a result, pattern SV is written at 1st address #0 and at #1 in the next period, and the address where SV is written is advanced in sequence in every period. Then, SV written at all addresses of memory 1 is read out in the next period and collated 5 and when a dissidence result of the collation is obtained, alarm signal alm is generated 6.
COPYRIGHT: (C)1980,JPO&Japio
JP2498779A 1979-03-02 1979-03-02 Memory supervisory system Pending JPS55117800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2498779A JPS55117800A (en) 1979-03-02 1979-03-02 Memory supervisory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2498779A JPS55117800A (en) 1979-03-02 1979-03-02 Memory supervisory system

Publications (1)

Publication Number Publication Date
JPS55117800A true JPS55117800A (en) 1980-09-10

Family

ID=12153323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2498779A Pending JPS55117800A (en) 1979-03-02 1979-03-02 Memory supervisory system

Country Status (1)

Country Link
JP (1) JPS55117800A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250550A (en) * 1988-08-11 1990-02-20 Nec Corp Memory monitoring equipment
JPH02163852A (en) * 1988-12-16 1990-06-25 Nec Corp Memory monitor system
JPH08123738A (en) * 1994-10-24 1996-05-17 Nec Corp Random access memory monitoring system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250550A (en) * 1988-08-11 1990-02-20 Nec Corp Memory monitoring equipment
JPH02163852A (en) * 1988-12-16 1990-06-25 Nec Corp Memory monitor system
JPH08123738A (en) * 1994-10-24 1996-05-17 Nec Corp Random access memory monitoring system

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