JPS5478964A - Selection circuit - Google Patents

Selection circuit

Info

Publication number
JPS5478964A
JPS5478964A JP14607577A JP14607577A JPS5478964A JP S5478964 A JPS5478964 A JP S5478964A JP 14607577 A JP14607577 A JP 14607577A JP 14607577 A JP14607577 A JP 14607577A JP S5478964 A JPS5478964 A JP S5478964A
Authority
JP
Japan
Prior art keywords
logic
terminal
leads
turned
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14607577A
Other languages
Japanese (ja)
Inventor
Katsuo Mori
Yuhei Abe
Nobuo Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14607577A priority Critical patent/JPS5478964A/en
Publication of JPS5478964A publication Critical patent/JPS5478964A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16557Logic probes, i.e. circuits indicating logic state (high, low, O)

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce the number of input terminals for the integrated circuit, by providing the switch element where the control terminal is connected to the input terminal fed and selected with three different voltages of high, medium and low, and the switch element controlled with the voltage fed to the input terminal. CONSTITUTION:When the common terminal 25 of the selection switch 21 is connected to the selection terminal 22, transistor Tr26 is turned off and Tr27 is turned on, and only the logic of the leads 15 of the logic circuit of the integrated circuit 19 is at H and the logic of the leads 16 and 17 is at L. When the common terminal 25 is connected to the selection terminal 23, Tr26 and 27 are turned on an they are both in saturation, and the logic of the leads 15 and 17 is at L, and only the logic of the lead 16 is at H. When the common terminal 25 is connected to the selection terminal 24, Tr26 is turned on and Tr27 is turned off, the logic of the leads 15 and 16 is at L, and only the logic of the leads 17 is at H. Thus, the selection circuit of three stages can be constituted with one input terminal.
JP14607577A 1977-12-07 1977-12-07 Selection circuit Pending JPS5478964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14607577A JPS5478964A (en) 1977-12-07 1977-12-07 Selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14607577A JPS5478964A (en) 1977-12-07 1977-12-07 Selection circuit

Publications (1)

Publication Number Publication Date
JPS5478964A true JPS5478964A (en) 1979-06-23

Family

ID=15399527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14607577A Pending JPS5478964A (en) 1977-12-07 1977-12-07 Selection circuit

Country Status (1)

Country Link
JP (1) JPS5478964A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746323U (en) * 1980-08-28 1982-03-15
JPS5857821A (en) * 1981-10-01 1983-04-06 Matsushita Electric Ind Co Ltd Switch circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015254A (en) * 1975-12-04 1977-03-29 General Motors Corporation Keyboard encoding circuit utilizing an A/D converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015254A (en) * 1975-12-04 1977-03-29 General Motors Corporation Keyboard encoding circuit utilizing an A/D converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746323U (en) * 1980-08-28 1982-03-15
JPS5857821A (en) * 1981-10-01 1983-04-06 Matsushita Electric Ind Co Ltd Switch circuit

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