JPS5447544A - Fault diagnosis system - Google Patents

Fault diagnosis system

Info

Publication number
JPS5447544A
JPS5447544A JP11419877A JP11419877A JPS5447544A JP S5447544 A JPS5447544 A JP S5447544A JP 11419877 A JP11419877 A JP 11419877A JP 11419877 A JP11419877 A JP 11419877A JP S5447544 A JPS5447544 A JP S5447544A
Authority
JP
Japan
Prior art keywords
diagnosis
bus
internal
register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11419877A
Other languages
Japanese (ja)
Inventor
Yasushi Ikeda
Junichi Tanahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11419877A priority Critical patent/JPS5447544A/en
Publication of JPS5447544A publication Critical patent/JPS5447544A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To decrease the quantity of hardware by using the internal common bus as the scan-in/scan-out bus and also installing the control signal selecting device which transmits the diagnosis control signal from the fault diagnosis device to each part of the data processor.
CONSTITUTION: In the diagnosis mode, the control signal is transmitted from the diagnosis device to each part of the data processor via diagnosis control register 5 and diagnosis control circuit 6. The diagnosis data is set to internal device 2-1 and 2-2 via diagnosis data register 4, bus register 3-1 and internal common bus 1-1, and the state information of the internal device is transmitted to the diagnosis device via bus 1-2, bus register 3-2 and register 4. Important information holding internal device 2-3 is connected to internal common bus 1-1 and 1-2 via the 2-way bus. The diagnosis data can be set to internal device 2-3 from any one of the internal common buses, and the contents can be read out freely. As a result, the exclusive scan bus becomes unnecessary, thus simplifying the device
COPYRIGHT: (C)1979,JPO&Japio
JP11419877A 1977-09-22 1977-09-22 Fault diagnosis system Pending JPS5447544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11419877A JPS5447544A (en) 1977-09-22 1977-09-22 Fault diagnosis system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11419877A JPS5447544A (en) 1977-09-22 1977-09-22 Fault diagnosis system

Publications (1)

Publication Number Publication Date
JPS5447544A true JPS5447544A (en) 1979-04-14

Family

ID=14631649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11419877A Pending JPS5447544A (en) 1977-09-22 1977-09-22 Fault diagnosis system

Country Status (1)

Country Link
JP (1) JPS5447544A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173855A (en) * 1983-03-24 1984-10-02 Nec Corp Logical device diagnosing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173855A (en) * 1983-03-24 1984-10-02 Nec Corp Logical device diagnosing system
JPS6341098B2 (en) * 1983-03-24 1988-08-15 Nippon Electric Co

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