JPH1140538A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which enables anisotropic and selective etching at a low cost. SOLUTION: Ar<+> 43 is ion-doped in the portions not covered with a polycrystal Si film 41 in SiO2 films 37 and 38. Then, wet etching is performed on the SiO2 films 37 and 38 with the polycrystal Si film 41 as a mask. By damage due to the ion doping, the etch rate in the portions not covered with the polycrystal Si film 41 is higher than that in portions covered with the polycrystal Si film 41. Thus, the anisotropic and selective etching can be performed in low-cost wet etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which performs a process of leaving a lower layer film in the same pattern as an upper layer film.

[0002]

2. Description of the Related Art FIGS. 3 to 5 show a conventional example of a method of manufacturing a semiconductor device in which a low breakdown voltage NMOS transistor and a high breakdown voltage NMOS transistor are mixedly mounted. In this conventional example, as shown in FIG. 3A, an N-type Si substrate 11 is formed.
P-well 12 for high-breakdown-voltage NMOS transistor and LO
An SiO ₂ film 13 as a COS oxide film and a P well 14 for a low breakdown voltage NMOS transistor are formed.

After that, an SiO ₂ film 15 which becomes a part of a gate oxide film for a high-breakdown-voltage NMOS transistor is formed on the surface of the element active region surrounded by the SiO ₂ film 13 by thermal oxidation. Opening 16 in the formation area
A photoresist 16 having a is formed by photolithography. Then, as shown in FIG. 3B, using the photoresist 16 as a mask, the SiO ₂ film 15 is formed with a hydrofluoric acid-based chemical.
Is removed, and then the photoresist 16 is removed.

[0004] Next, FIG. 4 as shown in (a), thermal oxidation is performed again, SiO ₂ as a gate oxide film for the low voltage NMOS transistor on the surface of the element active regions SiO ₂ film 15 is removed At the same time as the formation of the film 17, the thickness of the SiO ₂ film 15 remaining on the surface of the element active region is increased to form an SiO ₂ film 18 as a gate oxide film for a high breakdown voltage NMOS transistor.

The thicknesses of the SiO ₂ films 17 and 18 are designed to withstand the respective operating voltages of the low breakdown voltage NMOS transistor and the high breakdown voltage NMOS transistor. After that, when the impurity is added at a high concentration and the sheet resistance becomes 1
A polycrystalline Si film 21 of about 0 to 40 Ω / □ is deposited by a CVD method, and the polycrystalline Si film 21 is processed into a pattern of a gate electrode by photolithography and RIE.

[0006] Next, as shown in FIG.
A photoresist 22 having an opening 22a in a region where an OS transistor is to be formed is formed by photolithography, and an RI using the polycrystalline Si film 21 and the photoresist 22 as a mask is formed.
E removes the SiO ₂ film 17.

Next, as shown in FIG. 5A, after the photoresist 22 is peeled off, a photoresist 23 having an opening 23a in the formation region of the high breakdown voltage NMOS transistor is formed by photolithography. Crystal Si film 21
And SiO 2 by RIE using photoresist 23 as a mask
_{2 The} film 18 is removed. Then, as shown in FIG.
The photoresist 23 is stripped.

Thereafter, although not shown, the SiO ₂
An SiO ₂ film as a sacrificial oxide film having a uniform thickness is formed again on the surface of the element active region from which the films 17 and 18 have been removed, and a source / drain is formed by ion implantation of impurities through the SiO ₂ film. Thus, a low breakdown voltage NMOS transistor and a high breakdown voltage NMOS transistor are completed.

By the way, in order to form a source / drain by ion implantation of impurities through SiO ₂ films 17 and 18 as gate oxide films, the thin film thickness of the SiO ₂ film 17 for a low breakdown voltage NMOS transistor is used as a reference. When the ion implantation acceleration energy is determined by
Impurities cannot be ion-implanted into the formation region of the high breakdown voltage NMOS transistor in which the _two films 18 are formed, so that the source / drain cannot be formed.

On the contrary, when the acceleration energy of the ion implantation is determined based on the thick film thickness of the SiO ₂ film 18 for the high breakdown voltage NMOS transistor, the Si
In the formation region of the low-breakdown-voltage NMOS transistor in which the O ₂ film 17 is formed, the source / peak where the peak concentration is too deep is located.
A drain is formed, and impurities diffuse in the lateral direction from the source / drain, so that a short channel effect is remarkably generated in the low breakdown voltage NMOS transistor.

However, in the above-described conventional example, the polycrystalline Si film 2 of the SiO ₂ films 17 and 18 serving as the gate oxide film is used.
The portion not covered by 1 is once removed, and then a SiO ₂ film as a sacrificial oxide film having a uniform thickness is formed again, and the source / ion is implanted by ion implantation of impurities through the SiO ₂ film as the sacrificial oxide film. Since a drain is formed, a low breakdown voltage NMOS transistor and a high breakdown voltage NMOS transistor can be formed by one ion implantation.
An appropriate depth of source / drain can be formed in both the transistor and the transistor.

Further, in the above-mentioned conventional example, the polycrystalline Si
R using the film 21 and the photoresists 22 and 23 as a mask
Since the SiO ₂ films 17 and 18 are removed by anisotropic etching by IE, the portions of the SiO ₂ films 17 and 18 that are covered with the polycrystalline Si film 21 are not side-etched and serve as gate electrodes. The SiO ₂ films 17 and 18 can be left under the polycrystalline Si film 21 in the same pattern as the polycrystalline Si film 21.

Therefore, the characteristics are degraded due to the variation of the effective gate length from the design value, and the polycrystalline S
It is possible to manufacture a semiconductor device in which a low-breakdown-voltage NMOS transistor and a high-breakdown-voltage NMOS transistor are mounted together without causing a reduction in reliability due to a short circuit between the i-film 21 and the Si substrate 11.

On the other hand, when removing the SiO ₂ films 17 and 18, the RI under the condition based on the thin SiO ₂ film 17 is used.
When E is also applied to the thick SiO ₂ film 18, the SiO ₂ film 18 remains even after RIE is completed. Conversely, if the RIE under the condition based on the thick SiO ₂ film 18 is also applied to the thin SiO ₂ film 17, the RIE continues even after the SiO ₂ film 17 is removed. The Si substrate 11 is damaged, and the characteristics are degraded due to junction leakage and the like.

However, in the conventional example described above, FIG.
And as shown FIG. 5 (a), to remove the SiO ₂ films 17 and 18, polycrystalline addition to the photoresist 22, or separate RIE the SiO ₂ film using a photoresist 23 as a mask of the Si film 21 Since the steps 17 and 18 are performed, the optimum conditions for each RIE can be adopted, and the occurrence of damage in the Si substrate 11 can be prevented.

[0016]

However, in the above-mentioned conventional example, RIE is performed to anisotropically etch the SiO ₂ films 17 and 18 which are gate oxide films.
Since dry etching such as E is higher in cost than wet etching, it has been difficult to manufacture a semiconductor device at low cost.

In the above-mentioned conventional example, the SiO ₂ film 1
In order to remove 7, 18 a separate RIE using the photoresist 22 or photoresist 23 as a mask
Since the O ₂ films 17 and 18 are applied, the number of photomasks and the number of manufacturing steps are large, which also makes it difficult to manufacture a semiconductor device at low cost. Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can perform anisotropic and selective etching at low cost.

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a second film having a pattern narrower than the first film on the first film; Performing ion implantation on a portion of the film not covered by the second film, and performing wet etching on the first film using the second film as a mask after the ion implantation. Are provided.

In the method of manufacturing a semiconductor device according to the first aspect, since the ion implantation is performed on a portion of the first film which is not covered with the second film, the first film is damaged by the ion implantation. Among them, the etching rate of the portion not covered by the second film is higher than the etching speed of the portion covered by the second film.

For this reason, after the ion implantation, although the first film is wet-etched using the second film as a mask, a portion of the first film which is covered by the second film. That is not covered by the second film can be etched anisotropically and selectively without substantially side-etching, leaving the first film in the same pattern as the second film. Can be.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a gate insulating film is formed by the first film, and a gate electrode is formed by the second film.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the portion of the gate insulating film covered with the gate electrode is substantially removed, although the gate insulating film is wet-etched using the gate electrode as a mask. The portion not covered by the gate electrode can be anisotropically and selectively etched without side etching, so that the gate insulating film can be left in the same pattern as the gate electrode.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
According to a second aspect of the present invention, in the method for manufacturing a semiconductor device, a plurality of types of gate insulating films are formed by the first film.

In the method of manufacturing a semiconductor device according to the third aspect, the gate insulating film having a plurality of thicknesses is formed, but the gate insulating film is left in the same pattern as the gate electrode by wet etching using the gate electrode as a mask. Therefore, the process of leaving the gate insulating film in the same pattern as the gate electrode can be performed simultaneously on the entire gate insulating film without causing damage to the base of the gate insulating film.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed with an electrically inactive ion species.

In the method of manufacturing a semiconductor device according to claim 4, ions are implanted into the first film in order to leave the first film in the same pattern as the second film. Since the active ion species is used, even if the ion species is implanted up to the base of the first film, the sheet resistance of the base does not change.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of a semiconductor device in which a low-breakdown-voltage NMOS transistor and a high-breakdown-voltage NMOS transistor are mixed will be described below.
This will be described with reference to FIGS. In this embodiment, as shown in FIG. 1A, an N-type Si substrate 31 has a high breakdown voltage NM.
A P well 32 for an OS transistor, a SiO ₂ film 33 as a LOCOS oxide film, and a P well 34 for a low breakdown voltage NMOS transistor are formed.

Thereafter, a 100-200 nm-thick S film which becomes a part of a gate oxide film for a high breakdown voltage NMOS transistor is formed on the surface of the element active region surrounded by the SiO ₂ film 33.
The iO ₂ film 35 is formed by steam oxidation at about 900 to 1000 ° C., and a photoresist 36 having an opening 36 a in a formation region of the low breakdown voltage NMOS transistor is formed by photolithography.

Next, as shown in FIG. 1B, using the photoresist 36 as a mask, the SiO ₂ film 35 is etched with a hydrofluoric acid-based chemical.
Is removed, and then the photoresist 36 is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution.

Next, as shown in FIG.
The steam oxidation at about 000 ° C. is performed again to obtain the SiO ₂ film 3.
5 is formed on the surface of the element active region from which the gate oxide film for the low breakdown voltage NMOS transistor has a thickness of 10 to 50 n.
at the same time to form an SiO ₂ film 37 m, to form the SiO ₂ film 38 as a gate oxide film for thicker to high voltage NMOS transistor the thickness of the SiO ₂ film 35 is left on the surface of the element active region .

The thicknesses of the SiO ₂ films 37 and 38 are designed to withstand the respective operating voltages of the low breakdown voltage NMOS transistor and the high breakdown voltage NMOS transistor. After that, when the impurity is added at a high concentration and the sheet resistance becomes 1
A polycrystalline Si film 41 of about 0 to 40 Ω / □ is deposited by a CVD method, and a photoresist 42 having a gate electrode pattern is formed on the polycrystalline Si film 41 by photolithography.

Thereafter, RIE using the photoresist 42 as a mask is performed on the polycrystalline Si film 41, and the photoresist 4
Ar ⁺ 43 is ion-implanted into the SiO ₂ films 37 and 38 at a dose of about 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² while leaving 2 remaining. Then, the photoresist 42 is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution.

Next, as shown in FIG.
Using the film 41 as a mask, the SiO ₂ film 37 is
38 is removed. By the way, due to the damage caused by the ion implantation of Ar ⁺ 43 described above, the etching rate of the portion of the SiO ₂ films 37 and 38 not covered by the polycrystalline Si film 41 is reduced. The etching rate is higher than the etching rate, and the etching selectivity is about 10 to 15.

For this reason, the SiO ₂ film 37, 3
8 without substantially side-etching the portion covered with the polycrystalline Si film 41.
Can be etched anisotropically, selectively and simultaneously.

Thereafter, although not shown, SiO ₂
An SiO ₂ film as a sacrificial oxide film having a uniform thickness is formed again on the surface of the element active region from which the films 37 and 38 have been removed, and a source / drain and the like are formed by ion implantation of impurities through the SiO ₂ film. Thus, a low breakdown voltage NMOS transistor and a high breakdown voltage NMOS transistor are completed.

When the ions of Ar ⁺ 43 are implanted, the projection range is positioned in the SiO ₂ films 37 and 38.
Since dispersion exists at the rest position of r ⁺ 43, Ar is also present in the Si substrate 31 on which the source / drain is formed later.
⁺ 43 is injected. However, since Ar is electrically inactive, the sheet resistance of the source / drain does not change due to the ion implantation of Ar ⁺ 43.

In the above embodiment, the SiO ₂ films 37, 3
In order to anisotropically and selectively remove a portion of the substrate 8 not covered with the polycrystalline Si film 41, two steps of ion implantation of Ar ⁺ 43 and wet etching are performed. On the other hand, in the conventional example shown in FIGS. 3 to 5, the total of the formation of the photoresists 22 and 23, the RIE on the SiO ₂ films 17 and 18, and the removal of the photoresists 22 and 23 are 6 in total.
Process. Therefore, in this embodiment, the number of photomasks is smaller by two and the number of manufacturing steps is also smaller by four.

In the above embodiment, the source / drain having an appropriate depth is formed in both the low breakdown voltage NMOS transistor and the high breakdown voltage NMOS transistor by one ion implantation. For manufacturing a semiconductor device in which portions of the SiO ₂ films 37 and 38 which are different gate oxide films and which are not covered with the polycrystalline Si film 41 are once removed and a sacrificial oxide film having a uniform film thickness is formed again. Although the invention of the present application is applied, the invention of the present application can be applied to the manufacture of other semiconductor devices.

That is, since the impurity is ion-implanted with low acceleration energy to form a shallow source / drain with a small dispersion of the stationary position of the implanted ions, even if the gate oxide film has a uniform thickness, Of these, a portion not covered by the gate electrode may be removed once, and then a sacrificial oxide film thinner than the gate oxide film may be formed again. Therefore, a semiconductor device including only such a low breakdown voltage NMOS transistor The invention of the present application can also be applied to the manufacture of

Further, in addition to a semiconductor device including only NMOS transistors, a semiconductor device including only PMOS transistors, a semiconductor device including CMOS transistors,
The invention of the present application can be applied to the manufacture of an iCMOS semiconductor device and the like. In the above-described embodiment, Ar ⁺ 43 is used as an electrically inactive ion species. However, other inert gas ions and the same material as that of the Si substrate 31 are used.
An i-ion or the like may be used instead of Ar ⁺ 43.

[0041]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, although the first film is wet-etched using the second film as a mask, the second film is formed of the first film. The portion not covered by the second film can be etched anisotropically and selectively without substantially side-etching the portion covered by the second film, and the second film can be etched in the same pattern as the second film. One film can be left.

Accordingly, a semiconductor device can be manufactured at lower cost than when anisotropic dry etching is performed on the first film in order to leave the first film in the same pattern as the second film.

In the method of manufacturing a semiconductor device according to the second aspect, the portion of the gate insulating film that is covered with the gate electrode is substantially removed, although the gate insulating film is subjected to wet etching using the gate electrode as a mask. The portion not covered by the gate electrode can be anisotropically and selectively etched without side etching, so that the gate insulating film can be left in the same pattern as the gate electrode.

Therefore, it is possible to manufacture a semiconductor device at a low cost without a decrease in characteristics due to a change in the effective gate length from the design value or a decrease in reliability due to a short circuit between the gate electrode and the base.

In the method of manufacturing a semiconductor device according to the third aspect, the gate insulating film having a plurality of types of film thicknesses is formed, but the gate insulating film is made of the same material as the gate electrode without damaging the base of the gate insulating film. Since the processing to be left in the pattern can be performed simultaneously on the entire gate insulating film, the number of photomasks and the number of manufacturing steps can be reduced, and a semiconductor device without deterioration in characteristics or reliability can be manufactured at lower cost. can do.

In the method of manufacturing a semiconductor device according to claim 4, ions are implanted into the first film to leave the first film in the same pattern as the second film. Even if the ion species is implanted, the sheet resistance and the like of the base do not change, so that it is possible to manufacture a semiconductor device at a low cost without deteriorating characteristics.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing the first half of steps of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing the latter half of the process of one embodiment.

FIG. 3 is a side sectional view sequentially showing an initial step of a conventional example of the present invention.

FIG. 4 is a side sectional view sequentially showing a middle stage process of a conventional example.

FIG. 5 is a side sectional view sequentially showing a final step of a conventional example.

[Explanation of symbols]

37: SiO ₂ film (first film), 38: SiO ₂ film (first film), 41: polycrystalline Si film (second film), 43: A
r ⁺ (ion species)

Claims (4)

[Claims] A step of forming a second film having a pattern narrower than the first film on the first film; and a portion of the first film which is not covered by the second film. And a step of performing wet etching on the first film by using the second film as a mask after the ion implantation. 2. The method according to claim 1, wherein a gate insulating film is formed from the first film, and a gate electrode is formed from the second film. 3. The method according to claim 2, wherein a plurality of types of gate insulating films are formed of the first film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed using an ion species that is electrically inactive.