JPH1139245A - Semiconductor device controller and semiconductor device control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller which can be manufactured at a low cost and can flexibly cope with a change in control method by realizing access control to a semiconductor device such as the flash EEPROM with a simple hardware configuration. SOLUTION: An I/O port 111 is configured so that the port 111 may be accessed from CPU 11 for reading and writing and coupled with each signal pin of a NAND type flash EEPROM 14. Since the value of each binary data written in the port 111 by means of the CPU 11 is directly supplied to the corresponding signal pins of the EEPROM 14 as the logical values H and L of the voltage of the signal pins, each bit value of write data, address, commands, etc., as well as the 'H' and 'L' states of various kinds of control signals can be controlled directly with software.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEP.
The present invention relates to a semiconductor device control device and a semiconductor device control method for controlling a semiconductor device such as a ROM, and more particularly to a semiconductor device control device and a semiconductor device control method for controlling access to a semiconductor device used in a personal computer.

[0002]

2. Description of the Related Art Many conventional information processing apparatuses such as workstations and personal computers use a magnetic disk device as a secondary storage device. A magnetic disk device has advantages such as high recording reliability and low unit cost per bit, but has disadvantages such as a large device size and weakness against physical impact.

Therefore, in recent years, attention has been focused on a semiconductor disk device which is small in size and resistant to physical impact. A semiconductor disk device is a flash EEPROM that is a nonvolatile semiconductor memory that can be electrically erased in a batch.
The OM is used as a secondary storage device of a personal computer or the like as in a conventional magnetic disk device or the like. Since this semiconductor disk device does not include a mechanically movable part such as a magnetic head of a magnetic disk device or a rotating disk, malfunction and failure due to physical impact are unlikely to occur. Further, there is an advantage that the size of the device is reduced.

Recently, various command control type flash EEPROMs have been developed in which all operation modes can be designated by an external command.

This type of flash EEPROM has a data register for holding one page of data. The data write operation from the data register to the memory cell array and the data read operation from the memory cell array to the data register are performed from outside. Can be executed automatically without the control of. When such a command control type flash EEPROM is used by being incorporated in a semiconductor disk device, a controller for controlling the semiconductor disk device issues a command to execute the flash EEPROM.
Once the operation mode of M is specified, the control of the flash EEPROM is released thereafter.

However, the conventional controller has a configuration in which a series of signal timing controls for the flash EEPROM necessary for designating an access operation requested from the host system are all generated by dedicated hardware. There is a problem that the configuration is complicated. Further, in order to cope with a change in the access control method or the like, the hardware configuration must be redesigned, and a large amount of time and cost are required for the work.

[0007]

As described above, in the prior art, since a series of signal timing controls for the flash EEPROM are all performed by dedicated hardware, the hardware configuration becomes complicated, and the control operation is changed. It was difficult to respond flexibly to such situations.

[0008] The present invention has been made in view of such a point, and a flash E has a simple hardware configuration.
It is an object of the present invention to provide a semiconductor device control device and a semiconductor device control method which can realize access control to a semiconductor device such as an EPROM and which can flexibly cope with a change in control operation at low cost.

[0009]

According to the present invention, there is provided a semiconductor device control apparatus which is configured to be usable in a computer system and controls a semiconductor device in response to a request from a host CPU of the computer system. I / O coupled to each of a plurality of signal pins of the semiconductor device.
An O port, and the I / O
The value of each binary data written to the O port is supplied to the corresponding signal pin of the semiconductor device as its voltage value.

In this semiconductor device control apparatus,
It has an I / O port accessible by the host CPU, and the I / O port is coupled to each of a plurality of signal pins of the semiconductor device. The value of each binary data written to the I / O port by a software driver or the like is directly supplied to the corresponding signal pin of the semiconductor device as its voltage value. Accordingly, by writing data corresponding to the logic level of the signal pin to the I / O port under software control, a series of signal timings necessary for the access operation of the semiconductor device is generated. As described above, by adopting a configuration in which the access operation of the semiconductor device is directly controlled by software control, the flash E is realized with a simple hardware configuration.
Access control to a semiconductor device such as an EPROM can be realized, and it is possible to flexibly cope with a change in control operation at low cost.

Further, the I / O port can be constituted by a register having a multi-bit width. In this case, each bit of the register will be coupled to a corresponding signal pin of the semiconductor device. With this configuration, the semiconductor device can be controlled only by preparing a register having a bit width equivalent to the number of signal pins of the semiconductor device.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a flash memory controller according to an embodiment of the present invention. This flash memory controller 13 is applied to a computer system such as a personal computer, and is a NAND flash EEPROM.
14 access control.

As shown, the flash memory controller 13 includes a system bus 10 of a computer system.
In accordance with an I / O read / write cycle executed by the CPU 11 under software control stored in the main memory 12.
M14 is controlled. The flash memory controller 13 is provided with an address decoder 110 and an I / O port 111 addressed by the address decoder 110. I / O port 111 is CP
The read / write access is made possible by U11, and its I / O port 111 is connected to each signal pin of the NAND flash EEPROM 14.

That is, as shown, the I / O port 111 includes a plurality of control signal ports 112 for supplying various control signals 201 to the NAND flash EEPROM 14 and the NAND flash EEPROM 1.
4, a status port 113 for reading the status signal 201, and a NAND flash EEPROM.
14 and a data port 114 for transmitting and receiving, for example, 8-bit I / O data 203. These control signal port 112, status port 1
13 and the data port 114 are connected to the data bus 2, respectively, and these ports are selectively set to an enabled state by an address decoder 110 which decodes an address on the address bus 1.

The control signal 20 supplied to the NAND flash EEPROM 14 via the control signal port 112
1 is a command latch enable signal CLE, an address latch enable signal ALE, and a chip enable signal C
E #, a write enable signal WE #, a read enable signal RE #, and the like. Also, status port 1
13 is a ready / busy signal R / B, and the I / O data 20
What is transmitted and received as 3 is write data, read data, a command, and an address.

According to the controller 13, the CPU 1
The value of each binary data written to the I / O port 111 by 1 is supplied directly to the corresponding signal pin of the NAND type flash EEPROM 14 as the logical value H or L of the voltage, so that each control signal H , L state, and each bit value of write data, address, command, etc. can be directly controlled by software. Also, when the CPU 11 performs read access to the I / O port 111, the NAND flash EEPROM
Data and status read from the OM 14 can be read.

FIG. 2 shows an application example of the controller 13 of FIG. 1. Here, the controller 13 of FIG.
Is a controller LSI (I
(SA adapter controller). I
The SA expansion board 30 is used in a desktop type personal computer in an SSFDC (Solid State).
The ISA expansion board 3 is for enabling the use of a Floppy Disk Card 50.
The cable derived from 0 is connected to an adapter unit 40 for mounting the SSFDC 50. SS
The FDC 50 is a removable storage medium composed of a small flat resin package having a built-in NAND flash EEPROM, and as shown in FIG.
On the package surface, NAND flash EE
An electrode group connected to each signal pin of the PROM is arranged.

Next, a specific example of the I / O port 111 of FIG. 1 will be described with reference to FIG. In FIG. 3, I / O port 111 of FIG. 1 has two registers each having an 8-bit width, namely, SSFDC control register 111a and SSFDC data register 11
1b.

SSFDC control register 111a
Is a register for controlling the SSFDC50,
Bits 0 to 6 are SS
It is directly connected to the corresponding control signal electrode of FDC50.
The SSFDC control register 111a can be composed of a flip-flop or the like as usual.

The SSFDC data register 111b stores the SS
This is for controlling the 8-bit wide I / O data line of the FDC 50, and bits 0 to 7 are directly connected to the corresponding I / O signal electrodes of the SSFDC 50 as shown in the figure. This SSFDC data register 111b
Since it is not necessary to provide a latch function, it can be constituted by a bidirectional input / output buffer.

These SSFDC control registers 1
By performing read / write access to the 11a and the SSFDC data register 111b, a series of access control sequences required for data read, data write, and block erase can be realized by software control.

FIG. 5 shows the correspondence between hardware and software used in this embodiment. In FIG. 5, 70 is an application program, 80
Denotes an operating system, and 90 denotes an SSFDC software driver for controlling the SSFDC 50. SS
The FDC 50 is treated by the application program 70 and the operating system 80 as one of the disk drive devices. The SSFDC software driver 90 has a function of converting a disk address specified by the application program 70 or the operating system 80 into a memory address for accessing the SSFDC 50, for example, on a sector-by-sector basis.
It has a function of accessing the DC control register 111a and the SSFDC data register 111b to control a series of access control sequences required for data read, data write, and block erase of the SSFDC 50, respectively.

Next, referring to FIG. 6 and FIG.
The operation of reading data from the DC 50 will be described.
FIG. 6 is a signal waveform diagram of the NAND flash EEPROM at the time of data reading, and FIG. 7 shows a processing procedure of the software driver 90 at that time. In FIG. 6, (1) is a command latch enable signal CLE.
When sending a command to the NAND flash EEPROM, the SSFDC control register 111
CLE control data “1” is written to bit 2 of a,
As a result, the command latch enable signal CLE is set to the active state “1”.

(2) is a chip enable signal CE #, which is used to set the NAND flash EEPROM to the operation state when the SSFDC control register 111 is set.
CE control data “0” is written to bit 0 of “a”, whereby the chip enable signal CE # is set to the active state “0”.

(3) is a write enable signal WE #. When writing a command, address, and data to the NAND flash EEPROM, WE control data "0" is written to bit6 of the SSFDC control register 111a. Signal WE # is set to active state "0".

(4) Address latch enable signal A
LE, and when sending an address to the NAND flash EEPROM, the SSFDC control register 1
ALE control data "1" is written to bit 1 of bit 11a.
Are set to the active state “1”.

(5) is a read enable signal RE #, and when reading data from the NAND flash EEPROM, the SSFDC control register 111
RE control data “0” is written to bit 5 of “a”, whereby the read enable signal RE # is set to the active state “0”.

(6) is a ready / busy signal R / B, which becomes "0" indicating a busy state when the internal circuit of the NAND type flash EEPROM is operating, and becomes "0" when the operation is completed and the ready state is reached. 1 ". The values “0” and “1” are reflected in bit 4 of the SSFDC control register 111a.

(7) is an I / O signal line, which is SSFDC
Data register 111b and NAND flash EEP
Used to exchange commands, addresses, and data with the ROM.

Here, the write enable signal W
SS at E￣ and read enable signal RE￣
Although bits 6 and 5 of the FDC control register 111a are allocated, instead of allocating such dedicated bits, the CPU 11
Enable signal WE when write access to
ア ク テ ィ ブ becomes active, and the read enable signal RE # becomes active when a read access is made.

When reading data from the NAND flash EEPROM, the software driver 90
In order to generate the timing according to the signal waveform of FIG. 6, the SSFDC control register 1
11a and the SSFDC data register 111b are accessed.

That is, the software driver 90
First, the bi of the SSFDC control register 111a
CE control data “0” is written at t0, and the chip enable signal CE # of the NAND flash EEPROM is set to “0” (step S101). Next, the software driver 90 writes CLE control data “1” to bit 2 of the SSFDC control register 111a, and sets the command latch enable signal CLE to “1” (step S102). Thereafter, the software driver 90 writes a read command “00h” to the SSFDC data register 111b, and writes CLE control data “0” to bit2 of the SSFDC control register 111a (steps S103, S104). As a result, the write enable signal WE # becomes "0", and the read command "00h" is written in the NAND flash EEPROM.

Next, the software driver 90
AL is set to bit 1 of the FDC control register 111a.
The E control data "1" is written, and the address latch enable signal ALE is set to "1" (step S105).
Then, a 24-bit memory read address is sequentially written into the SSFDC data register 111b three times (step S106). The write enable signal WE # becomes "0" in synchronization with the writing of the memory read address, whereby the memory read address written in the SSFDC data register 111b is written in the NAND flash EEPROM.

After that, the software driver 90
AL is set to bit 1 of the FDC control register 111a.
After writing the E control data "0" to set the address latch enable signal ALE to "0" (step S10
7), bi of SSFDC control register 111a
Polling t4, NAND flash EEPROM
It waits until data is read out to the OM data register and changes from the busy state to the ready state (step S108). When the NAND flash EEPROM enters the ready state, the software driver 90
The DC data register 111b is sequentially read (step S109). In synchronization with this read access, NAND
Enable signal RE of the flash EEPROM
順次 sequentially become “0”, whereby, for example, data for one page can be continuously read.

FIGS. 8 and 9 are waveform diagrams at the time of data writing and block erasing, respectively. The SSFDC control register 111a and the SSFDC data register 111 follow the timings of these waveform diagrams.
By performing access b, data writing and erasing operations to the NAND flash EEPROM can also be controlled.

As described above, according to the present embodiment, by writing data corresponding to the logic level of each signal pin of the NAND flash EEPROM to the I / O port under software control, the NAND flash E
A series of signal timings required for the EPROM access operation are generated. As described above, since the access operation of the NAND flash EEPROM can be directly controlled by software control, access control to the flash EEPROM can be realized with a simple hardware configuration, and the cost is low and the control operation can be flexibly changed. Can be handled.

In the above description, the flash EEPROM is used.
Although only the control for the OM has been described, the control of this embodiment can be applied to not only the flash EEPROM but also various other semiconductor devices.

[0038]

As described above, according to the present invention,
By employing a configuration in which software directly writes data for determining the logic level of each signal pin of the semiconductor device to an I / O port accessible by the host CPU, the hardware configuration is simplified, the cost is reduced, and the control method is reduced. It is possible to flexibly cope with the change of.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device control device according to an embodiment of the present invention.

FIG. 2 shows a semiconductor device control apparatus according to the same embodiment as SSF.
The figure which shows the example applied to the DC controller.

FIG. 3 is an exemplary view showing the configuration of an SSFDC used in the embodiment.

FIG. 4 is an exemplary view showing a specific configuration example of an I / O port provided in the semiconductor device control device of the embodiment.

FIG. 5 is an exemplary view showing a correspondence relationship between the semiconductor device control apparatus according to the embodiment and software drivers controlling the semiconductor device control apparatus;

FIG. 6 shows a flash E of SSFDC in the embodiment.
FIG. 6 is a waveform chart showing timing when data is read from an EPROM.

FIG. 7 is a flowchart showing a processing procedure of a software driver corresponding to the data read timing of FIG. 6;

FIG. 8 shows a flash E of SSFDC in the embodiment.
FIG. 4 is a waveform chart showing timing when data is written to an EPROM.

FIG. 9 shows a flash E of SSFDC in the embodiment.
FIG. 9 is a waveform chart showing timing when an EPROM executes a block erase operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Address bus 2 ... Data bus 11 ... Host CPU 12 ... Main memory 13 ... Flash memory controller 14 ... NAND flash EEPROM 20 ... Desktop personal computer 30 ... ISA board 40 ... Adapter unit 50 ... SSFDC 111 ... I / O port 112: control signal port 113: status port 114: data port 111a: SSFDC control register 111b: SSFDC data register

Claims (7)

[Claims] 1. A semiconductor device controller configured to be usable in a computer system and controlling a semiconductor device in response to a request from a host CPU of the computer system, wherein the semiconductor device controller is configured to be accessible by the host CPU. A plurality of I / O ports coupled to each of the plurality of signal pins, and a value of each binary data written to the I / O port by the host CPU is applied to a corresponding signal pin of the semiconductor device by the voltage thereof. A semiconductor device control device supplied as a value. 2. The I / O port of claim 1, wherein the I / O port comprises a multi-bit register, each bit of the register being coupled to a corresponding signal pin of the semiconductor device. Semiconductor device controller. 3. The semiconductor device according to claim 2, wherein the semiconductor device is a flash EEP.
2. The semiconductor device control device according to claim 1, further comprising a ROM. 4. The semiconductor device according to claim 1, wherein said semiconductor device is a flash EEP.
A first register having a multi-bit width coupled to each of a plurality of control signal pins of the flash EEPROM; and a plurality of I / O signal pins of the flash EEPROM. A second register having a multi-bit width, wherein the second register comprises a bidirectional input / output buffer for transmitting / receiving a command, an address, and data to / from the plurality of I / O signal pins. 2. The semiconductor device control device according to claim 1, wherein 5. A semiconductor device control method used in a computer system having an I / O port coupled to each of a plurality of signal pins of a semiconductor device, wherein the host computer responds to an access request from a host program. Of the plurality of signal pins of the semiconductor device are sequentially written to the I / O port, and a series of necessary operations for executing an access operation requested from a host program are performed. A method of controlling a semiconductor device, wherein a signal timing can be generated by software control. 6. The I / O port comprises a multi-bit wide register in which each bit is coupled to a corresponding signal pin of the semiconductor device, and generates a series of signal timings by accessing the register. 6. The method of controlling a semiconductor device according to claim 5, wherein: 7. The semiconductor device according to claim 7, wherein the semiconductor device is a flash EEP.
A semiconductor disk device including a ROM, wherein a disk address specified by an access request from the host program is converted into a memory address for accessing the flash EEPROM, and the memory address is written to the I / O port. The semiconductor device control method according to claim 5, wherein