JPH11214520A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for dynamically restructuring a circuit function by enabling the circuit function of an FPGA core to be changed to a desired condition by programming corresponding to external operation condition change input in a working condition where the power supply of an LSI circuit is supplied. SOLUTION: In a semiconductor integrated circuit with an FPGA core 10 in a semiconductor integrated circuit, the FPGA core that can be rewritten repeatedly and has a rewriting interface circuit is provided, and a writing control means is provided where corresponding program data are received from an external storage medium 20 by the specification of a circuit program corresponding to the FPGA core 10 and the data are written to the FPGA core.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (LSI) having an FPGA core used for interfacing with peripheral circuits on an LSI chip of the semiconductor integrated circuit (LSI).

[0002]

2. Description of the Related Art A conventionally known technique is disclosed in Japanese Patent Laid-Open No.
No. 24300 discloses a semiconductor integrated circuit. This will be described below with reference to this.

FIG. 3 is a configuration diagram on an LSI chip of the above-mentioned known technology. The configuration of the LSI chip of FIG. 3 includes a modularized CPU core, memory, standard cells, FP
It consists of modules for GA and other peripheral circuits. This L
The FPGA in the SI is an evaluation LSI (evaluation chip), and is replaced with a logic circuit and fixed wiring at the stage of finally becoming an LSI chip, and is used for mass production LSI.
Becomes

A difference from an FPGA (field programmable gate array) according to the present invention will be described. The FPGA shown in FIG. 3 changes the logic design,
The wiring pattern can be changed at any time, and the logic of the newly developed functional blocks can be corrected on site (field) as needed.
The main purpose is to enable SI evaluation in a short time. The FPGA is a gate array that allows the user to program and rewrite the internal wiring / functional circuit as desired.

[0005] In addition, the rewriting of the program contents for the FPGA is performed based on the evaluation result by correcting the program of the logic design part which becomes a bug. That is, the program is modified via a writing means so as to achieve the target function. As a result, repeated evaluation debugging can be performed in a short period of time. That is, it is used as a substitute for a newly developed functional block. The above-mentioned rewriting mode to the FPGA generally uses a nonvolatile memory element such as an EEPROM which does not disappear even when the power is turned off.

[0006]

As described above, in the prior art, an FPGA core is mounted for the main purpose of evaluating and debugging an LSI. By the way, FIG.
As shown in the configuration of (a), there is an example of an apparatus configuration for transferring stored data from the disk 100 to the memory 300 via the data converter 200 at high speed. This is used, for example, in a pattern generator of a semiconductor test apparatus. Disk 100
Has a buffer memory and is fast, for example, 10M words /
Outputs data at a transfer rate of seconds. Data converter 200
Receives the read data, converts it into a data form corresponding to the setting conditions in the selection register, and then, together with a control signal for writing and an address signal to the memory,
Supply to FIG. 4B shows an example of data format conversion.
As shown in FIG.
It is necessary to provide a number of other conversion forms, such as a format conversion for switching to the side, and a predetermined bit shift conversion for aligning the bit string of the scan pattern. This is converted every clock of, for example, 10 MHz or continuously converted by pipeline processing and output. Therefore, it is necessary to provide a dedicated circuit only for the type of conversion mode. The memory 300 is a long pattern memory used for a pattern generator or the like.

[0007] Next, FIG.
An example of a simple configuration integrated on SI is shown. This configuration is
It comprises a PU core 60, a selection register 65, and peripheral function modules 51-59. The address generator is not included. The selection register 65 is a register that mainly determines what format is to be converted and written to the memory, and the peripheral function module is selected and designated thereby. The CPU core 60 is a controller, which is mainly used for management for controlling the transfer operation, and changes the setting of the selection register 65 every time an external operation condition change input is received, and corresponds to DMA transfer. Like, memory 300
A transfer start physical address is generated to prepare for high-speed transfer. The selection register 65 is a peripheral function module 5
Setting registers 1 to 59 are selectively operable. Only one or several peripheral modules among these operate at the same time, and the remaining many unselected peripheral modules are idle.

[0008] The individual peripheral function modules 51 to 59
This is a functional circuit capable of high-speed operation specialized for a certain data conversion purpose, and a high-speed conversion circuit circuit circuit logic such as data conversion processing, scan data conversion, and stream conversion. These functional circuits are required to perform high-speed conversion and transfer output at a clock cycle of, for example, 10 MHz. Therefore, even if similar conversion functions cannot be followed in high-speed operation, they are provided as individual peripheral function modules. There is a need. As a result, the number of peripheral function modules 51 to 59 to be provided increases. As a result, the circuit scale increases, which makes it difficult to accommodate the LSI, or increases the scale and costs. When a new data conversion mode is required, a corresponding new LSI is required. There are practical difficulties from these viewpoints. Therefore, the problem to be solved by the present invention is that in the operating state where the power of the LSI circuit is supplied, the circuit function of the FPGA core can be changed to a desired condition in response to an external operation condition change input. It is an object of the present invention to provide a semiconductor integrated circuit capable of dynamically reconfiguring circuit functions.

[0009]

FIG. 1 shows a solution according to the present invention. First, in order to solve the above-mentioned problem, in the configuration of the present invention, a semiconductor integrated circuit having an FPGA core in a semiconductor integrated circuit (LSI) includes an FPGA core 10 that can be repeatedly rewritten and has a rewrite interface circuit. The semiconductor integrated circuit further includes a write control unit that receives the corresponding program data from the external storage medium 20 and writes the FPGA core 10 in accordance with designation of a circuit program for the FPGA core. According to the above invention, the LSI
In the operation state where the power of the circuit is supplied, the circuit function of the FPGA core which determines the circuit function of the interface in the LSI in response to the input of the operation condition change from the outside can be program-changeable to a desired condition and dynamically. A semiconductor integrated circuit can be realized in which the circuit function can be reconfigured to greatly reduce the size of the pause circuit inside the LSI.

Second, in order to solve the above-mentioned problem, the configuration of the present invention is to make it possible to dynamically reset the circuit function of the FPGA core 10 when the power is supplied and the LSI circuit is in an operating state. There is the above-mentioned semiconductor integrated circuit as a feature. Further, there is the above-mentioned semiconductor integrated circuit, wherein the write / hold memory cell of the rewritable FPGA core 10 is an EEPROM or a RAM.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

FIG. 1 is a block diagram showing one embodiment of the present invention. The configuration consists of a controller section inside the LSI and an FPGA
And a storage medium 20 outside the LSI.

The storage medium 20 is stored in the storage medium as many as the number of peripheral function modules required for the write program data (configuration data) for making the FPGA unit function equivalently to the conventional peripheral function module. I have. As the storage medium 20, a disk or a memory is used.
It is supplied to the CPU core in the SI.

The controller in the LSI is a CPU core 6
0, a control memory 62, and a selection register 65.
This adds the following functions to the conventional functional elements. In other words, in order to receive the setting conditions in the selection register 65 and to program the FPGA unit to the corresponding circuit logic via the write control line, the write interface control with the FPGA unit and the program data from the storage medium 20 are performed. External interface control for receiving the information.
The control memory 62 is a program storage memory and a work RAM used for the CPU core 60.

The FPGA section is a rewriteable FPG.
The A core 10 is housed in an LSI, and the program contents can be changed from the CPU core 60 at any time via a write control line and a rewrite interface circuit in the FPGA core. Since the FPGA and its write control are well known in the art, the description thereof is omitted. Where F
It goes without saying that the PGA needs to use an FPGA core having a scale capable of realizing any conventional peripheral function module by a program, but the circuit scale can be greatly reduced. As a memory cell for holding write information of the FPGA, a RAM having no limitation on the number of times of writing is preferable, but an EEPROM may be used.

With the above configuration, for example, in the case of format conversion for exchanging the arrangement of word data shown in FIG. 4B, the connection conditions between the input terminal and the output terminal of the LSI may be changed by a program. Thus, the selection register 65
By changing the content of the program to the FPGA at any time according to the content of the above, there is obtained an advantage that various peripheral function modules can be realized using an FPGA core of a relatively small scale.

[0017]

According to the present invention, the following effects can be obtained from the above description. As described above, the present invention includes an FPGA unit in an LSI, a storage medium 20 for storing a plurality of types of program data for changing a circuit function of the FPGA unit, and a circuit function corresponding to a set condition as needed. By providing a configuration including a control unit for writing and updating the program data to be executed, a circuit function corresponding to the set condition is realized. As a result, there is obtained an advantage that various peripheral function modules can be realized using an FPGA core of a scale that can be mounted on an LSI. Further, even for an unknown peripheral function module that is newly required in the future, by adding a corresponding write program to the storage medium 20, a great advantage that a circuit change of the LSI itself is not required can be obtained. Therefore, the technical effect of the present invention is great,
Industrial economic effects are also great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram on an LSI chip and an external interface showing an embodiment of the present invention.

FIG. 2 is a configuration diagram on a conventional LSI chip.

FIG. 3 is a configuration diagram on a conventional LSI chip.

FIG. 4 shows an example of an apparatus configuration for converting data and transferring the data to a memory at high speed, and an example of format conversion.

[Explanation of symbols]

 Reference Signs List 10 FPGA core 20 Storage medium 51-59 Peripheral function module 60 CPU core 62 Control memory 65 Selection register 100 Disk 200 Data conversion unit 300 Memory

Claims (3)

[Claims] 1. An FPGA in a semiconductor integrated circuit (LSI)
In a semiconductor integrated circuit having a core, an FPGA core having a rewriteable and rewriteable interface circuit, and receiving a corresponding program data from an external storage medium by designating a circuit program for the FPGA core,
A semiconductor integrated circuit, comprising: write control means for writing an FPGA core. 2. The semiconductor integrated circuit according to claim 1, wherein a circuit function of said FPGA core can be dynamically reset when power is supplied to said LSI circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the write / hold memory cell of the rewritable FPGA core is an EEPROM or a RAM.