JPH103070A - Liquid crystal display panel and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal panel capable of making the opening ratio larger while suppressing crosstalk and the burning of a screen from being generated. SOLUTION: In this liquid crystal display panel having parallel arranged first and second substrates, gate buss lines and data buss lines formed on the counter surface of the first substrate and pixel electrodes 14 formed on the counter surface of the first substrate, outer circumferential parts of respective pixel electrodes 14 are arranged so as to be overlapped with data buss lines of both sides of them. Then, when the static capacitance between one electrode 14 and adjacent two lines of data buss lines 11 of the pixel electrode and the total capacitance of the capacitance between the one pixel electrode and two lines of gate buss lines 12 of the pixel electrode and the capacitance between two lines of the data buss lines 11 and a common electrode 14 are respectively defined as CPS and CPX, 8CPS<CPX is made to be valid.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display panel and a liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix liquid crystal display panel using a thin film transistor (TFT) includes a TFT substrate on which a TFT is formed, a counter substrate facing the TFT substrate, and a liquid crystal material sandwiched between the two substrates. Is done.

A plurality of data bus lines arranged in parallel with each other and intersecting the
Further, a plurality of gate bus lines arranged in parallel with each other are provided. A scanning signal is applied to the gate bus line, and an image signal is applied to the data bus line. Transparent pixel electrodes are arranged in a region surrounded by the gate bus lines and the data bus lines.

Each pixel electrode is connected to one data bus line by a TFT provided for each pixel electrode.
The gate electrode of each TFT is connected to one gate bus line, and the conduction state is controlled by a scanning signal applied to the gate bus line.

[0005] On the opposing surface of the opposing substrate, a transparent common electrode common to all pixels is provided. Further, in order to prevent generation of a photo-excitation current which is excited in the TFT by light incident from the counter substrate side, and to shield light leakage from between the data bus line, the gate bus line and the pixel electrode, the counter substrate is formed. A light shielding film is arranged in a predetermined area on the facing surface.

By accurately aligning the area (opening) of the counter substrate not covered with the light-shielding film with the transparent pixel electrode of the TFT substrate, only light incident on the area where the transparent pixel electrode is formed is transmitted. And light incident on other areas can be blocked. In practice, the counter substrate and T
In order to allow a margin for alignment with the FT substrate, the light shielding film and the transparent pixel electrode are designed to overlap with a width of about several μm to 7 μm.

Since it is necessary to provide a margin for alignment, the aperture ratio of the liquid crystal display panel is reduced. In a projection type liquid crystal display panel having an area of one pixel smaller than that of a direct-view type liquid crystal display panel, a decrease in aperture ratio is a particularly serious problem. Increasing the brightness of the light source can compensate for the decrease in the aperture ratio, but there are problems such as the size of the light source and the rise in temperature of the liquid crystal display panel.

In order to increase the aperture ratio of a liquid crystal display panel, there has been proposed a configuration in which the outer edge of a transparent pixel electrode is arranged so as to overlap a bus line. With this configuration, there is no light leaking from between the transparent electrode and the bus line, and it is not necessary to provide a light-shielding film in this portion. For this reason, it is possible to prevent a decrease in aperture ratio due to the overlap between the light-shielding film and the transparent pixel electrode.

[0009]

When the outer edge portion of the transparent pixel electrode and the data bus line are arranged so as to overlap with each other, the parasitic capacitance between the transparent pixel electrode and the data bus line increases.
Due to this parasitic capacitance, the potential of the transparent pixel electrode fluctuates under the influence of the voltage change of the data bus line. If the change in the potential of the transparent pixel electrode exceeds one gradation, crosstalk occurs.

When the outer edge of the transparent pixel electrode and the gate bus line are arranged so as to overlap with each other, the parasitic capacitance between the transparent pixel electrode and the gate bus line increases. During a scanning period of a pixel, a TFT is connected to a gate bus line corresponding to the pixel.
A forward bias voltage equal to or higher than the threshold voltage is applied. When the scanning of the pixel is completed, the gate bus line displays T
A reverse bias voltage sufficient to make the FT non-conductive is applied.

When the scanning of a certain pixel is completed, the voltage applied to the gate bus line decreases from the forward bias voltage to the reverse bias voltage. Under the influence of this voltage drop, the potential of the pixel electrode also drops. Therefore, when a positive voltage is applied to the pixel electrode, the absolute value of the voltage decreases, and when a negative voltage is applied, the absolute value of the voltage increases.

When performing frame inversion driving, the polarity of the voltage applied to each pixel electrode is inverted for each frame. As described above, since the absolute value of the negative voltage applied to each pixel electrode is larger than the absolute value of the positive voltage, the voltage applied to the pixel electrode includes a negative DC component. This DC component causes screen burn-in.

An object of the present invention is to provide a liquid crystal display panel capable of increasing the aperture ratio while suppressing the occurrence of crosstalk and screen burn-in.

[0014]

According to one aspect of the present invention, there are provided first and second parallelly arranged first and second opposing surfaces.
And a second substrate, a common electrode formed on the facing surface of the second substrate, and a plurality of gate bus lines formed on the facing surface of the first substrate and arranged in parallel with each other. A plurality of data bus lines formed on a facing surface of the first substrate, extending in a direction intersecting with the gate bus lines, and arranged in parallel with each other; And a pixel electrode arranged corresponding to each area surrounded by two adjacent gate bus lines and two data bus lines, and the outer edge of each pixel electrode is formed on both sides thereof. , The capacitance between one pixel electrode and two adjacent data bus lines is C _DS , and the capacitance between one pixel electrode and one adjacent pixel electrode is two. Gate bus line, two days Tabasurain, and when the total capacitance of between the common electrode and the C _PX,

[0015]

And a switching element formed on the opposing surface of the first substrate, wherein the pixel electrode satisfies 8C _DS <C _PX , wherein the switching element is provided corresponding to the pixel electrode. There is provided a liquid crystal display panel having the switching element which is connected to one data bus line and whose conduction state is controlled by one gate bus line.

If eight times the capacitance C _DS is made smaller than the capacitance C _PX , when displaying 16 gradations,
The variation width of the pixel voltage of the non-scanning pixel when the voltage of the data bus line varies from the center to the end of the voltage variation range is 1
The voltage width can be suppressed to be equal to or less than the voltage width corresponding to the gradation.

According to another aspect of the present invention, there are provided a first and a second substrate arranged in parallel with the opposing surfaces facing each other, a common electrode formed on the opposing surface of the second substrate, A plurality of gate bus lines formed on the opposing surface of the first substrate and arranged in parallel with each other; and a plurality of gate bus lines formed on the opposing surface of the first substrate and extending in a direction intersecting the gate bus lines. And a plurality of data bus lines arranged in parallel with each other, and formed on an opposing surface of the first substrate and surrounded by two gate bus lines and two data bus lines adjacent to each other. A pixel electrode disposed corresponding to each of the regions, wherein the pixel electrode is disposed such that an outer edge of each pixel electrode overlaps at least one of the data bus lines on both sides thereof; The switch formed on the opposing surface of the substrate A switching element, which is provided corresponding to the pixel electrode, connects the corresponding pixel electrode to one data bus line, and controls the conduction state by one gate bus line. And a driving circuit for driving the liquid crystal display panel so that the number of gradations is n. One pixel electrode and two data bus lines adjacent thereto. and C _PX capacitance sum between the capacitance and C _DS, 1 single pixel electrode and two gate bus lines adjacent thereto, two data bus lines, and the common electrode between the When

[0018]

## EQU5 ## A liquid crystal display device that satisfies nC _DS <2C _PX is provided.

When n times the capacitance C _DS is smaller than twice the capacitance C _PX , the voltage of the data bus line is changed from the center to the end of the voltage fluctuation range when displaying n gradations. The fluctuation width of the pixel voltage of the non-scanning pixel when the fluctuation is increased can be suppressed to a voltage width corresponding to one gradation or less.

According to another aspect of the present invention, there are provided a first and a second substrate arranged in parallel with each other with the opposing surfaces facing each other; a common electrode formed on the opposing surface of the second substrate; A plurality of gate bus lines formed on the opposing surface of the first substrate and arranged in parallel with each other; and a plurality of gate bus lines formed on the opposing surface of the first substrate and extending in a direction intersecting the gate bus lines. And a plurality of data bus lines arranged in parallel with each other, and formed on an opposing surface of the first substrate and surrounded by two gate bus lines and two data bus lines adjacent to each other. And a switching element formed on the opposing surface of the first substrate, wherein the switching element is provided corresponding to the pixel electrode, and one switching element is provided corresponding to the pixel electrode. And one data bus line A liquid crystal layer sandwiched between the first and second substrates, wherein the switching element has a conduction state controlled by a bus line, and the liquid crystal layer is refracted in response to a change in voltage between the pixel electrode and the common electrode. The index changes, the liquid crystal layer having a high refractive index state and a low refractive index state, and the liquid crystal layer having an intermediate refractive index state, the outer edge of each pixel electrode, a switching element connected to the pixel electrode It is arranged so as to overlap with the gate bus line to be controlled.
The capacitance between one pixel electrode and a gate bus line that controls a switching element connected to the pixel electrode is represented by C
_{GS is} the total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode, and the capacitance in a high refractive index state. the capacity when the C _PX1 low refractive index state C _PX2, the absolute value of the difference between the gate bus line voltage to a non-conducting state and the gate bus line voltage for the switching element to a conducting state and [Delta] V _G When

[0021]

[6] _{| (1 / C PX1) -} (1 / C PX2) | · C GS ·
And a liquid crystal display panel having the pixel electrode satisfying ΔV _G <1.

When the above inequality is satisfied, the DC component of the voltage of the pixel electrode caused by the fluctuation of the voltage of the gate bus line can be reduced to 1 V or less. DC component is 1
In the case of V or less, the DC component can be relatively easily removed by the electric treatment.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIGS. 1 and 2, a description will be given of a conventional technique and a method of solving the problem according to an embodiment of the present invention.

FIG. 1A shows an equivalent circuit and a driving circuit for one pixel of an active matrix type liquid crystal display panel using TFTs. The TFTs 3 are arranged at intersections between a plurality of data bus lines 1 arranged in parallel with each other and a plurality of gate bus lines 2 orthogonal thereto. Each data bus line 1 is supplied with an image signal from the driving circuit 5, and a gate bus line 2 is supplied with a scanning signal from the driving circuit 5. The drain terminal 3D of the TFT 3 is connected to one data bus line 1, and the gate terminal 3G is
Connected to one gate bus line 2 and a source terminal 3S
Are connected to the pixel electrode 4.

The parasitic capacitance between the pixel electrode 4 and the data bus lines 1 on both sides thereof is represented by C _DS , and the parasitic capacitance between the pixel electrode 4 and the T bus connected to the pixel electrode 4.
The gate bus line 2 for controlling the FT 3 and the pixel electrode 4
C _GS , and the auxiliary capacitance between the other gate bus line 2 and the pixel electrode 4 is C _S. Further, each pixel electrode 4, the capacitance between the common electrode thereto facing each other across the liquid crystal layer and C _LC. As described later, the auxiliary capacitance C _S is designed to be as large as possible.

FIG. 1B shows the voltage dependence of the light transmittance of the liquid crystal display panel. The horizontal axis represents the voltage (pixel voltage) between the pixel electrode and the common electrode, and the vertical axis represents the light transmittance. When the pixel voltage is V _off becomes a high transmittance (white display), the voltage becomes low transmittance (black display) when V _on. Voltage V _on and V
By dividing the voltage range of the difference ΔV from _off into n equal parts and applying a voltage corresponding to each division point, it is possible to display n gray scales. In the average voltage V _mid with the voltage V _{of f} and V _on, the light transmittance becomes the value of the average of the white display and the black display state, gray is displayed.

FIG. 1C shows an example of a temporal change of the voltage of the data bus line 1, the gate bus line 2, and the pixel electrode 4. The solid line V _D and V _G in the figure, one data bus line 1 and the gate voltage applied to the bus line 2 corresponding to the pixel of interest, respectively, a broken line V _S represents the voltage of the pixel electrode 4 .

Time t₁At the gate bus line 2
A pulse voltage is applied and the pixel of interest is scanned.
It is. Voltage V_GDuring the period when is at the high level, the TFT
Becomes conductive. To display in gray, the time t₁
Voltage V at_DTo V_midKeep it equal to Time t₁
Since the TFT 3 is turned on, the pixel voltage V_SAlso V
_midIs equal to

[0029] When the voltage V _G falls, since the TFT3 is nonconducting, the pixel voltage V _S, ideally, the time t ₂ of one frame period T is the scanning of the next frame is started after the lapse Maintain a constant voltage until. But actually,
Parasitic capacitance C _DS pixel voltage V _S due to the influence of changes as described below.

When the scanning of the pixel of interest is completed, the voltage V _D changes according to the display state of the pixel to be scanned next. For example, a pixel to be scanned next when the black display causes a voltage V _D as shown in FIG. 1 (C) is lowered from V _mid to V _off. When the voltage V _D falls, it drops the pixel voltage V _S due to the influence of the parasitic capacitance C _DS. Thus, the pixel voltage V _S is varied in accordance with the voltage change of the data bus lines 1 disposed adjacent to the pixel electrode, crosstalk occurs.

[0031] When the frame inversion drive, just before the scanning start time t ₂ of the next frame, to equalize the voltage V _D to -V _mid. At this time, also decreases the pixel voltage V _S corresponding to the change of the voltage V _D. Since the period after the voltage drop is very small compared to the one frame period T, the display quality is not significantly affected.

In order to suppress the occurrence of crosstalk,
Variation width ΔV of pixel voltage at the end of scanning_SReduce
Preferably. Also, as shown in FIG.
Elementary voltage V_SIs V_midChange rate of transmittance when changing near
Is the largest. Therefore, the pixel voltage V_SIs V_midTo
Crosstalk is likely to occur in substantially equal pixels.
Pixel voltage V_SIs almost V_midCross at pixel equal to
In order to suppress the occurrence of talk, the scanning of the pixel is terminated.
After completion, the voltage V of the data bus line 1 is_DIs V _midFrom
V_offOr V_onUp to ΔV / 2
Pixel voltage V_SFluctuation width ΔV_SThan the voltage width for one gradation
It is preferable to make it smaller. That is, the pixel voltage V_Sof
Fluctuation width ΔV_STo

[0033]

It is preferable that ΔV _S <ΔV / n (1). Here, n is the number of gradations.

[0034] The fluctuation width ΔV _S of the pixel voltage V _S,

[0035]

ΔV _S = (C _DS / C _PX ) (ΔV / 2) (2) Here, C _PX is the total capacitance C _DS + C _GS + C _LC + C _S for the pixel electrode 4.

From equations (1) and (2),

[0037]

The following equation is derived: nC _DS <2C _PX (3)

For example, 8C_DS<C_PXTo satisfy
As a result, the liquid crystal display panel of 16 gradation display
Locktalk can be effectively suppressed. Also, 3
2C _DS<C_PX64 gradations by satisfying
Effective crosstalk in display LCD panel
Can be suppressed. Also, 128C_DS<C_PXSatisfy
In this way, the liquid crystal display
Can effectively suppress the crosstalk in the
Wear.

In FIG. 1C, the influence of the parasitic capacitance between the pixel electrode and the data bus line on the display quality has been described. Next, the effect of the parasitic capacitance between the pixel electrode and the gate bus line on the display quality will be described.

FIG. 2A shows an example of a temporal change of the voltage applied to the data bus line 1, the gate bus line 2, and the pixel electrode 4 shown in FIG. Solid line V _G in the figure
Represents the voltage of the gate bus line 1, solid lines V _D (on) and V _D (off) represent the voltage of the data bus line 1 corresponding to the pixels in the black display state and the white display state, respectively,
_S (on) and V _S (off) represent the pixel voltages of the pixels in the black display state and the white display state, respectively.

The time u ₁ of the scanning is finished and falls voltage V _G, Figure 1 (A) to indicate the parasitic capacitance C pixel voltage influenced by the _GS V _S (on) and V _S (off) descend. The pixel voltages V _S (on) and V _S (off) similarly decrease at the time when the scanning at the time u ₂ is completed after the lapse of one frame period T. In the case of FIG. 1 (C), regardless of the polarity of the pixel voltage V _S, the pixel voltage V _S at the end of scan is changed in the direction to reduce its absolute value. On the other hand, in the case of FIG. 2A, when the pixel voltage V _S is positive, the absolute value decreases, and when the pixel voltage V _S is negative, the absolute value increases.

[0042] The change width ΔV _S of the pixel voltage V _S,

[0043]

ΔV _S = (C _GS / C _PX ) ΔV _G (4) Here, [Delta] V _G is the voltage corresponding to the pulse height of the pulse voltage applied to the gate bus line 2. That, [Delta] V _G corresponds to the difference between the gate voltage to the gate voltage and the non-conductive state to the conductive state TFT 13.

The pixel is the case of the black display state _{(V S = V S (on} )), as in the white display state _{(V S = V S (off} )), the dielectric constant of the liquid crystal layer is different, the liquid crystal The capacitance _CLC across the layers is also different. Therefore, the total capacitance C _PX (o
n) and the total capacitance C _PX (off) of the pixel electrode in the white display state are different from each other. From equation (4),

[0045]

ΔV _S (on) = (C _GS / C _PX (on)) ΔV _G ΔV _S (off) = (C _GS / C _PX (off)) ΔV _G (5) is derived. Here, ΔV _S (on) and ΔV _S (of
f) is the fluctuation width of the pixel voltage V _S of the pixel in the black display state and the pixel in the white display state, respectively.

As shown in the equation (5), the variation width of the pixel voltage V _S differs between the pixel in the black display state and the pixel in the white display state. Therefore, the pixel voltage V of the pixel in the black display state
The _S amplitude central value V _C of the center value of the amplitude of (on) V _C (on) and the pixel voltage of the pixel in a white display state _{V S (off) (off)} , different from each other.

The potential of the common electrode is set at the center values V _C (on) and V _C (o
ff), when the center value of the amplitude of the pixel voltage is different from the potential of the common electrode,
DC component in the pixel voltage V _S remains. This DC component causes screen burn-in.

FIG. 2B shows a case where a DC component eliminating circuit for removing a DC component is added to the driving circuit 5 of FIG. 1A in both the black display state and the white display state pixels. 4 shows an example of a voltage change. For differs from FIG. 2 (A), the voltage V _D applied to the data bus line 1 is that the DC bias voltage corresponding to each of the black display and white display is given.

That is, the voltage V _D (on) is equal to ΔV _S (on)
DC bias voltage and voltage V _D (off) correspond to Δ
A DC bias voltage corresponding to V _S (off) is given in advance. Therefore, the center value of the amplitude of the pixel voltage V _S (on) and the center value of the amplitude of V _S (off) can be matched. This DC bias voltage is provided by a DC component eliminating circuit in the drive circuit 5.

As described above, the DC component of the voltage applied to the liquid crystal layer can be removed by applying a DC bias voltage according to the display state to the voltage applied to the data bus line 1 in advance. However, in order to provide a DC bias voltage according to the display state of the pixel by the DC component eliminating circuit and obtain a sufficient DC component removing effect, the variation ΔV _S (on) and ΔV _S (off) of the pixel voltage V _S are required. Is preferably smaller than 1V.

That is, from equation (5),

[0052]

It is preferable that ((1 / C _PX (off)) − (1 / C _PX (on))) · C _GS · ΔV _G <1 (6)

From equations (3) and (6), the parasitic capacitances C _DS and C _GS between the pixel electrode and each bus line are reduced,
It can be seen that it is preferable to increase the total capacity _CPX .
One method for increasing the total capacity C _PX is shown in FIG.
A method of increasing the capacitance C _S shown in FIG.

FIG. 2C shows the capacitance C_SDepends on
Pixel voltage V_SShows the variation of Solid line V _DIs the data bus line
Voltage applied to the_SIs the pixel G₁Pixel voltage V
_SIs shown. Pulse G₁~ G_ThreeIs the data bus
Pixels G continuously arranged along the₁~ G_ThreeEach scanning signal
This is a pulse corresponding to the signal. 2 (A) and 2 (B)
As mentioned, the pulse G₁Falls, Figure 1 (A)
The parasitic capacitance C shown in_GSPixel voltage V_SDecreases
I do.

When the pulse G ₂ rises and falls, the pixel voltage V is affected by the capacitance C _S , respectively.
_S rises and falls. Electrostatic capacity C _S, since occurring in both rising and falling of the pulse G _2, the pixel voltage V _S before and after affected by the pulse G ₂ is hardly fluctuates. Therefore, even if the capacitance C _S is positively increased, the influence on the pixel voltage V _S is small. Increasing the capacitance C _S is more effective than the degradation of display quality due to the fluctuation of the pixel voltage V _S than the total capacitance C _{PX of} Expressions (3) and (6).
Has a large effect of improving display quality.

Next, a configuration of the liquid crystal display panel according to the embodiment of the present invention for satisfying the expressions (3) and (6) will be described with reference to FIG.

FIG. 3A is a plan view schematically showing a liquid crystal display panel according to the embodiment. As shown in FIG. 3A, a plurality of data bus lines 11 arranged in parallel with each other.
Extend in the vertical direction of the figure, and a plurality of gate bus lines 12 arranged in parallel to each other extend in the horizontal direction of the figure. A TFT 13 is provided at an intersection of the data bus line 11 and the gate bus line 12. The drain region 13D of the TFT 13 is connected to the corresponding data bus line 11, and the gate electrode 13G is continuous with the corresponding gate bus line 12.

Two data bus lines 1 adjacent to each other
A pixel electrode 14 is arranged corresponding to a region surrounded by one and two gate bus lines 12. Pixel electrode 1
4 is connected to the source region 13S of the corresponding TFT13. Portions of the outer edge of the pixel electrode 14 other than the portion facing the TFT 13 overlap the bus lines 12 and 13. In correspondence with the area where the TFT 13 is arranged,
A light-shielding film 16 is provided. The entire rectangular area surrounded by the two gate bus lines 12 and the two data bus lines 11 adjacent to each other is the light shielding film 16 and the pixel electrode 1.
4 to be completely covered.

FIG. 3B is a dashed line B3 of FIG.
The sectional view in -B3 is shown. Glass substrates 20 and 30
Are arranged parallel to each other. On the facing surface of the glass substrate 20, a gate electrode 13G made of chromium (Cr) is formed. The gate electrode 13G is formed, for example, by sputtering over the entire region on the opposing surface of the glass
After depositing the film, the Cr film is formed by patterning. By patterning the Cr film, a gate bus line 12 continuous to the gate electrode 13G shown in FIG. 3A is also formed at the same time.

On the opposing surface of the glass substrate 20, a thickness of about 330 nm made of SiN is formed so as to cover the gate electrode 13G.
Of the gate insulating film 21 is formed. Gate insulating film 2
1 is formed by, for example, chemical vapor deposition (CVD). An amorphous silicon film 13C having a thickness of about 150 nm is formed in a region on the surface of the gate insulating film 21 where a TFT is to be formed.

The source electrode 1 having a three-layered structure of Ti / Al / Ti is formed in a region corresponding to the source and the drain in the region on the surface of the amorphous silicon film 13C.
3S and the drain electrode 13D are formed. Lower T
The thickness of the i layer is about 20 nm, the thickness of the Al layer is about 50 nm,
The thickness of the upper Ti layer is about 80 nm. Drain electrode 1
3D is formed simultaneously with the data bus line 11 that is continuous with the drain electrode 13D shown in FIG.

The deposition of the amorphous silicon film 13C is performed as follows.
For example, it is performed by CVD using SiH ₄ as a source gas, and patterning is performed using a resist pattern as a mask,
This is performed by etching using a plasma asher. T
The i-layer and the Al layer are deposited by sputtering, and the patterning is performed by etching using a resist pattern as a mask and wet processing.

On the surface of the gate insulating film 21, the TFT 13
An interlayer insulating film 22 having a thickness of about 2 μm is formed so as to cover. The interlayer insulating film 22 is formed by, for example, spin-coating an acrylic resin LC-201 manufactured by Sanyo Chemical Industries. The relative permittivity of the acrylic resin LC-201 is about 3
It is. The surface of the interlayer insulating film 22 becomes substantially flat.

On the surface of the interlayer insulating film 22, a plurality of transparent pixel electrodes 1 made of indium tin oxide (ITO)
4 are formed. Each transparent pixel electrode 14 is connected to the TFT 1 through a contact hole formed in the interlayer insulating film 22.
3 is connected to the third source electrode 13S. An alignment film 23 is formed on the entire surface so as to cover the transparent pixel electrode 14.

On the opposing surface of the glass substrate 30, a TFT 1
3 corresponding to the region where Cr.
A 20 nm light-shielding film 16 is formed. Light shielding film 16
Is formed by depositing a Cr film on the entire surface by, for example, sputtering and then patterning by etching using wet processing.

A transparent common electrode 31 made of ITO is formed on the entire surface so as to cover the light shielding film 16, and an alignment film 32 is formed on the surface thereof. Between the alignment films 23 and 32,
A liquid crystal material 40 is sandwiched.

The width of the data bus line 11 shown in FIG. 3A is 6 μm, the width of the gate bus line 12 is 15 μm, the pitch of both bus lines is 100 μm, the pixel electrode 14 and the data bus lines 11 on both sides thereof are The overlap width with the gate bus line 12 is 2 μm, and the area of the rectangular area surrounded by the data bus line 11 and the gate bus line 12 which is shielded by the light shielding film 16 is about 14 μm.
It was set to 00 μm ² .

It should be noted that the pixel electrode 14 and the gate bus line 12 corresponding to the adjacent pixel have a large overlapping width in order to increase the capacitance. Furthermore, by disposing an auxiliary electrode connected to the pixel electrode 14 at the interface between the gate insulating film 21 and the interlayer insulating film 22 shown in FIG.
The substantial distance between the pixel electrode 14 and the gate bus line is shortened.

At this time, the parasitic capacitance C _GS shown in FIG.
Is 27.8 fF, the parasitic capacitance C _DS is 6.2 fF, the capacitance C _S is 245 fF, and the capacitance C _LC (o when the voltage V _{off is} applied.
ff) is 150.8 fF, the capacitance C when the voltage V _{on is} applied
_LC (on) was 307.8 fF. When these numerical values are applied to Expression (3), the inequality expression is satisfied when the number of gradations n is 138 or less. That is, it is possible to perform display of a maximum of 138 gradations while suppressing occurrence of crosstalk.

When these numerical values are applied to equation (6), an inequality holds when ΔV _G is 57.8 V or less. That is, the difference [Delta] V _G voltage of the gate bus line when the voltage and the non-scanning of the gate bus lines during scanning 57.8
Driving to be equal to or less than V satisfies Expression (6). Since the difference between the ON level and the OFF level of the gate voltage of a normal TFT is 57.8 V or less, the liquid crystal display panel shown in FIG. 3 satisfies Expression (6).

As shown in FIG. 3B, an interlayer insulating film 22 having a relative dielectric constant of 3 and a thickness of about 2 μm is formed between the pixel electrode 14 and the data bus line 11 and the gate bus line 12. , The parasitic capacitance between the pixel electrode 14 and the bus lines 11 and 12 disposed adjacent to the pixel electrode 14 can be reduced. By reducing the parasitic capacitance, FIG.
Also, as described with reference to FIG. 2, Expressions (3) and (6) are satisfied, and the occurrence of crosstalk and screen burn-in can be suppressed.

In order to obtain a sufficient effect of reducing the parasitic capacitance, the relative dielectric constant of the interlayer insulating film disposed between the pixel electrode 14 and the bus lines 11 and 12 is set to 3.5 or less, and the film thickness is reduced. Preferably, the thickness is 1.5 μm or more. In the above embodiment, the case where the acrylic resin is used as the interlayer insulating film 22 has been described, but other materials may be used as long as the relative dielectric constant and the film thickness are within these ranges. For example, a photosensitive resin used in a semiconductor process may be used. When a photosensitive resin is used, patterning can be easily performed by exposure and development.

Next, another effect of the liquid crystal display panel shown in FIG. 3 will be described with reference to FIG. FIG. 4A is a schematic cross-sectional view showing a relative positional relationship between the pixel electrode 14 and the gate bus line 12. Each component is given the same reference numeral as the corresponding component in FIG. Note that, for simplification, illustration of a gate insulating film and the like is omitted.

When a potential difference occurs between the pixel electrode 14 and the gate bus line 12, an electric field E is generated between the vicinity of the end of the pixel electrode 14 and the gate bus line 12. This electric field E hardly penetrates the liquid crystal layer.

FIG. 4B shows a case of a conventional liquid crystal display panel. A thinner interlayer insulating film 22a is formed instead of the interlayer insulating film 22 of FIG. Pixel electrode 1
4 is arranged so that its outer edge does not overlap with the gate bus line 12. In this case, an electric field E is generated in the lateral direction between the end of the pixel electrode 14 and the gate bus line 12.

A part of the horizontal electric field E penetrates the liquid crystal layer. Under the influence of the transverse electric field E penetrating the liquid crystal layer, the arrangement of the liquid crystal molecules is disturbed, and the disorder of the arrangement causes deterioration of display quality. On the other hand, in the case of FIG. 4A, since a horizontal electric field is not generated in the liquid crystal layer, it is possible to prevent display quality from deteriorating due to the horizontal electric field.

In the case of FIG. 4B, irregularities are formed on the substrate facing surface in the vicinity of the gate bus line 12. These irregularities cause disturbance of the alignment of the liquid crystal molecules.
On the other hand, in the case of FIG. 4A, since the surface of the interlayer insulating film 22 becomes substantially flat, it is possible to prevent the disorder of the alignment of the liquid crystal molecules due to the unevenness of the surface facing the substrate.

Although FIG. 3 illustrates the case where the light-shielding film is provided on the counter substrate side, it may be provided on the TFT substrate side.

FIG. 5 is a sectional view of a liquid crystal display panel in which a light shielding film is provided on the TFT substrate side. A black resin 41 is formed so as to cover the TFT 13. The black resin 41 is shown in FIG.
The light-shielding film 16 shown in FIG. No light-shielding film is formed on the counter substrate side. Other configurations are the same as those in FIG.

When a black resin is formed on the TFT substrate side, T
When bonding the FT substrate and the counter substrate, there is no need to perform high-accuracy alignment. Therefore, the overlap between the light-shielding film 16 and the pixel electrode 14 shown in FIG. 3A can be reduced, and the aperture ratio can be further increased.

FIGS. 3 and 4 show a case where the outer edge of the pixel electrode 14 overlaps both the data bus line 11 and the gate bus line 12 around it, but it may be configured to overlap only one of the bus lines. . Also, the pixel electrode 14
Of the data bus lines 11 on both sides may overlap with only one of the data bus lines. In this case, a light-shielding film is disposed in a region corresponding to a gap between the pixel electrode 14 and a gate bus line and a data bus line which do not overlap with the pixel electrode 14.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0083]

As described above, according to the present invention,
When the pixel electrode and the bus line are arranged so as to overlap each other to increase the aperture ratio, it is possible to suppress an increase in parasitic capacitance between the pixel electrode and the bus line, and to reduce the occurrence of crosstalk and screen burn-in. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an equivalent circuit of one pixel of a liquid crystal display panel, a graph showing voltage dependence of light transmittance, a data bus line, a gate bus line, and a pixel electrode for describing a solution to a problem according to an embodiment of the present invention. 5 is a graph showing an example of a change over time of the voltage of FIG.

FIG. 2 is a graph illustrating an example of a time change of a voltage of a data bus line, a gate bus line, and a pixel electrode of a liquid crystal display panel, for describing a method of solving a problem according to an embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view schematically showing a liquid crystal display panel according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view schematically showing a TFT substrate for describing an effect of the liquid crystal display panel shown in FIG.

FIG. 5 is a plan view and a sectional view schematically showing a liquid crystal display panel according to a modification of the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Data bus line 2, 12 Gate bus line 3, 13 TFT 4, 14 Pixel electrode 5 Drive circuit 16 Light shielding film 20, 30 Glass substrate 21 Gate insulating film 22 Interlayer insulating film 23, 32 Alignment film 31 Common electrode 40 Liquid crystal Material 41 Black resin

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuya Kobayashi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Ikuo Tomita 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 in Fujitsu Limited

Claims (7)

[Claims] A first substrate and a second substrate arranged in parallel with the opposing surfaces facing each other; a common electrode formed on the opposing surface of the second substrate; A plurality of gate bus lines formed on a surface and arranged in parallel with each other; and a plurality of gate bus lines formed on a facing surface of the first substrate and extending in a direction intersecting with the gate bus lines and parallel to each other. A plurality of data bus lines arranged, and a plurality of data bus lines formed on the opposing surface of the first substrate and corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other. The pixel electrodes are arranged such that the outer edge of each pixel electrode overlaps at least one of the data bus lines on both sides thereof, and
The capacitance between one pixel electrode and two adjacent data bus lines is C _DS , one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode. a sum when the capacitance was C _PX, Equation 1] 8C _DS <and the pixel electrode C _PX is true, the switching element formed on a facing surface of the first substrate between the A liquid crystal display panel having a switching element provided corresponding to the pixel electrode, connecting the corresponding pixel electrode to one data bus line, and controlling the conduction state by one gate bus line. 2. A light-shielding film formed on at least one of the first and second substrates on a facing surface of the first and second substrates and arranged in a region where the switching element is arranged. 2. The liquid crystal display panel according to claim 1, wherein a film is not disposed in an overlapping region between the pixel electrode and the data bus line and in the vicinity thereof. 3. A first and a second substrate arranged in parallel with each other with facing surfaces facing each other; a common electrode formed on the facing surface of the second substrate; and a facing of the first substrate. A plurality of gate bus lines formed on a surface and arranged in parallel with each other; and a plurality of gate bus lines formed on a facing surface of the first substrate and extending in a direction intersecting with the gate bus lines and parallel to each other. A plurality of data bus lines arranged, and a plurality of data bus lines formed on the opposing surface of the first substrate and corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other. A pixel electrode disposed, wherein the outer edge of each pixel electrode is disposed so as to overlap at least one of the data bus lines on both sides thereof, and the pixel electrode is formed on a facing surface of the first substrate. Switching element, A liquid crystal configured to include the switching element provided corresponding to the pixel electrode, connecting the corresponding pixel electrode to one data bus line, and controlling the conduction state by one gate bus line; A display panel; and a driving circuit for driving the liquid crystal display panel so that the number of gradations is n. The electrostatic capacitance between one pixel electrode and two data bus lines adjacent thereto is provided. When the capacitance is C _DS , the total capacitance between one pixel electrode and two gate bus lines adjacent thereto, two data bus lines, and the common electrode is C _PX , A liquid crystal display device which satisfies nC _DS <2C _PX . 4. A mutually parallel arrangement with the opposing surfaces facing each other.
First and second substrates, a common electrode formed on a facing surface of the second substrate, and a common electrode formed on a facing surface of the first substrate and arranged in parallel with each other.
A plurality of gate bus lines disposed on the first substrate, and a plurality of gate bus lines formed on a facing surface of the first substrate;
Extend in a direction that intersects the lines and are arranged parallel to each other
And a plurality of data bus lines formed on the opposing surface of the first substrate and adjacent to each other
Two gate bus lines and two data bus lines
A pixel electrode arranged corresponding to each of the regions surrounded by
And provided corresponding to the pixel electrode,
Pixel electrode and one data bus line
The gate whose conduction state is controlled by the gate bus line
A switching element; and a liquid crystal layer sandwiched between the first and second substrates.
The change in the voltage between the pixel electrode and the common electrode.
The refractive index changes accordingly, the high refractive index state and the low refractive index state,
And the liquid crystal layer having an intermediate refractive index state.
The outer edge of each pixel electrode is connected to a switch connected to the pixel electrode.
So that it overlaps the gate bus line that controls the switching element
And is connected to one pixel electrode and the pixel electrode.
Between the gate bus line that controls the switching element
The capacitance of C _GS, One pixel electrode and adjacent to it
Two gate bus lines, two data bus lines and
The total capacitance between the common electrode and the
The capacity in the rate state is C_PX1Capacitance in low refractive index state
To C_PX2To make the switching element conductive.
Gate to make the gate bus line voltage non-conductive
The absolute value of the difference from the bus voltage is ΔV_GWhere: | (1 / C)_PX1)-(1 / C_PX2) ｜ ・ C_GS・
ΔV_G<1. A liquid crystal display panel comprising: 5. A light-shielding film formed in a region where the switching element is arranged on at least one of the first and second substrates on a surface facing the one substrate, wherein the light-shielding film is provided. 5. The liquid crystal display panel according to claim 4, wherein no is formed in an overlapping area between the pixel electrode and the gate bus line and in the vicinity thereof. 6. A first and a second substrate arranged in parallel with each other with their opposing surfaces facing each other; a common electrode formed on the opposing surface of the second substrate; A plurality of gate bus lines formed on a surface and arranged in parallel with each other; and a plurality of gate bus lines formed on a facing surface of the first substrate and extending in a direction intersecting with the gate bus lines and parallel to each other. A plurality of data bus lines arranged; and a film formed on the opposing surface of the first substrate, covering the gate bus lines, the data bus lines and the switching elements, and having a film thickness on the gate bus lines and the data bus lines. And an insulating film having a relative dielectric constant of not more than 1.5 μm and a relative dielectric constant of not more than 3.5, and two gate bus lines and two data bus lines which are formed on the surface of the insulating film and are adjacent to each other. Each area A pixel electrode disposed response,
A pixel electrode disposed so that an outer edge of each pixel electrode overlaps at least one of the gate bus line and the data bus line; and a switching element formed on a facing surface of the first substrate. A liquid crystal display panel having a switching element provided corresponding to the pixel electrode, connecting the corresponding pixel electrode to one data bus line, and controlling the conduction state by one gate bus line. 7. The liquid crystal display panel according to claim 6, wherein the insulating film is formed of an acrylic resin or a photosensitive resin.