JPH10302487A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a reliable control of the cell threshold and improvement in performance and reliability by first performing write verifying when the automatic write is started, and for the memory cell resultantly required, repeating write and write verifying until write is completed. SOLUTION: A memory cell array 10 which constitutes a flash EEPROM divides plural non-volatile memory cells having a floating gate and a control gate to plural blocks BK. The control circuit 22 controls each part and the address counter 23 designates the intended block BK and the address of the memory cell at the times of automatic write and automatic erase. By the write command of the command circuit 25, the PLA circuit 28 executes write verifying first when automatic write is started. As the results, write and write verifying are repeated until write is completed for the memory cell which needs write. Therefor, performance and reliability are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically erasable and rewritable nonvolatile semiconductor memory device (EEPROM).
In particular, the present invention relates to an EEPROM having at least one of an automatic writing function and an automatic erasing function, and is used, for example, in a batch erasing type semiconductor memory such as a NOR flash EEPROM.

[0002]

2. Description of the Related Art An EEPROM has an advantage that data in a non-volatile cell is not erased even when the power is turned off, and its demand has been greatly increased in recent years. In particular, a flash memory in which a memory cell is constituted by one transistor and which can be erased at a time is expected to be used as a substitute for a large-capacity magnetic disk.

A memory cell used in a conventional EEPROM cell array has an NMOS type having a two-layer gate structure in which a floating gate electrode formed as a charge storage layer in a gate insulating film and a control gate electrode are stacked. It consists of a field effect transistor (cell transistor).

Such a cell transistor causes deterioration of writing characteristics or erasing characteristics due to repetition of writing / erasing at the time of use, and takes longer time for writing / erasing or floating than at the beginning of use. The amount of charge injection / emission to the gate decreases, and the range of change between the threshold in the written state and the threshold in the erased state of the memory cell decreases.

Further, when writing and erasing are repeated during use, an electric field concentrates on the carriers trapped in the insulating film, causing dielectric breakdown of the memory cell. In addition, writing / erasing to other cells sharing the drain region becomes impossible, or erroneous data is read from the memory cell.

For example, when a high write voltage is applied to the control gate common to the destroyed cell, a leak current flows from the control gate through the insulating film of the destroyed cell to the semiconductor substrate, and the write voltage becomes lower than a desired potential. Problems occur, such as writing becomes impossible due to the drop, and current consumption increases.

In an EEPROM, a writing voltage and an erasing voltage are each formed by a high voltage generating circuit which obtains a high voltage by boosting a power supply voltage Vcc. This high-voltage generating circuit includes a booster circuit composed of a multistage cascade-connected charge pump circuit, and a voltage limiting circuit connected to the last-stage charge pump circuit in the booster circuit.

In the above-described EEPROM, when writing data, the larger the number of times of application of a write pulse having a constant voltage and a constant time width, the more the amount of charge written to the floating gate electrode can be increased. In this case, the intelligent write method adopted to prevent overwriting controls the number of times of application of a write pulse and performs data writing in a plurality of small steps. Then, the data writing and the reading operation after the writing are repeated, and the writing operation is terminated when the read data becomes equal to the writing data.

On the other hand, EEPRO has recently increased in capacity.
In semiconductor memories such as M, it is becoming an essential technology to provide a redundant circuit in order to improve the production yield. This redundant technique is different from a normal memory cell array (regular memory cell array) in that a spare memory cell array for repairing, for example, a defective row of the regular memory cell array, and a spare memory cell for selecting a row of the spare memory cell array. An address decoder (programmable decoder) is provided on the same semiconductor chip to rescue a defective cell in a normal memory cell array found in an inspection process in a manufacturing stage.

In recent flash EEPROMs, there has been an increasing demand for products adopting a single power supply system that does not use an external power supply dedicated to writing and erasing. In such a flash EEPROM, a read power supply voltage Vcc is used when data is rewritten by a booster circuit built in the memory.
It is necessary to generate the above high voltage, and if it is attempted to provide the booster circuit with a current supply capability necessary for erasing all the memory cells at the same time, the power consumption of the booster circuit becomes extremely large. This is disadvantageous for products that require power consumption.

Therefore, in order to suppress the power consumption of the booster circuit, the cell array area to be erased may be set in units of blocks, and a plurality of blocks to be erased may be automatically erased serially for each block.

[0012]

However, a conventional flash EEPROM having an automatic writing function and an automatic erasing function has been proposed.
M was not always satisfactory in terms of certainty, performance, and reliability of cell threshold control.

An object of the present invention is to provide a semiconductor memory device capable of reliably controlling a cell threshold at the time of automatic writing and erasing in a flash EEPROM and improving performance and reliability.

[0014]

According to a first semiconductor memory device of the present invention, there is provided a memory cell array in which a plurality of nonvolatile memory cells having a double-layer gate structure in which a floating gate and a control gate are stacked are arranged. An automatic write control circuit for automatically controlling a write process by designating one or a plurality of memory cells to be written in the memory cell array based on a write command input; and At the start of automatic writing, write verification is first performed, and as a result of the write verification, writing and write verification are repeated until writing is completed for a memory cell that requires writing. Here, the automatic write control circuit controls the amount of charge injected into the floating gate according to the number of repetitions of the write and write verify. The control of the amount of injected charge is performed by controlling the time width of a write pulse.

A second semiconductor memory device of the present invention is based on a memory cell array in which a plurality of nonvolatile memory cells having a two-layer gate structure in which a floating gate and a control gate are stacked are arranged, and based on an erase command input. An automatic erase control circuit for automatically controlling an erase process by designating a plurality of memory cells to be erased in the memory cell array. And erasing and erasing verification are repeated until erasure is completed for the memory cells that need to be erased as a result of the erasure verification. Preferred embodiments of the second semiconductor memory device are as follows: (1) The automatic erase control circuit further performs detection of an over-erased bit line after erasing and control of a threshold of an over-erased memory cell.

(2) At the time of erasing and erasing verification, an erasing voltage for a fixed pulse time is applied, and erasing verification is performed every time erasing to determine whether the threshold value of a memory cell is equal to or less than a predetermined value. Erase and erase verify are repeated until it is confirmed that the threshold value is equal to or less than a predetermined value.

A third semiconductor memory device according to the present invention is based on a memory cell array in which a plurality of nonvolatile memory cells having a two-layer gate structure in which a floating gate and a control gate are stacked are arranged, and based on an erase command input. An automatic write / erase control circuit for automatically controlling a process by designating a plurality of memory cells to be erased in the memory cell array, wherein the automatic write / erase control circuit Write verification is performed, and as a result of the write verification, if writing before erasure is necessary, writing and write verification are repeated until the writing is completed. When the pre-erase writing is completed, erasure verification is performed, and then erasure is completed. Until then, the erase and erase verify operations are repeated. Preferred embodiments of the third semiconductor memory device are as follows.

(1) The memory cell array includes a plurality of memory cell blocks divided in a row direction.
Here, the automatic write / erase control circuit serially designates a plurality of memory cell blocks, and automatically controls processing for a plurality of memory cells in the designated memory cell block.

(2) The automatic write / erase control circuit further performs detection of an over-erased bit line after erasing and control of a threshold value of the over-erased memory cell. (3) At the time of the pre-erase write, the write address is automatically counted up in order to write to all the memory cells in the designated block.

(4) In the pre-erase write, the pre-erase write is also performed on the redundancy cell before the defective replacement and the main body cell after the defective replacement. (5) At the time of erasing and erasing verification, an erasing voltage for a fixed pulse time is applied, and erasure verification is performed every time erasing to determine whether or not the threshold value of a memory cell is equal to or less than a predetermined value. Erase and erase verify are repeated until it is confirmed that the value is equal to or less than the value.

(6) The automatic write / erase control circuit further checks whether the threshold values of all the memory cells are equal to or less than a predetermined value by the erase verify, and then executes the leak as the over-erase bit line detection processing. Do a check.

(7) In the leak check, all word lines are set to 0 V, a bit line for one address is selected, and whether or not the selected bit line has a bit line leak due to an over-erased memory cell. Is determined by determining

(8) When the result of the leak check is OK, the erase sequence is terminated, and when the result of the leak check is NG, self-convergence processing which is threshold control of the over-erased memory cell is executed. Here, the case of NG means a case where it is determined that the bit line has an overerased memory cell. In the self-convergence processing, the self-convergence voltage is applied to the selected bit line for a certain period of time while all word lines are kept at 0 V to raise the threshold value of the over-erased memory cell to a value at which bit line leakage does not substantially occur. .

(9) After the self-convergence process, the automatic write / erase control circuit performs the leak check again to determine whether the self-convergence has been correctly performed. (10) After executing the self-convergence processing, the automatic write / erase control circuit re-executes erase verify to check whether or not the threshold values of all memory cells are equal to or less than a predetermined value.

(11) The automatic write / erase control circuit terminates the erase sequence if it is confirmed at the time of the erase verify after the self-convergence processing that the threshold values of all the memory cells are equal to or less than a predetermined value. If the thresholds of some of the memory cells cannot be confirmed to be equal to or less than the predetermined value, the erase is performed again, and the self-convergence process and the erase are repeated until both the leak check and the erase verify are determined to be OK. .

As described above, according to the semiconductor memory device of the present invention, the control of the cell threshold can be reliably performed at the time of automatic writing and erasing in the flash EEPROM, and the performance and reliability can be improved.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. Here, it is assumed that the flash EEPROM according to the present embodiment has the following basic configuration. (1) A single power supply system having a built-in booster circuit that boosts a voltage supplied from an external power supply and generates a write / erase voltage. (2) an automatic write function for automatically writing a plurality of memory cells in a cell array area to be written;
An automatic erasing function for automatically erasing a plurality of blocks in a cell array area to be erased in units of blocks in a serial manner. (3) To have a defective cell rescue control function of replacing a defective row in a cell array with a spare row and relieving the spare row, for example.

FIG. 1 shows a NOR according to an embodiment of the present invention.
FIG. 1 is a block circuit diagram schematically showing an overall configuration of a flash EEPROM. In FIG. 1, in a memory cell array 10, memory cells (cell transistors) each composed of an N-channel MOSFET having a floating gate and a control gate constitute, for example, a NOR type cell (see FIG. 2) and are arranged in a matrix as a whole. And n in the row direction
It is divided into blocks BK0 to BKn-1.

In the NOR type cell shown in FIG. 2, the drains of the plurality of cell transistors Q are commonly connected to one bit line BL, and correspond to the control gates of the plurality of cell transistors Q, respectively. The word lines WL are connected, and the sources of the plurality of cell transistors Q are commonly connected to one source line SL in block units.

The operating principles of the cell transistor Q and the NOR type cell are well known, and the description thereof is omitted here. The address buffer 11 has, for example, 18-bit address signals A0 to A through an address input terminal.
17 is input from outside. The predecoder 12 decodes an address signal (internal address signal) from the address buffer 11.

The row decoder 13 is connected to the predecoder 12
And a word line driver for supplying a predetermined voltage to a word line in accordance with the decoded output by performing row selection of the memory cell array 10 by decoding a row address signal from the memory cell array 10.

The column decoder 14 is used for the predecoder 1
2 is decoded. The column gate 15 is controlled by a decode output of the column decoder 14 and selects a column of the memory cell array 10.

The sense amplifier 16 is connected to the column gate 15
Connected to the memory cell, senses and amplifies read information from the memory cell, and outputs the amplified signal. In addition, according to various operation modes of the EEPROM, a flag signal (a determination result flag PVOK for write verification, a determination result flag E for erase verification,
VOK, judgment result flag LCKOK of leak check)
Output function.

An input / output circuit (I / O buffer) 17 is connected to the sense amplifier 16, and inputs and outputs, for example, 16-bit input / output data D0 to D15 with the input / output terminal. The source decoder 18 controls each of the blocks BK0 to BKn-
A source line driver for selecting one source line and supplying a predetermined voltage to the source line according to the decode output.

The bit line boosting circuit 20 supplies a high voltage necessary for a write operation to the bit line via the column gate 15. The word line / source line boosting circuit 21 supplies a high voltage required for a write operation and an erase operation to the word line driver of the row decoder 13 and the source line driver of the source decoder 18 in order to apply the high voltage to the word line and the source line. .

The control circuit 22 controls the operation of each section in the EEPROM, and is connected to a chip enable (/ CE) input terminal, an output enable (/ OE) input terminal, and a write enable (/ WE) input terminal.

Address counter 23 for generating addresses
Are addresses (row address Ax, column address Ay) for designating addresses of target blocks and memory cells in automatic writing or automatic erasing.
Generate

The selection circuit 24 selects an address signal from the address buffer 11 during normal operation and supplies it to the predecoder 12, and selects an address signal output from the address counter 23 during automatic writing or automatic erasing. Then, the data is supplied to the predecoder 12.

The command circuit 25 decodes a command signal based on a combination of an address signal from the address buffer 11 and an input signal passed through the input / output circuit 17, and outputs various control signals.

The cycle counter 26 counts the number of times of writing or erasing on the memory cell array 10. 27 is a timer circuit. The PLA (programmable logic array) 28 realizes the above-described automatic writing function and automatic erasing function, and is configured to control a sequence operation as described later.

The PLA 28 is connected to the command circuit 2
5, various outputs of the cycle counter 26 and the timer circuit 27 and various flag signals (P
VOK, EVOK, LCKOK), outputs a PLA code signal, and supplies it to the bit line boosting circuit 20, word line / source line boosting circuit 21, address counter 23, cycle counter 26, and timer circuit 27.

As described above, the memory cell array 10 is provided with a redundancy circuit in order to rescue a defective cell found in an inspection process in an EEPROM manufacturing stage and to improve a manufacturing yield.

If the characteristics of writing or erasing data to the memory cells of the main memory cell array are deteriorated to a predetermined level or less at the stage of using the EEPROM, if necessary, the writing characteristics or erasing characteristics are deteriorated thereafter. A function of automatically replacing a memory cell with a redundant memory cell instead of a cell may be provided.

Although not shown, the redundant circuit has redundant memory cells (Redundancy cells) for several rows and a spare row decoder. Further, when data writing characteristics or erasing characteristics of the main memory cell array are deteriorated to a predetermined level or less at the stage of using the EEPROM, the characteristic deterioration is automatically performed by replacing the deteriorated cells with redundant memory cells. What is necessary is just to provide a cell detection circuit and a replacement control circuit.

FIG. 3 is a flowchart showing an example of the flow of an automatic write sequence under the control of the PLA 28 in FIG. The feature of the automatic write sequence in the flash EEPROM of the present embodiment is that it is executed from write verify. That is, normally, (1) write and (2) write verify are performed until the write is completed. In the present invention, after write verify is performed first, write and write verify are repeated. In the flowchart of FIG. 3 (Start indicates the start of the sequence and End indicates the end of the sequence), after the write command is recognized, the set value PC of the cycle counter is reset (PC = 0) (Step A1), It is determined whether or not the designated address is designated as a write / erase prohibition state (step A2).
If NO, the sequence ends, and the sequence is not prohibited (Un
If protect = YES), start with write verify (step A3 to step A5).

The first write verify operation is performed as follows. First, write verify voltage (Prog
ram Verify Voltage: PV voltage) is set up (step A3), and read (READ) is performed for 500 ns (step A4). Read data READ
It is determined whether or not -DATA is equal to the write input data INPUT-DATA (step A5). If the read data and the write input data are equal, no write is necessary, so the write verify voltage is reset (Reset) (Step A6), and the sequence ends.
If NO, a normal write operation is performed.

The flow of the write operation is basically the same as the conventional one. Specifically, a series of controls for verifying whether or not data writing is correctly performed by reading data from the memory cells after writing data to the memory cells are performed. Is repeated as necessary until writing is correctly performed.

In the present embodiment shown in FIG. 3, the number of repetitions of write and write verify is counted up (PC = PC + 1) by the write counter PC (step A16) and controlled. In the present embodiment, the maximum number of repetitions is set to 320 (step A7), and when the number of repetitions exceeds that, it is determined that the memory cell is abnormal and the write voltage is reset (step A8). ) With an error flag (Error Flag)
Is set (step A9), and the sequence ends.
If the maximum number of times of writing has not yet been reached, writing and write verify are repeated (step A1).
0 to step A15). At this time, the time width of the write pulse is changed according to the number of write repetitions (Step A11, Step A12). For example, 2 μs is used for the first to fifteenth write times (PC <16).
(Step A13), 10 μs from the 16th to 23rd times (16 ≦ PC <24) (Step A14),
100 μs from the 24th time to 320 times (PC ≧ 24)
(Step A15).

FIG. 4 shows an example of the entire flow (flowchart of the main routine) of the automatic erase sequence under the control of the PLA 28 in FIG. FIGS. 5 to 8 show steps B6, B8, and B in FIG.
9, details of step B12. In this automatic erasing sequence, similarly to the automatic writing sequence, prior to writing and erasing, write verification and erasure verification are respectively performed, and unnecessary writing and erasing are omitted.

FIG. 5 shows an example of the flow of the pre-erase write operation for the main body cell, FIG. 6 shows an example of the flow of the pre-erase write operation for the redundancy cell before the defective replacement, and the main body cell after the defective replacement, and FIG. FIG. 8 shows an example of the flow of the verify operation, and FIG. 8 shows an example of the flow of the leak check and the self-convergence operation.

The operation of this embodiment shown in the flowcharts of FIGS. 4 to 8 will be described. As can be seen from the flowchart of the entire erase operation shown in FIG. 4, after the recognition of the erase command,
The block selection address counter BLKAdd is set to 0 (step B1), the cycle counter PC is set to 0 (step B2), and the write confirmation flag RDBIT before erasure of the redundancy cell before defective replacement and the main body cell after defective replacement is set to "L". "Reset to level (RDB
IT = L) (step B3). Thereafter, the judgment result flag PVOK for write verification, the judgment result flag EVOK for erase verification, and the judgment result flag LCKOK for leak check are reset (PVOK, EVOK, LCOK).
KOK = L) (step B4).

Then, it is determined whether or not the designated address is designated as a write / erase inhibit state for each block (step B5). If not, the erase operation is started from the pre-erase write (step B6). At this time, the block selection address (BLK Add) is counted up by a counter (BLK Add = BLK Add + 1) (step B1).
7) Specify that the erase operation is performed in order from BLK Add = 0 (block BK0) to 1 (block BK1), 2 (block BK2),..., 10 (block BK10).

In the flow of the erasing operation, LCKOK is set to the “H” level as necessary (LC
KOK = H) is checked (step B11),
EVOK is set to "H" level (EVOK
= H) is checked (step B14).

In the flowchart of FIG. 4, the pre-erase write (Block PV) is performed for the main cell in block units.
&Program; Pre-Program) (Step B6)
As can be seen from the flowchart shown in FIG. 5, after resetting the column address Ay and the row address Ax (step C1), the write sequence described above counts up the column address Ay (AY = AY + 1) (step C3), Ax count up (A
(X = AX + 1) is added (step C6), a block to be erased is selected, and the process is repeated to write data to the main cells of all addresses. At this time, the word line voltage is reset (step A6) to the read voltage Vcc before the transition to the row selection after the end of the column selection. The other operations are the same as those of the write operation of FIG. 3, and therefore are denoted by the same reference numerals and description thereof will be omitted.

Write before erasure (Spare / Fail Row Program) to the redundancy cell before defective replacement and the main cell after defective replacement in the flowchart of FIG.
6 is shown in FIG. When the cell is not replaced with a redundancy cell, a spare cell for redundancy is selected. When the cell is replaced with a redundancy cell, a main cell before replacement is selected (step D1). Then, writing is performed using a write pulse having a time width of 10 μs. (Step D2, Step D3), Write verify is not executed (Step D4 to Step D10). The reason why the write verify is not executed is that the result of the write verify becomes NG when the write defective cell is replaced.

It should be noted that the redundancy column address A
Y and the row address AX are addresses stored in the defective address storage circuit of the redundant circuit. Block erase verify (Block EV) in the flowchart of FIG.
FIG. 7 shows the operation of block erase (Block Erase). Starting from the erase verify operation (steps E1 to E1).
Step E4), the threshold value Vth of the cell is set to a predetermined value (for example, 3
V) (steps E2 to E18). In other words, the cell array area to be erased is set as a block unit, and the erase and erase verify processing in the block unit for each block to be erased are repeated so as to be executed for all the addresses, so that a plurality of blocks to be erased are divided into blocks. Automatically erase serially every time.

FIG. 8 shows the operations of the block leak check and the self-convergence (Block LCK & Conv) in the flowchart of FIG. Self-convergence is performed for each bit line (for each column) (step F1, step F2). At this time, as a result of reading by the sense amplifier using the leak check load transistor (step F3), when there is no bit line leak (for example, the leak current value is 5 μA or less), that is, the read state of the “0” write cell. In this case, the leak check is OK (step F5).
-Step F8).

Contrary to the above, when there is a bit line leak (for example, the leak current value is 5 μA or more), that is, “1”
When the read state of the write cell is set, the leak check is NG. In the case of the leak check NG, the threshold of the over-erased memory cell causing the bit line leak is controlled to be high by the operation of the self-convergence (Convergence) so that the bit line leak does not occur (steps F9 to F9).
Step F14).

The self-convergence operation is performed by setting all word lines to 0 V and applying a self-convergence voltage (for example, 5 V) to the selected bit line (step F13). It is performed in a state equivalent to the case where it is set to.

The number of times of erasure and self-convergence is counted up by the counter PC (step F15). Unlike the above-mentioned write operation, it is determined whether or not the total number of times of erasure and self-convergence is a maximum of 3072. (Step F10).

As described above, the features of the automatic erase sequence in the flash EEPROM are as follows. (1) Write verification of write-before-erase is first performed on a block basis, write-before-erase and write-verify are performed until write-end is completed, and then erase-verify and subsequent erase and erase-verify are performed. In addition, detection of over-erased memory cells for each bit line after erasing and control of the threshold value of the over-erased memory cells are also performed. When erasing a plurality of blocks, the above operation is continuously performed for each block.

(2) In the pre-erase write, the write address is automatically counted up in order to write to all the memory cells in the designated block.

(3) In the pre-erase write, the pre-erase write is also performed on the redundancy cell before the defective replacement and the main body cell after the defective replacement. (4) In the erasing and erasing verification, an erasing voltage for a fixed pulse time is applied, and erasing verification is performed for each erasing to determine whether the threshold value of the memory cell is equal to or less than a predetermined value.
Erase and erase verify are repeated until it is confirmed that the threshold values of all the memory cells in the block are equal to or smaller than a predetermined value.

(5) After all memory cells in the block have passed the erase verify, a leak check which is an over-erased memory cell detection process is performed. In the leak check, all word lines are set to 0 V, a bit line for one address is selected, and it is determined whether or not the selected bit line has a bit line leak due to an over-erased memory cell.

(6) When the result of the leak check is OK, the erase sequence is terminated. When the result of the leak check is NG (when it is determined that the bit line has the over-erased memory cell), the erase sequence is over. A self-convergence process as threshold control of the erased memory cell is executed. The self-convergence process includes:
A self-converging voltage is applied to the selected bit line for a certain period of time while all word lines remain at 0 V, and the threshold value of the overerased memory cell is raised so as to fall within a desired threshold distribution.

(7) After the self-convergence process, the leak check is performed again to determine whether the self-convergence process has been correctly performed. (8) After the self-convergence process is once executed, the erase verify is always executed again to check whether or not the threshold values of all the memory cells are equal to or less than a predetermined value.

(9) In the erase verify after the self-convergence process, when it is confirmed that the threshold values of all the memory cells are equal to or less than a predetermined value, the erase sequence is terminated.
When it is confirmed that the threshold value of some of the memory cells has exceeded a predetermined value, the erase operation is performed again, and the self-convergence process and the erase operation are repeated until both the leak check and the erase verify operation are determined to be OK.

The flash E of the present embodiment as described above
In an EPROM, by rewriting data in a memory cell by an automatic writing sequence and an automatic erasing sequence, the threshold value of a cell after writing is set to a predetermined distribution width after writing without unnecessarily prolonging the writing time. It becomes possible to control. Further, since a verify operation is performed at the beginning of the process to omit writing and erasing to cells that do not need to be written or erased, overwriting and overerasing are eliminated, and threshold control is stabilized.

Further, for cells written up to a predetermined threshold value, the threshold values of the cells become uniform without further stress. After erasing, even when an over-erased memory cell occurs, the self-converging voltage is applied only to the bit line where the over-erased memory cell exists, so that the threshold value of the cell is controlled to a predetermined distribution width without applying unnecessary stress. It becomes possible to do.

Further, since almost the same operation is performed in the sequence of the automatic writing and the automatic erasing,
The circuit can be simplified. That is, in the erase sequence, it is necessary to perform writing before erasing. Since the data before erasure includes a mixture of "1" data and "0" data, if the pre-erase writing is performed in that state, the following two problems occur. (1) The threshold value Vth of the cell of “0” data written from “1” data differs from the threshold value Vth of the cell of “0” data written to “0” data. Causes a variation in the threshold value Vth. (2) Additional writing is performed on "0" data, which causes cell deterioration due to writing.

As a countermeasure, in the pre-erase write, the data that is already "0" is not written, and only the "1" data is written. In other words, starting from verify at the time of programming before erasure, it is determined whether the data is "0" data or "1" data, and writing is performed only on the "1" data cells that need to be written.
By adjusting the threshold values Vth of the cells, stable performance can be realized.

Further, by adopting such a sequence starting from the verification in all modes, the circuit configuration can be simplified, and by sharing the logic, the circuit area can be reduced, and the cost can be reduced by reducing the chip size. Can be realized. Also, by unifying the sequence,
Design time can be shortened and design efficiency can be improved.

Therefore, data can be rewritten stably, and a highly reliable memory device can be provided. The EEPROM of the above embodiment is used.
As a boosting circuit for boosting the power supply voltage to obtain a high voltage such as a writing voltage or an erasing voltage, a multistage cascaded charge pump circuit and a voltage limiting circuit connected to the last stage charge pump circuit It is possible to configure.

When data is written, the higher the write voltage used, the shorter the time required for data write can be. However, if the write voltage is too high, overwriting occurs at the time of data write.

In order to avoid this problem, it is assumed that the write voltage is gradually increased to perform the data write in a plurality of times, and that the data write and the read operation after the write are repeatedly performed. A method (intelligent write method) of terminating the write operation when the data becomes equal to the write data may be adopted.

In this case, in order to set the write voltage and the erase voltage to optimal values, it is possible to provide a voltage adjusting circuit on the output side of the booster circuit and control as follows.
That is, after writing or erasing data to or from a memory cell, a series of controls for verifying whether data writing or erasing is correctly performed by performing data reading from the memory cell are performed. The control is repeated as necessary until writing or erasing is correctly performed. When the number of times of execution of a series of controls (the number of times of verification) is held, the number of times of verification is compared with a predetermined number of times, and the voltage is determined according to the comparison result. The control data for controlling the setting means is set to automatically adjust and control the voltage adjusting circuit so that the output voltage (write voltage or erase voltage) of the booster circuit becomes an optimum value. It is stored in the sex storage means.

In this case, if the number of times of verification is larger than the set number of times, the output voltage of the booster circuit is controlled so as to increase the writing or erasing ability. By controlling the output voltage of the booster circuit to be lower in order to lower the erasing ability, it is possible to automatically adjust the output voltage of the booster circuit to an optimum value. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0078]

As described above, according to the semiconductor memory device of the present invention, it is possible to reliably control the cell threshold at the time of automatic writing and automatic erasing in a flash EEPROM, thereby improving performance and reliability. .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram schematically showing an overall configuration of a NOR flash EEPROM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a NOR type cell in the memory cell array in FIG. 1;

FIG. 3 is a flowchart showing an example of the flow of an automatic write sequence in the flash EEPROM of FIG. 1;

FIG. 4 is a flowchart showing an example of the entire flow (main routine) of an automatic erase sequence in the flash EEPROM of FIG. 1;

FIG. 5 is a flowchart showing an example of the flow of a pre-erase write operation for a main body cell corresponding to step B6 in FIG. 4;

FIG. 6 is a flowchart showing an example of a flow of a pre-erase write operation for a redundancy cell and a main body defective replacement cell corresponding to step B8 in FIG. 4;

FIG. 7 is a flowchart showing an example of the flow of an erase and erase verify operation corresponding to step B9 in FIG. 4;

FIG. 8 is a flowchart showing an example of the flow of a leak check and self-convergence operation corresponding to step B12 in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Memory cell array BK0-BKn-1 ... Block 11 ... Address buffer 12 ... Predecoder 13 ... Row decoder 14 ... Column decoder 15 ... Column gate 16 ... Sense amplifier 17 ... Input / output (I / O) circuit 18 ... Source decoder 20 ... Bit line booster circuit 21 ... Word line / source line booster circuit 22 ... Control circuit 23 ... Address counter (address generation circuit) 24 ... Selection circuit 25 ... Command circuit 26 ... Cycle counter 27 ... Timer circuit 28 ... PLA circuit

Claims (20)

[Claims] 1. A memory cell array in which a plurality of nonvolatile memory cells having a two-layer gate structure in which a floating gate and a control gate are stacked are arranged, and an object of data writing in the memory cell array based on a write command input An automatic write control circuit for automatically controlling a write process by designating one or a plurality of memory cells, wherein the automatic write control circuit first performs a write verify at the start of automatic write, and A semiconductor memory device characterized by repeating writing and write-verify for a memory cell that needs to be written as a result of verification until writing is completed. 2. The semiconductor memory device according to claim 1, wherein said automatic write control circuit controls the amount of charge injected into said floating gate in accordance with the number of repetitions of said write and write-verify. Storage device. 3. The semiconductor memory device according to claim 2, wherein the control of the amount of injected charges is performed by controlling a time width of a write pulse. 4. A memory cell array in which a plurality of nonvolatile memory cells having a two-layer gate structure in which a floating gate and a control gate are stacked are arranged, and data to be erased in the memory cell array based on an erase command input An automatic erase control circuit for automatically controlling an erase process by designating a plurality of memory cells,
Wherein the automatic erasure control circuit first performs erasure verification at the start of automatic erasure, and repeats erasure and erasure verification on the memory cells requiring erasure as a result of the erasure verification until erasure is completed. Storage device. 5. The semiconductor memory device according to claim 4, wherein said automatic erase control circuit further performs detection of an over-erased memory cell for each bit line after erasing and control of a threshold value of the over-erased memory cell. Semiconductor storage device. 6. The semiconductor memory device according to claim 4, wherein at the time of said erasing and erasing verification, an erasing voltage for a fixed pulse time is applied, and erasing is performed each time erasing to determine whether a threshold value of a memory cell is equal to or less than a predetermined value. A semiconductor memory device wherein verification is performed, and erasure and erase verification are repeated until it is confirmed that the threshold values of all memory cells are equal to or less than a predetermined value. 7. A memory cell array in which a plurality of nonvolatile memory cells having a two-layer gate structure in which a floating gate and a control gate are stacked are arranged, and data to be erased in the memory cell array based on an erase command input An automatic write / erase control circuit for automatically controlling processing by designating a plurality of memory cells to be used, wherein the automatic write / erase control circuit first performs write verification of pre-erase write, and As a result, if writing before erasing is necessary, write and write verify are repeated until writing is completed,
A semiconductor memory device wherein erase verify is performed at the time of completion of pre-erase write, and thereafter, erase and erase verify operations are repeated until the erase is completed. 8. The semiconductor memory device according to claim 7, wherein said memory cell array comprises a plurality of memory cell blocks divided in a row direction. 9. The semiconductor memory device according to claim 8, wherein said automatic write / erase control circuit serially designates a plurality of memory cell blocks and automatically designates a plurality of memory cells in the designated memory cell block. A semiconductor memory device characterized by controlling processing. 10. The semiconductor memory device according to claim 7, wherein said automatic write / erase control circuit further performs detection of an over-erased memory cell for each bit line after erasing and control of a threshold value of the over-erased memory cell. A semiconductor memory device characterized by the following. 11. The semiconductor memory device according to claim 7, wherein at the time of writing before erasure, a write address is automatically counted up to perform writing to all memory cells in a specified memory block. A semiconductor memory device characterized in that: 12. The semiconductor memory device according to claim 7, wherein in the pre-erase write, the pre-erase write is also performed on the redundancy cell before the defective replacement and the main body cell after the defective replacement. . 13. The semiconductor memory device according to claim 7, wherein at the time of said erasing and erasing verification, an erasing voltage for a fixed pulse time is applied, and erasing is performed each time erasing to determine whether a threshold value of a memory cell is equal to or less than a predetermined value. A semiconductor memory device wherein verification is performed, and erasure and erase verification are repeated until it is confirmed that the threshold values of all memory cells are equal to or less than a predetermined value. 14. The semiconductor memory device according to claim 13, wherein said automatic write / erase control circuit further checks that threshold values of all memory cells are equal to or less than a predetermined value by said erase verify. A semiconductor memory device which performs a leak check which is an over-erased memory cell detection process. 15. The semiconductor memory device according to claim 14, wherein in said leak check, all word lines are set to 0 V, a bit line for one address is selected, and an over-erased memory cell is set to the selected bit line. A semiconductor memory device, which is performed by determining whether or not there is a bit line leak due to the following. 16. The semiconductor memory device according to claim 15, wherein when the result of the leak check is OK, the erase sequence is terminated, and when the result of the leak check is NG, the threshold control of the over-erased memory cell is performed. A semiconductor memory device which performs a certain self-convergence process. 17. The semiconductor memory device according to claim 16, wherein said self-convergence processing raises a threshold value of an overerased memory cell by applying a self-convergence voltage to a selected bit line for a predetermined time while all word lines remain at 0V. A semiconductor memory device characterized by the above-mentioned. 18. The semiconductor memory device according to claim 16, wherein the automatic write / erase control circuit performs the leak check again after the self-convergence processing, and determines whether the self-convergence has been correctly performed. A semiconductor memory device. 19. The semiconductor memory device according to claim 16, wherein said automatic write / erase control circuit executes said self-convergence processing and then executes erase verify again to set thresholds of all memory cells to a predetermined value or less. A semiconductor memory device, which checks whether or not it is. 20. The semiconductor memory device according to claim 19, wherein said automatic write / erase control circuit confirms at the time of erase verify after said self-convergence processing that threshold values of all memory cells are equal to or less than a predetermined value. In this case, the erase sequence is terminated, and if it is not confirmed that the threshold value of some of the memory cells is equal to or less than the predetermined value, the erase is performed again, and both the leak check and the erase verify are determined to be OK. A semiconductor memory device characterized by repeating self-convergence processing and erasure until the semiconductor memory device.