JPH10283302A - Method and system for supplying data to bus connected to plural processors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the delay of starting data access and to improve flexibility by deciding whether or not a bus is usable to transfer data after the data is accessed in a memory, and transferring the data to the bus when the bus is usable. SOLUTION: A data flow chip 20 supplies data to processors 2-1 to 2-n by using a bus 60 and receives data from a memory 30 through a bus 70. For example, when the processor 2-1 tries to read data out of the memory 30, the data flow chip 20 should have the right to access the data bus 60. When the time when the data flow chip 20 obtains the right to access the data bus 60 is determined, the system should consider the use state of the data buses. Therefore, there is the possibility that many read requests are suspended at an arbitrary point of time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a method and system for data access in a memory controller, and more particularly to servicing a plurality of processors, such as a buffered memory controller, especially an SMP memory controller. And a system for enabling low-latency data access with a controller that provides a low latency data access.

[0002]

BACKGROUND OF THE INVENTION Current memory controllers, such as SMP memory controllers, which service multiple processors, typically use a single data bus for all processors. Whenever a processor attempts to read data from memory, the memory controller must determine how to grant the processor access to its data bus. In that case,
The controller must take into account the bus usage by other processors.

When the execution of a read instruction for a particular processor begins, the data bus can be reserved, but no other processor can use the bus until the read instruction is completed. In such a system, the speed of the system will be significantly reduced. Rather, the processor typically arbitrates for the bus and uses multiple passline buffers to store data until the bus is available.

At the beginning of a data request, it is generally not possible to determine when a data bus connected to a plurality of processors can service the request. Buses are in use for various reasons. The read request may be pending. Usually, the address bus and the data bus are independent of each other. When an address is issued, the address is tagged. The data read from the memory is associated with the corresponding tag. This allows the system to issue multiple addresses without having to wait for data for a particular request to be returned. Further, the data need not be returned in the order in which the requests were issued. Thus, many read requests can be pending at any one time. The processor can also issue a write request and place the write data on the bus.

[0005] Thus, when a processor issues a particular read request, it is unclear when the bus will be available to transfer data read from memory to the processor. Conventional systems typically store data temporarily in a buffer because it is unknown when the bus will be available.

By storing data in a buffer,
While the controller can support multiple processors, there are drawbacks. The first data that the processor receives from the memory controller is delayed because data from the memory must enter the memory controller before loading into the passline buffer. This data is held in a passline buffer until the controller can arbitrate for the bus. Data is stored in a buffer, whether the bus is immediately available or unavailable for multiple cycles.

In a typical memory controller servicing a single processor, data is not buffered. If the data is not buffered in a typical system using multiple processors, one processor can request the bus in anticipation of receiving the read data. In that case, the bus is reserved for that processor,
Thus, no other processor can access the bus during the time required for the read operation. Therefore,
Such a non-buffered implementation is not suitable for a multiprocessor system.

Similarly, when buffers are not used in a multiple processor system, the data bus can be divided into multiple time windows if the exact latency of the transfer from memory is known. When a bus is requested, it is known that after a given number of cycles the bus will be used for that request. The flexibility of when data can be transferred to the processor is limited because the processor must request access to the bus well before data transfer on the bus begins. Once a bus has been arbitrated, it cannot be used later for any other purpose.

[0009]

Therefore, there is a need for a system and method for providing data to a plurality of processors, which system has a low initial data access delay and high flexibility. The present invention addresses such a need.

[0010]

SUMMARY OF THE INVENTION The present invention provides a method and system for providing data to a bus in a computer system. The computer system includes a memory. The bus can support a plurality of processors.
The method and system determine whether a bus is available for transferring data after the data has been accessed in memory. The method then transfers the data to the bus, if available.

In accordance with the systems and methods disclosed herein, the present invention provides for a highly flexible data transfer with low initial data access delay.
Thereby, overall system performance is improved.

[0012]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in multiprocessor systems. The following description is provided to enable one of ordinary skill in the art to practice the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will readily occur to those skilled in the art, and the general principles set forth herein may be applied to other embodiments. Accordingly, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

FIG. 1 is a schematic block diagram of a system 1 including a plurality of processors 2 such as an SMP system.
In the illustrated example, there are n processors 2-1 to 2-n. An address bus 40, an arbitration bus 50, and a data bus 60 are connected to each processor. In the system 1 shown in FIG. 1, an address control chip 10 controls addressing. The address control chip 10, together with the data flow chip 20, constitutes a memory controller that controls access to the memory 30.

The data flow chip 20 includes a bus 60
To supply data to the processors 2-1 to 2-n, and receive data from the memory 30 via the bus 70.
A certain processor, for example, processor 2-1 has memory 3
When trying to read data from 0, the data
The flow chip 20 must be granted access to the data bus 60. In determining when the data flow chip 20 can gain access to the data bus 60, the system 1 must take into account the usage of the data bus 60 by the remaining processors 2.

At the beginning of a data request, it is generally not possible to determine when the data bus 60 will be available to service the request. Buses are in use for various reasons. The read request may be pending. Usually, the address bus 40 and the data bus 60 are independent of each other. Thus, system 1 can issue multiple addresses without having to wait for data for a particular request to be returned. Further, the data need not be returned in the order in which the requests were issued. Thus, many read requests can be pending at any one time. Also, one of the processors 2 can issue a write request and place the write data on the bus.

FIG. 2 shows a conventional data flow chip 2.
FIG. 2 is a more detailed block diagram of the address 0, the address control chip 10, and the memory 30. When one of the processors 2 issues a particular read request, it is not known when the data bus 60 will be available to transfer the data read from the memory 30. Data is typically temporarily stored in buffer 26 because it is not known when data bus 60 will be available.

Normally, data read from memory 30 is transferred via bus 70 to latch 21 in data flow chip 20. Next, the data is ECC inspection /
The error is checked in the correction logic circuit 22. Next, the ECC check / correction logic circuit 22 transfers the data to the second latch 24. Data is transferred to buffer 26 on the next clock cycle. Buffer 26 stores data until control logic 28 determines that data bus 60 is available to transfer data to the appropriate one of the plurality of processors 2.

Typically, address control chip 10 informs control logic 28 when data bus 60 can receive data from data flow chip 20. In a conventional system, the address control chip 10
The data flow chip 20 is controlled mainly by three commands, MEM_CMD, SYS_CMD, and SYS_GRANT.

MEM_CMD, provided by line 91, notifies data flow chip 20 of the arrival of data from memory 30 via bus 70. SYS_CMD provided by line 92 indicates that data must be supplied to data bus 60 to data flow chip 20.
Notify. The SYS_GRANT command, provided by line 93, notifies data flow chip 20 that data bus 60 has been acquired and specifies the amount of data that must be provided to data bus 60. In a conventional system, the address control chip 10 arbitrates the data bus 60. When the access right to the data bus 60 is obtained, the address control chip 10 sets the SYS_GR
Issue ANT. The SYS_GRANT command is sent to data bus 6
0 informs data flow chip 20 that it is available to receive data.

It should be noted that it is possible to construct a bufferless multiprocessor system, but this is not usually done. In one typical unbuffered system, a memory controller can request a bus in anticipation of receiving read data. But,
The bus would be reserved for that transfer during the read operation. Similarly, if the latency of a transfer from memory is known, the data bus can be divided into multiple time windows. When a read is requested, the bus must be used for that request after a predetermined number of cycles. This limits the flexibility of the system. Thus, unbuffered configurations are generally unsuitable for multiprocessor systems.

The processor 1 according to the system 1 shown in FIG.
Can access memory 30 relatively quickly, but those skilled in the art will recognize that buffer 26 creates a disadvantage. Since data from memory 30 must first enter data flow chip 20 and then load into buffer 26, the first data received by one of processors 2 is delayed. This data remains in the buffer 26 until the address control chip 10 arbitrates the bus 60. Data is stored in the buffer 26 whether the data bus 60 is immediately available or unavailable for multiple cycles. Therefore, a delay may occur when transmitting the first data from the memory 30 to one of the processors 2.

The present invention provides a method and system for providing a flexible multiprocessor system with reduced initial data access latency. The present invention is described with respect to a memory controller that includes a data flow chip and an address chip. However, those skilled in the art will readily recognize that the method and system will work well with other types of memory controllers.

To more specifically illustrate the method and system according to the present invention, please refer to FIG. 3, which shows a block diagram of one embodiment of such a system. The system 200 of the present invention includes several components similar to conventional systems. Therefore, these components are given the same numbers as the conventional components shown in FIG.

Referring now to FIG. 3, data from memory 30 'is received by data flow chip 20'. In the preferred embodiment, the address control chip 1
0 'controls the data flow chip 20'. In one embodiment, the data is provided to latch 21 'and ECC check / correction logic 22'. Next, the system 200
Determine if data bus 60 'is available to receive data. In the preferred embodiment, this is done by the control logic 28 'determining whether a SYS_GRANT command has been received on line 93'.

The first bypass 202 provides data directly from the ECC check / correction logic 22 ′ to the multiplexer 206. If data bus 60 'is found to be available, the first bypass 202
Data input to 06 is supplied to data bus 60 '. If data bus 60 'is not immediately available, data is provided to latch 24'. Next, the system 200 sends the data bus 60 'to receive the data.
Is determined to be available. In the preferred embodiment, control logic 28 'once again determines whether a SYS_GRANT command has been received on line 93'.

The data from the second bypass 204 is supplied to the multiplexer 206. When the data bus 60 ′ becomes available, the data input from the second bypass 204 to the multiplexer 206 is transferred to the data bus 60 ′.
Supplied to In the preferred embodiment, this occurs one cycle after the data is input to the data flow chip 20 '. If data bus 60 'is not available, data is provided to buffer 26'. When data bus 60 'becomes available, the data provided from buffer 26' to multiplexer 206 is transferred to data bus 60 '. In a preferred embodiment, this is
It occurs two or more cycles after the data is received at the data flow chip 20 '.

The system 200 avoids unnecessary disadvantageous situations during the initial data transfer to the processor associated with the conventional buffered system shown in FIG. Due to the first bypass 202, one of the processors 2 can receive the first data as fast as in an unbuffered system. The system 200 also accommodates cases where the bus is not immediately licensed for a particular read operation.

If the data bus 60 'is not immediately licensed for a read operation, the system 200 will
Advance by cycles and perform a retest to determine if data bus 60 'is available. data·
If bus 60 'is available, the data is transferred to data bus 60'. If not, system 200 waits until data bus 60 'is ready.
Data can be held in the buffer 26 '. Therefore, the data is supplied to an appropriate one of the processors 2 as soon as possible.

Further, the system 200 is more flexible than a typical unbuffered system. It is not necessary to arbitrate for data bus 60 'long before data from memory 30' can be transferred to data bus 60 '. In the preferred embodiment, once the system 200 has arbitrated the data bus 60 'by the address control chip 10', after a few cycles the bus will be granted its operation for the required length.
Thus, system 200 is not divided into windows of a predetermined length when using bus 60 '.

A method and system for providing data to a plurality of processors has been disclosed wherein the initial data access has a low delay and high flexibility.

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) A method for supplying data to a bus connected to a plurality of processors in a computer system including a memory and a memory controller for controlling the memory, the method comprising: (a) storing data in the memory; Determining whether the bus is available to transfer the data after the data has been accessed; and (b) transferring the data to the bus if the bus is available. And a method comprising: (2) said step (b) comprises: (b1) transferring said data to said bus when said bus is available; and (b2) latching said data when said bus is not available. Transferring; (b3) determining whether the bus has become available for transferring the data; and (b4) if the bus has become available for transferring the data. Transferring the data from the latch to the bus. (3) (c) The method of (2) above, further comprising storing the data from the latch when the bus is not available. (4) The method according to (3), wherein the step (c) further comprises the step of: (c1) supplying the stored data to the bus when the bus becomes available. (5) The step (b2) is one of the steps (a)
The method according to (2), which is performed after a cycle. (6) The step (c1) is the step (a) 2
The method according to (4), performed after or after the cycle. (7) The method of (6) above, wherein step (a) further comprises: (a1) searching for a command indicating that the memory controller has taken ownership of the bus. (8) The above (7), wherein the step (a) of determining whether the bus is usable further includes the step of: (a2) determining an amount of data that can be supplied to the bus.
The method described in. (9) The method of (8) above, wherein step (b3) further comprises: (b3i) searching for a command indicating that the memory controller has taken ownership of the bus. (10) The method of (9) above, wherein step (c2) further comprises: (c2i) searching for a command indicating that the memory controller has taken ownership of the bus. (11) A system for supplying data to a bus connected to a plurality of processors, comprising: a receiving unit for receiving the data; and a receiving unit coupled to the receiving unit, wherein the bus is provided within a first predetermined period. A first bypass for supplying the data to the bus when the bus becomes available; and a determination means coupled to the first bypass for determining whether the bus is available. Including system. (12) a latch coupled to the receiving means for holding the data; and a latch coupled to the latch, wherein the data is transmitted to the bus when the bus becomes available within a second predetermined period. The system of claim 11, further comprising a second bypass for providing. (13) The system of (12) above, further comprising storage means coupled to said second bypass and said latch for storing said data until said bus is available. (14) The above-mentioned (13), further comprising means for inspecting the data for the presence or absence of an error and correcting the error.
System. (15) The system according to (14), wherein the first predetermined period is immediately after completing the error check and correction of the data. (16) the second predetermined period is one cycle after the step in which the data is input to the receiving means;
The system according to the above (15). (17) The system according to (16), wherein the data stored in the storage unit is transferred two cycles after or after the data is input to the reception unit.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a system corresponding to a plurality of processors.

FIG. 2 is a block diagram of a conventional system for supplying data to a plurality of processors.

FIG. 3 is a block diagram of a system for providing data to a plurality of processors according to the present methods and systems.

[Explanation of symbols]

 1 System 2-1 Processor 1 2-2 Processor 2 2-n Processor n 10 Address control chip 20 Data flow chip 30 Memory 40 Address bus 50 Arbitration bus 60 Data bus 70 Bus

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor David Wayne Victor United States 78681 Round Rock, Texas Newland Drive 3810

Claims (17)

[Claims] A memory and a memory for controlling the memory.
In a computer system including a controller,
A method for providing data to a bus connected to a plurality of processors, comprising: (a) whether the bus is available to transfer the data after the data has been accessed in the memory; And (b) transferring the data to the bus if the bus is available. 2. The method of claim 1, wherein the step (b) comprises: (b1) transferring the data to the bus when the bus is available; and (b2) transferring the data when the bus is not available. Transferring to the latch; (b3) determining whether the bus is available for transferring the data; and (b4) enabling the bus for transferring the data. Transferring the data from the latch to the bus. 3. The method of claim 2, further comprising the step of: (c) storing said data from said latch when said bus is not available. 4. The method of claim 3, wherein step (c) further comprises: (c1) providing the stored data to the bus when the bus becomes available. . 5. The method of claim 2, wherein said step (b2) is performed one cycle after said step (a). 6. The method according to claim 4, wherein said step (c1) is performed two cycles after or after said step (a). 7. The method of claim 6, wherein step (a) further comprises: (a1) searching for a command indicating that the memory controller has taken ownership of the bus. 8. The method according to claim 7, wherein said step (a) of determining whether said bus is available further comprises: (a2) determining an amount of data that can be supplied to said bus. Method. 9. The method of claim 8, wherein said step (b3) further comprises: (b3i) searching for a command indicating that said memory controller has taken ownership of said bus. 10. The method of claim 9, wherein said step (c2) further comprises: (c2i) searching for a command indicating that said memory controller has taken ownership of said bus. 11. A system for supplying data to a bus connected to a plurality of processors, comprising: receiving means for receiving the data; coupled to the receiving means, within a first predetermined time period. A first bypass for supplying the data to the bus when the bus becomes available; and a determining means coupled to the first bypass for determining whether the bus is available. And a system that includes. 12. A latch coupled to said receiving means for holding said data; and a latch coupled to said latch, said data being provided when said bus becomes available within a second predetermined time period. A second bypass for supplying the bus.
System. 13. The system of claim 12, further comprising storage means coupled to said second bypass and said latch for storing said data until said bus is available. 14. The system of claim 13, further comprising means for checking said data for errors and correcting errors. 15. The method according to claim 1, wherein the first predetermined period is immediately after error checking and correction of the data are completed.
5. The system according to 4. 16. The system of claim 15, wherein said second predetermined time period is one cycle after the step of inputting said data to said receiving means. 17. The system according to claim 16, wherein the data stored in said storage means is transferred two cycles or more after the data is input to said receiving means.