JPH10200384A - Delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit by delaying only the rise of inputted pulse signal and reducing delay in the fall of the pulse signal as much as possible to attain reduction of elements consisting of the circuit without lowering the performance and reliability. SOLUTION: A pulse inputted to an input terminal IN of a delay circuit 1 becomes a waveform delaying both in rise and fall of the pulse through an inverter delay circuit part 10 at a connecting part A. When the signal level of the input terminal IN is 'L', a p-channel MOS transistor 11 is turned on and an n-channel MOS transistor 12 is turned off. Therefore, the signal level of the connecting part B is turned to 'H' in spite of the operation at an n- channel MOS transistor 13, a logic is inverted by an inverter circuit 14, and an output terminal OUT of the delay circuit 1 is turned to 'L' level. Thus, the delay circuit 1 can delay only the rise of the pulse signal inputted to the input terminal IN and outputs it from the output terminal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit formed on a semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional delay circuit. The delay circuit shown in FIG. 5 delays only the rising edge of an input pulse signal and causes the falling edge of the pulse signal to fall. Is to be made as small as possible. 5, a delay circuit 50 includes an inverter delay circuit section 59 formed by connecting eight inverter circuits 51 to 58 in series, two p-channel MOS transistors 60 and 61, and two n-channel MOS transistors. It is composed of transistors 62 and 63 and an inverter circuit 64 for logical inversion. The p-channel MOS transistors 60 and 61 and the n-channel MOS transistor 6
Reference numerals 2 and 63 form a NAND circuit.

The above p-channel MOS transistor 60
, The source is connected to the DC power supply VDD, the drain is connected to the drain of the n-channel MOS transistor 62, and the gate is connected to the n-channel MOS transistor 6
2 and constitutes one input terminal of the NAND circuit, and is connected to the output terminal IN of the delay circuit 50. The source of the n-channel MOS transistor 62 is connected to the drain of the n-channel MOS transistor 63, and the source of the n-channel MOS transistor 63 is grounded.

Further, the drain of the p-channel MOS transistor 60 and the n-channel MOS transistor 6
The connection with the drain 2 is connected to the drain of the p-channel MOS transistor 61 to form the output terminal of the NAND circuit, and to the input terminal of the inverter circuit 64. In the p-channel MOS transistor 61, the source is connected to the DC power supply VDD, and the gate is
Inverter circuit 5 connected to the gate of n-channel MOS transistor 63 to form the other input terminal of the NAND circuit and to form the output terminal of inverter delay circuit section 59
8 output terminal. The input terminal of the inverter circuit 51, which is the input terminal of the inverter delay circuit section 59, is connected to the input terminal IN of the delay circuit 50, and the output terminal of the inverter circuit 64 is connected to the output terminal OUT of the delay circuit 50. Is done.

Next, an example of the operation of the delay circuit 50 having the above configuration will be described. In FIG. 5, the output terminal of the inverter circuit 58, the p-channel MOS transistor 61 and the n-channel MOS transistor 6
3 is designated by E, the p-channel MOS transistors 60 and 61 and the n-channel MO
The connection part connecting the drains of the S transistor 62 is
And FIG. 6 is a timing chart showing an operation example of the delay circuit 50 shown in FIG.

As can be seen from FIG. 6, the pulse input to the input terminal IN of the delay circuit 50 has a waveform that is delayed at the point E by the inverter delay circuit 59 in both the rising and falling of the pulse. However, at the point F, the signal level becomes "L" only when the signal level at the input terminal IN of the delay circuit 50 and the signal level at the point E both become "H" by the NAND circuit. Further, at the output terminal OUT of the delay circuit 50, the signal level at the point F is logically inverted by the inverter circuit 64, so that the pulse output from the output terminal OUT is different from the pulse input to the input terminal IN. , Only the rise is delayed, and the fall is a waveform that is not delayed without being affected by the inverter delay circuit unit 59.

FIG. 7 is a circuit diagram showing another example of the conventional delay circuit. The delay circuit 70 shown in FIG. 7 delays only the falling edge of the input pulse signal, and The delay at the rise is made as small as possible. 7, a delay circuit 70 includes an inverter delay circuit section 79 formed by connecting eight inverter circuits 71 to 78 in series, two p-channel MOS transistors 80 and 81, and two n-channel MOS transistors. It comprises transistors 82 and 83 and an inverter circuit 84 for logical inversion. The p-channel MOS transistors 80 and 81 and the n-channel MOS transistors 82 and 83 form a NOR circuit.

The above p-channel MOS transistor 80
, The source is connected to the DC power supply VDD, the drain is connected to the source of the p-channel MOS transistor 81, and the gate is connected to the n-channel MOS transistor 82.
And constitutes one input terminal of the NOR circuit, and is connected to the output terminal IN of the delay circuit 70. The drains of the p-channel MOS transistors 81 are connected to the drains of n-channel MOS transistors 82 and 83, respectively, and the sources of the n-channel MOS transistors 82 and 83 are grounded.

Further, the drain of the p-channel MOS transistor 81 and the n-channel MOS transistor 8
A connection portion between the drains 2 and 83 forms an output terminal of the NOR circuit, and is connected to an input terminal of the inverter circuit 84. The gate of the p-channel MOS transistor 81 is connected to the gate of the n-channel MOS transistor 83 to form the other input terminal of the NOR circuit, and to the output terminal of the inverter circuit 78 forming the output terminal of the inverter delay circuit section 79. Connected. The input terminal of the inverter circuit 71 serving as the input terminal of the inverter delay circuit section 79 is connected to the input terminal IN of the delay circuit 70, and the output terminal of the inverter circuit 84 is connected to the output terminal OUT of the delay circuit 70. Is done.

Next, an operation example of the delay circuit 70 having the above configuration will be described. 7, the output terminal of the inverter circuit 78, the p-channel MOS transistor 81 and the n-channel MOS transistor 8
3 is G, and the connection between the drains of the p-channel MOS transistor 81 and the n-channel MOS transistors 82 and 83 is H.
And FIG. 8 is a timing chart showing an operation example of the delay circuit 70 shown in FIG.

As can be seen from FIG. 8, the pulse input to the input terminal IN of the delay circuit 70 has a waveform that is delayed at the point G by the inverter delay circuit section 79 in both the rise and fall of the pulse. However, at the point H, the signal level becomes "L" only when the signal level of either the input terminal IN of the delay circuit 70 or the point G becomes "H" by the NOR circuit. Further, the delay circuit 7
At the output terminal OUT of 0, the signal level at the point H is logically inverted by the inverter circuit 84, so that the pulse output from the output terminal OUT falls with respect to the pulse input to the input terminal IN. And the rising edge has a waveform that is not delayed without being affected by the inverter delay circuit unit 79.

[0012]

However, in a semiconductor integrated circuit, it is always a problem to simplify the circuit by reducing the number of elements constituting the circuit without deteriorating the performance and reliability. is there. For this reason, in a semiconductor integrated circuit using the delay circuit, it is necessary to reduce the number of elements constituting the circuit without deteriorating the performance and reliability, and to simplify the circuit.

Accordingly, an object of the present invention is to simplify a circuit in a delay circuit used in a semiconductor integrated circuit by reducing elements constituting the circuit without deteriorating performance and reliability. .

[0014]

A delay circuit according to the first aspect of the present invention outputs a signal input terminal to which a signal is input from the outside and a signal input to the signal input terminal with a predetermined time delay. A delay circuit unit, a first switching unit whose switching operation is controlled by a signal input from the signal input terminal, and a switching operation connected in series with the first switching unit and performed by a signal input from the signal input terminal , A third switching unit connected in series with the second switching unit, the switching operation of which is controlled by a signal output from the delay circuit unit, the first switching unit and the third switching unit. An inverting circuit for inverting and outputting a signal level at a connection with the second switching unit, and the first switching unit and the second switching unit. The switching unit performs a switching operation opposite to the signal level of the signal from the signal input terminal, and the first switching unit sets the input terminal of the inverting circuit unit to the “H” level when the first switching unit is in a conductive state. The second switching unit and the third switching unit set the input terminal of the inverting circuit unit to the “L” level when both are brought into the conductive state.

According to a second aspect of the present invention, in the delay circuit according to the first aspect, the signal input from the signal input terminal is:
Only the rise of the signal level is delayed by a predetermined time and output from the output terminal of the inverting circuit section.

In the delay circuit according to a third aspect of the present invention, in the first or second aspect, the first switching section is a p-channel MOS transistor, and the second switching section and the third switching section are n-channel type MOS
It is a transistor.

A delay circuit according to a fourth aspect of the present invention includes a signal input terminal to which a signal is input from the outside, a delay circuit portion that delays a signal input to the signal input terminal for a predetermined time and outputs the delayed signal, A first switching unit whose switching operation is controlled by a signal input from a signal input terminal; and a second switching unit connected in series with the first switching unit and whose switching operation is controlled by a signal output from the delay circuit unit. A switching unit, a third switching unit connected in series with the second switching unit, the switching operation of which is controlled by a signal input from the signal input terminal; and a connection between the second switching unit and the third switching unit. And an inverting circuit for inverting and outputting a signal level in the unit, wherein the first switching unit and the third switching unit include: Performs opposite switching operation to the signal level of the signal from the signal input terminal, a first
When both the switching unit and the second switching unit are turned on, the input terminal of the inversion circuit unit is set to “H” level, and when the third switching unit is turned on, the input terminal of the inversion circuit unit is set to “L”. Level.

According to a fifth aspect of the present invention, in the delay circuit according to the fourth aspect, the signal input from the signal input terminal is:
Only the falling of the signal level is delayed by a predetermined time and output from the output terminal of the inverting circuit section.

The delay circuit according to the sixth aspect of the present invention is the delay circuit according to the fourth or fifth aspect, wherein the first switching section and the second
The switching unit is a p-channel MOS transistor, and the third switching unit is an n-channel MOS transistor.
It is a transistor.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing an example of a delay circuit according to the first embodiment of the present invention. The delay circuit shown in FIG. 1 delays only the rise of an input pulse signal, and delays the rise of the pulse signal. The delay in the downlink is made as small as possible. In FIG. 1, a delay circuit 1 includes an inverter delay circuit section 10 formed by connecting eight inverter circuits 2 to 9 in series, one p-channel MOS transistor 11, and two n-channel M transistors.
It is composed of OS transistors 12 and 13 and an inverter circuit 14 for logical inversion.

The p-channel MOS transistor 11
, The source is connected to the DC power supply VDD, the drain is connected to the drain of the n-channel MOS transistor 12, and the gate is connected to the n-channel MOS transistor 1.
2 and to the output terminal IN of the delay circuit 1. The source of the n-channel MOS transistor 12 is connected to the drain of the n-channel MOS transistor 13, and the source of the n-channel MOS transistor 13 is grounded.

Further, the drain of the p-channel MOS transistor 11 and the n-channel MOS transistor 1
The connection between the drain 2 and the drain 2 is connected to the input terminal of the inverter circuit 14. N-channel type MOS transistor 1
The gate of No. 3 is connected to the output terminal of the inverter circuit 9 which is the output terminal of the inverter delay circuit unit 10. Also,
An input terminal of the inverter circuit 2, which is an input terminal of the inverter delay circuit section 10, is connected to an input terminal IN of the delay circuit 1, and an output terminal of the inverter circuit 14 is connected to an output terminal OUT of the delay circuit 1. .

Next, an operation example of the delay circuit 1 having the above configuration will be described. In FIG. 1, the connection between the output terminal of the inverter circuit 9 and the gate of the n-channel MOS transistor 13 is denoted by A, and the p-channel MOS transistor 11 and the n-channel
A connection portion connecting the drains of the S transistor 12 is denoted by B
And FIG. 2 is a timing chart showing an operation example of the delay circuit 1 shown in FIG.

As can be seen from FIG. 2, the pulse input to the input terminal IN of the delay circuit 1 has a waveform that is delayed at the point A by the inverter delay circuit section 10 in both the rising and falling of the pulse. When the signal level of the input terminal IN is at "L" level, the p-channel MOS transistor 11 is turned on and the n-channel MOS transistor 12 is turned off. Becomes "H" level,
The logic is inverted by the inverter circuit 14, and the output terminal OUT of the delay circuit 1 becomes "L" level.

Here, when the signal level of the pulse input to the input terminal IN changes from "L" level to "H" level, the p-channel type MOS transistor 11 turns off and n
Even if the channel type MOS transistor 12 is turned on, if the point A remains at the “L” level, the n-channel type
Since the OS transistor 13 is off, the signal level at the point B is maintained and does not change from the “H” level, and the signal level at the output terminal OUT does not change from the “L” level. Next, when the point A goes to the “H” level, the n-channel MOS transistor 13 turns on, the point B goes to the “L” level, and the output terminal OUT goes to the “H” level.

Further, when the signal level of the pulse input to the input terminal IN changes from "H" level to "L" level, the p-channel MOS transistor 11 turns on, and
Since the channel MOS transistor 12 is turned off, the signal level at the point B changes from "L" level to "H" level, and the signal level at the output terminal OUT changes from "H" level to "L" level. . Thereafter, when the signal level at the point A changes from “H” level to “L” level, the n-channel MOS transistor 13 is turned off.
Since the n-channel MOS transistor 12 has already been turned off, the signal level at the point B does not change and the output terminal O
The signal level of the UT does not change. In this manner, the delay circuit 1 outputs the pulse signal input to the input terminal IN from the output terminal OUT with only the rising edge delayed.

As described above, the delay circuit according to the first embodiment is a delay circuit that delays only the rise of the signal input from the input terminal IN without deteriorating the performance and reliability of the circuit. Can be reduced in number, and the circuit can be simplified.

Embodiment 2 FIG. 3 is a circuit diagram showing an example of the delay circuit according to the second embodiment of the present invention.
The delay circuit shown in (1) delays only the falling edge of the input pulse signal and minimizes the delay at the rising edge of the pulse signal. 3, the delay circuit 20 includes eight inverter circuits 21 to 28.
Are connected in series to form an inverter delay circuit 29
And two p-channel MOS transistors 30, 31
And one n-channel MOS transistor 32 and an inverter circuit 33 for logic inversion.

The above p-channel MOS transistor 30
, The source is connected to the DC power supply VDD, the drain is connected to the source of the p-channel MOS transistor 31, and the gate is connected to the n-channel MOS transistor 32.
And the output terminal I of the delay circuit 20
N. The drain of the p-channel MOS transistor 31 is connected to the drain of the n-channel MOS transistor 32, and the source of the n-channel MOS transistor 32 is grounded.

Further, the drain of the p-channel MOS transistor 31 and the n-channel MOS transistor 3
The connection between the drain 2 and the drain 2 is connected to the input terminal of the inverter circuit 33. p-channel type MOS transistor 3
One gate is connected to the output terminal of the inverter circuit 28, which is the output terminal of the inverter delay circuit unit 29. The input terminal of the inverter circuit 21, which is the input terminal of the inverter delay circuit section 29, is connected to the input terminal IN of the delay circuit 20, and the output terminal of the inverter circuit 33 is connected to the output terminal OUT of the delay circuit 20. Is done.

Next, an operation example of the delay circuit 20 having the above configuration will be described. In FIG. 3, a connection portion connecting the output terminal of the inverter circuit 28 and the gate of the p-channel MOS transistor 31 is denoted by C,
A connection portion connecting the drains of the p-channel MOS transistor 31 and the n-channel MOS transistor 32 is denoted by D. FIG. 4 is a timing chart showing an operation example of the delay circuit 20 shown in FIG.

As can be seen from FIG. 4, the pulse input to the input terminal IN of the delay circuit 20 has a waveform delayed at the point C by the inverter delay circuit unit 29 in both the rising and falling of the pulse. When the signal level of the input terminal IN is "L" level, the p-channel MOS transistor 30 is turned on and the n-channel MOS transistor 32 is turned off. In this state, since the point C is at the “L” level, the signal level at the point D is at the “H” level, the logic is inverted by the inverter circuit 33, and the output terminal OUT of the delay circuit 20 is at the “L” level. is there.

Next, when the signal level of the pulse input to the input terminal IN of the delay circuit 20 changes from "L" level to "H" level, the p-channel MOS transistor 3
0 is turned off and the n-channel MOS transistor 32 is turned on. Therefore, regardless of the signal level at the point C, that is, regardless of the operation of the p-channel MOS transistor 31,
The point changes from the “H” level to the “L” level, and accordingly, the output terminal OUT of the delay circuit 20 changes from the “L” level to the “H” level. Thereafter, the point C changes from the “L” level to the “H” level and the p-channel MOS transistor 31 turns off, but the signal level of the point D and the output terminal OUT of the delay circuit 20 does not change.

Next, when the signal level of the pulse input to the input terminal IN of the delay circuit 20 changes from "H" level to "L" level, the p-channel MOS transistor 3
0 turns on and the n-channel MOS transistor 3
2 is turned off, but since the point C is at the "H" level, the p-channel MOS transistor 31 remains off.
Therefore, the signal level at the point D is maintained and does not change from the “L” level, and the signal level at the output terminal OUT of the delay circuit 20 does not change from the “H” level. Next, the above C
When the point changes from the “H” level to the “L” level, the p-channel MOS transistor 31 turns on, the point D changes from the “L” level to the “H” level, and the output terminal OUT of the delay circuit 20 changes to the “H” level. Level from the “L” level. Thus, the delay circuit 20 is connected to the input terminal I
The pulse signal input to N is output from the output terminal OUT with only its falling delayed.

As described above, the delay circuit according to the second embodiment is a delay circuit that delays only the fall of the signal level of the signal input from the input terminal IN.
Without reducing the performance and reliability of the circuit, the number of transistors included in the circuit can be reduced, and the circuit can be simplified.

The first embodiment and the second embodiment
In the above, eight inverter circuits are connected in series to form a delay circuit portion, but the present invention is not limited to this, and any circuit that can delay a signal input from an input terminal for a predetermined time. I just need.

[0037]

The delay circuit according to the first aspect of the present invention comprises three switching units in addition to the delay circuit unit and the inverting circuit unit, and detects only the rising of the signal level of the signal input from the signal input terminal. In a delay circuit for delaying, the number of switching units constituting the circuit can be reduced and the circuit can be simplified without lowering the performance and reliability of the circuit.

According to a second aspect of the present invention, in the delay circuit according to the first aspect, the signal input from the signal input terminal is delayed from the output terminal of the inverting circuit section by delaying only the rising of the signal level for a predetermined time. Therefore, in a delay circuit that delays only the rise of a signal level of a signal input from a signal input terminal, the number of switching units configuring the circuit is reduced without lowering the performance and reliability of the circuit. And the circuit can be simplified.

According to a third aspect of the present invention, in the delay circuit according to the first or second aspect, the first switching unit is a p-channel MOS transistor, and the second switching unit and the third switching unit are n-channel MOS transistors. Since it is a channel type MOS transistor, in a delay circuit that delays only the rise of the signal level of the signal input from the signal input terminal, the performance of the MOS transistor constituting the circuit can be reduced without reducing the performance and reliability of the circuit. The number can be reduced, and the circuit can be simplified.

The delay circuit according to the fourth invention comprises three switching units in addition to the delay circuit unit and the inverting circuit unit, and delays only the fall of the signal level of the signal input from the signal input terminal. In the delay circuit
Without deteriorating the performance and reliability of the circuit, the number of switching units constituting the circuit can be reduced, and the circuit can be simplified.

According to a fifth aspect of the present invention, in the delay circuit according to the fourth aspect, the signal input from the signal input terminal is delayed from the output terminal of the inverting circuit section by delaying only the falling of the signal level for a predetermined time. Therefore, in the delay circuit that delays only the fall of the signal level of the signal input from the signal input terminal, the number of switching units configuring the circuit is reduced without lowering the performance and reliability of the circuit. And the circuit can be simplified.

In a delay circuit according to a sixth aspect of the present invention, in the fourth or fifth aspect, the first switching section and the second switching section are p-channel MOS transistors, and the third switching section is an n-channel MOS transistor. Since it is a channel type MOS transistor, in a delay circuit for delaying only the fall of the signal level of the signal input from the signal input terminal, the MOS transistor forming the circuit without deteriorating the performance and reliability of the circuit Can be reduced, and the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a delay circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation example of the circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a delay circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation example of the circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing an example of a conventional delay circuit.

FIG. 6 is a timing chart showing an operation example of the circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing another example of a conventional delay circuit.

FIG. 8 is a timing chart illustrating an operation example of the circuit illustrated in FIG. 7;

[Explanation of symbols]

1,20 delay circuit, 2-9,14,21-28,3
3 Inverter circuit, 10, 29 Inverter delay circuit section, 11, 30, 31 P-channel type MOS transistor, 12, 13, 32 N-channel type MOS transistor

Claims (6)

[Claims] A signal input terminal to which a signal is externally input; a delay circuit for delaying a signal input to the signal input terminal for a predetermined time and outputting the signal; and a signal input from the signal input terminal A first switching unit for controlling a switching operation, a second switching unit connected in series with the first switching unit, the switching operation of which is controlled by a signal input from the signal input terminal; and the second switching unit. A third switching unit connected in series with the switching unit and having a switching operation controlled by a signal output from the delay circuit unit; and inverting and outputting a signal level at a connection unit between the first switching unit and the second switching unit. The first switching unit and the second switching unit transmit a signal from a signal input terminal. Signal operation, and the first switching unit performs
When the conduction state is established, the input terminal of the inverting circuit section is set to “H” level, and when both the second switching section and the third switching section are conducted, the input terminal of the inverting circuit section is set to “L” level. A delay circuit characterized in that: 2. The delay circuit according to claim 1, wherein the signal input from the signal input terminal is output from the output terminal of the inverting circuit unit after a predetermined time delay only at the rise of the signal level. . 3. The device according to claim 1, wherein the first switching section is a p-channel MOS transistor, and the second switching section and the third switching section are n-channel MOS transistors. 3. The delay circuit according to any one of 2. 4. A signal input terminal to which a signal is input from the outside, a delay circuit for delaying a signal input to the signal input terminal for a predetermined time and outputting the signal, and a signal input from the signal input terminal. A first switching unit for controlling a switching operation, a second switching unit connected in series with the first switching unit, the switching operation of which is controlled by a signal output from the delay circuit unit; and the second switching unit. A third switching unit connected in series with the switching unit and having a switching operation controlled by a signal input from the signal input terminal; and inverting and outputting a signal level at a connection unit between the second switching unit and the third switching unit. The first switching unit and the third switching unit transmit a signal from a signal input terminal. When the first switching unit and the second switching unit are in a conducting state, the input terminal of the inverting circuit unit is set to “H” level, and the third switching unit is A delay circuit wherein the input terminal of the inverting circuit section is set to "L" level when the conductive state is established. 5. The delay according to claim 4, wherein the signal input from the signal input terminal is output from the output terminal of the inverting circuit after being delayed for a predetermined time only at the fall of the signal level. circuit. 6. The first switching unit and the second switching unit are p-channel MOS transistors,
The delay circuit according to claim 4, wherein the third switching unit is an n-channel MOS transistor.