JPH10135369A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Semiconductor integrated circuit device and manufacturing method thereof

Info

Publication number
JPH10135369A
JPH10135369A JP8284771A JP28477196A JPH10135369A JP H10135369 A JPH10135369 A JP H10135369A JP 8284771 A JP8284771 A JP 8284771A JP 28477196 A JP28477196 A JP 28477196A JP H10135369 A JPH10135369 A JP H10135369A
Authority
JP
Japan
Prior art keywords
element mounting
integrated circuit
circuit device
semiconductor integrated
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8284771A
Other languages
Japanese (ja)
Inventor
Fujiaki Nose
藤明 野瀬
Yuji Watanabe
祐二 渡邊
Eiji Yamaguchi
栄次 山口
Taku Kikuchi
卓 菊池
Takashi Miwa
孝志 三輪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8284771A priority Critical patent/JPH10135369A/en
Publication of JPH10135369A publication Critical patent/JPH10135369A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To decrease the rigidity of an element mounting portion of an element mounting board, so as to reduce the stress applied onto a bump connection part of a semiconductor element and improve connection reliability of the bump connection part of the semiconductor element, by forming the element mounting portion of the element mounting board with a thickness smaller than that of a non-element mounting portion. SOLUTION: In an element mounting board 2 for supporting a semiconductor chip 1, an element mounting portion 2a is formed with a thickness smaller than that of a non-element mounting portion 2b. Thus, the rigidity of the element mounting portion 2 in the element mounting board 2 may be decreased. Therefore, when BGA is heated or cooled to cause the element mounting board 2 to expand or contract, the element mounting portion 2a may be deformed in accordance with the degree of deformation of the semiconductor chip 1, since the element mounting portion 2a having a coefficient of thermal expansion greater than that of the semiconductor chip 1 has flexibility. As a result, the stress applied onto a bump connection part 3a may be reduced, and connection reliability of the bump connection part 3a may be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、フリップチップ接続におけるバンプの接続
信頼性を向上させる半導体集積回路装置およびその製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly, to a semiconductor integrated circuit device and a method for manufacturing the same, which improve bump connection reliability in flip chip connection.

【0002】[0002]

【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。
2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

【0003】半導体チップ(半導体素子)を搭載してな
るBGA(Ball Grid Array)などの半導体集積回路装置
の製造方法においては、半導体チップとこれを支持する
素子搭載基板とをはんだバンプ、メッキ形成バンプまた
は導電性有機材料などを介して電気的に接続するフリッ
プチップ接続と呼ばれる技術が用いられている。
[0003] In a method of manufacturing a semiconductor integrated circuit device such as a BGA (Ball Grid Array) having a semiconductor chip (semiconductor element) mounted thereon, a semiconductor chip and an element mounting substrate supporting the semiconductor chip are solder bumps and plated bumps. Alternatively, a technique called flip-chip connection for electrically connecting via a conductive organic material or the like is used.

【0004】なお、素子搭載基板は、比較的剛性が大き
く形成されている場合が多いため、半導体チップと素子
搭載基板間で応力が発生すると、バンプ接続部で電気的
断線を起こす可能性がある。
Since the element mounting board is often formed to have relatively high rigidity, if a stress is generated between the semiconductor chip and the element mounting board, an electrical disconnection may occur at the bump connection portion. .

【0005】したがって、そのバンプ接続部において高
接続信頼性を得るために、半導体チップと素子搭載基板
とによって形成される空隙またはバンプの周囲に液状の
絶縁性樹脂を滴下あるいは注入し、その後、絶縁性樹脂
を硬化させている。
Therefore, in order to obtain high connection reliability at the bump connection portion, a liquid insulating resin is dropped or injected around the gap or the bump formed between the semiconductor chip and the element mounting substrate, and then the insulating material is formed. The hardening resin is cured.

【0006】ここで、フリップチップ接続については、
例えば、日経BP社、1993年5月31日発行、香山
晋、成瀬邦彦(監)、「実践講座VLSIパッケージン
グ技術(下)」、175〜178頁に記載されている。
Here, regarding the flip chip connection,
For example, it is described in Nikkei BP, issued May 31, 1993, Susumu Kayama and Kunihiko Naruse (monitoring), "Practical Course VLSI Packaging Technology (Lower)", pages 175 to 178.

【0007】[0007]

【発明が解決しようとする課題】ところが、前記した技
術におけるフリップチップ接続を行うBGAでは、素子
搭載基板にプリント基板を使用すると、半導体チップと
素子搭載基板との材料による熱膨張係数差が大きいた
め、バンプを介して半導体チップを搭載した後、室温に
戻した(冷却した)際、あるいは実使用状況下でバンプ
接続部に過大な熱応力が発生する。
However, in the BGA for performing flip-chip connection in the above-mentioned technology, when a printed circuit board is used as an element mounting board, a difference in thermal expansion coefficient between the semiconductor chip and the element mounting board due to the material is large. After mounting the semiconductor chip via the bump, when the temperature is returned to room temperature (cooled), or under actual use conditions, excessive thermal stress is generated at the bump connection portion.

【0008】この時、素子搭載基板は半導体チップより
遙かに厚くかつ剛性が大きい場合が多い。
At this time, the element mounting board is often much thicker and more rigid than the semiconductor chip.

【0009】したがって、素子搭載基板の変形が少な
く、バンプ接続部に対して大きな応力が掛かるため、バ
ンプ接続部において断線が起こることが問題とされる。
Therefore, there is a problem that disconnection occurs at the bump connection portion because the deformation of the element mounting substrate is small and a large stress is applied to the bump connection portion.

【0010】さらに、半導体チップと素子搭載基板との
間の空隙またはバンプ接続部を絶縁性樹脂によって補強
した際にも、BGAとして実装基板に搭載すると素子搭
載基板の反りが拘束されるため、BGA搭載時のリフロ
ーによる熱履歴を受けることで接続不良に至ることが問
題とされる。
Further, even when the gap or bump connection between the semiconductor chip and the element mounting board is reinforced with an insulating resin, if the element is mounted on the mounting board as a BGA, the warpage of the element mounting board is restrained. A problem is that connection failure may occur due to heat history due to reflow during mounting.

【0011】本発明の目的は、半導体素子のバンプ接続
部における接続信頼性を向上させる半導体集積回路装置
およびその製造方法を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit device which improves the connection reliability at a bump connection portion of a semiconductor element, and a method of manufacturing the same.

【0012】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【0013】[0013]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【0014】すなわち、本発明の半導体集積回路装置
は、半導体素子を搭載してなるものであり、バンプを介
して前記半導体素子を支持する素子搭載基板を有し、前
記素子搭載基板における素子搭載部が非素子搭載部と比
較して薄く形成されているものである。
That is, a semiconductor integrated circuit device according to the present invention has a semiconductor element mounted thereon, has an element mounting substrate supporting the semiconductor element via bumps, and has an element mounting portion in the element mounting substrate. Are formed thinner than the non-element mounting portion.

【0015】これにより、素子搭載基板において素子搭
載部が非素子搭載部と比較して薄く形成されていること
により、素子搭載基板の素子搭載部の剛性を小さくする
ことができる。
Accordingly, the rigidity of the element mounting portion of the element mounting substrate can be reduced because the element mounting portion is formed thinner than the non-element mounting portion in the element mounting substrate.

【0016】したがって、素子搭載基板の素子搭載部が
柔軟性を有するため、半導体集積回路装置が加熱あるい
は冷却された際に、半導体素子の変形の度合いに応じて
素子搭載基板の素子搭載部が変形することができる。
Therefore, since the element mounting portion of the element mounting substrate has flexibility, when the semiconductor integrated circuit device is heated or cooled, the element mounting portion of the element mounting substrate is deformed in accordance with the degree of deformation of the semiconductor element. can do.

【0017】その結果、半導体素子のバンプ接続部に掛
かる応力を低減することができ、半導体素子のバンプ接
続部の接続信頼性を向上させることができる。
As a result, the stress applied to the bump connection of the semiconductor element can be reduced, and the connection reliability of the bump connection of the semiconductor element can be improved.

【0018】さらに、本発明の半導体集積回路装置は、
前記素子搭載基板の素子搭載面とその反対側の非素子搭
載面との両面に凹部が形成されて前記素子搭載部が薄く
形成されているものである。
Furthermore, the semiconductor integrated circuit device of the present invention
Concave portions are formed on both sides of the element mounting surface of the element mounting substrate and the non-element mounting surface on the opposite side, and the element mounting portion is formed thin.

【0019】また、本発明の半導体集積回路装置の製造
方法は、半導体素子を支持するとともに素子搭載部が非
素子搭載部と比較して薄く形成された素子搭載基板を準
備する工程、バンプを介して前記半導体素子を前記素子
搭載基板の素子搭載部に搭載する工程を含むものであ
る。
Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, there is provided a step of preparing an element mounting substrate which supports a semiconductor element and has an element mounting portion formed thinner than a non-element mounting portion, via a bump. Mounting the semiconductor element on an element mounting portion of the element mounting board.

【0020】[0020]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0021】図1は本発明の半導体集積回路装置である
BGAの構造の実施の形態の一例を示す断面図、図2は
本発明の半導体集積回路装置であるBGAの素子搭載基
板の構造の実施の形態の一例を示す底面図、図3は本発
明の半導体集積回路装置であるBGAにおける素子搭載
基板の変形時の構造の実施の形態の一例を示す断面図で
ある。
FIG. 1 is a cross-sectional view showing an embodiment of the structure of a BGA which is a semiconductor integrated circuit device of the present invention. FIG. 2 is an embodiment of a structure of an element mounting board of a BGA which is a semiconductor integrated circuit device of the present invention. FIG. 3 is a cross-sectional view showing an example of an embodiment of the structure of the BGA which is a semiconductor integrated circuit device according to the present invention when the element mounting substrate is deformed.

【0022】本実施の形態の半導体集積回路装置は、半
導体チップ(半導体素子)1が素子搭載基板2にフリッ
プチップ接続されるものである。
In the semiconductor integrated circuit device of the present embodiment, a semiconductor chip (semiconductor element) 1 is flip-chip connected to an element mounting substrate 2.

【0023】つまり、半導体チップ1がボール状の電極
すなわちバンプ3を介して素子搭載基板2に搭載されて
いる。
That is, the semiconductor chip 1 is mounted on the element mounting substrate 2 via the ball-shaped electrodes, that is, the bumps 3.

【0024】なお、本実施の形態においては、前記半導
体集積回路装置の一例としてBGAを取り上げて説明す
る。
In this embodiment, a BGA will be described as an example of the semiconductor integrated circuit device.

【0025】前記BGAの構成は、半導体集積回路が形
成された半導体チップ1と、バンプ3を介して半導体チ
ップ1を支持する素子搭載基板2(ベース基板もしくは
パッケージ基板ともいう)とからなり、素子搭載基板2
における素子搭載部2aがその周囲の非素子搭載部2b
と比較して薄く形成されている。
The structure of the BGA includes a semiconductor chip 1 on which a semiconductor integrated circuit is formed, and an element mounting substrate 2 (also referred to as a base substrate or a package substrate) that supports the semiconductor chip 1 via bumps 3. Mounting board 2
Of the element mounting portion 2a in the area
It is formed thinner than.

【0026】さらに、本実施の形態のBGAは、図1に
示すように、素子搭載基板2の素子搭載面2cに対する
その反対側の非素子搭載面2dに凹部2eが形成されて
素子搭載部2aが薄く形成されている。
Further, as shown in FIG. 1, in the BGA of the present embodiment, a concave portion 2e is formed in a non-element mounting surface 2d opposite to the element mounting surface 2c of the element mounting substrate 2 so that the element mounting portion 2a Are formed thinly.

【0027】また、半導体チップ1は、その熱膨張係数
が、例えば、約3.5×10-6/℃であり、そのバンプ接
続面1aの外周部には、バンプ3を接続する複数の電極
パッドが格子状に設けられている。
The semiconductor chip 1 has a thermal expansion coefficient of, for example, about 3.5 × 10 −6 / ° C., and a plurality of electrodes for connecting the bumps 3 are provided on the outer periphery of the bump connection surface 1a. Pads are provided in a grid pattern.

【0028】さらに、バンプ3は、例えば、Sn−3w
t%Agのはんだによって形成されている。
Further, the bump 3 is made of, for example, Sn-3w.
It is formed by solder of t% Ag.

【0029】ここで、本実施の形態における素子搭載基
板2は、例えば、ガラスエポキシ系の樹脂によって形成
されており、その熱膨張係数は、約15×10-6/℃で
ある。さらに、図2に示すように、素子搭載基板2の平
面形状は、四角形を成している。
Here, the element mounting substrate 2 in the present embodiment is formed of, for example, a glass epoxy resin, and has a coefficient of thermal expansion of about 15 × 10 −6 / ° C. Further, as shown in FIG. 2, the planar shape of the element mounting board 2 is a quadrangle.

【0030】また、素子搭載基板2における半導体チッ
プ1直下のマウントエリアすなわち素子搭載部2aだけ
がその周囲の非素子搭載部2bに比べて薄く形成されて
いる。
Further, only the mount area immediately below the semiconductor chip 1 on the element mounting board 2, that is, only the element mounting portion 2a is formed thinner than the surrounding non-element mounting portion 2b.

【0031】つまり、本実施の形態においては、素子搭
載基板2の素子搭載面2cのほぼ中央部に半導体チップ
1が搭載されるため、図2に示すように、素子搭載基板
2の非素子搭載面2dのほぼ中央部に半導体チップ1
(図1参照)とほぼ同じ面積を有する凹部2eが形成さ
れ、かつその周囲には複数個の端子電極2fが設けられ
ている。
That is, in this embodiment, since the semiconductor chip 1 is mounted substantially at the center of the element mounting surface 2c of the element mounting substrate 2, the non-element mounting of the element mounting substrate 2 is performed as shown in FIG. The semiconductor chip 1 is located substantially at the center of the surface 2d.
A concave portion 2e having substantially the same area as that of FIG. 1 is formed, and a plurality of terminal electrodes 2f are provided around the concave portion 2e.

【0032】ここで、素子搭載基板2における素子搭載
部2aの厚さは、例えば、0.1〜0.2mm、その周囲の
非素子搭載部2bの厚さは、0.6〜1mmである。
Here, the thickness of the element mounting portion 2a of the element mounting substrate 2 is, for example, 0.1 to 0.2 mm, and the thickness of the non-element mounting portion 2b around the element mounting portion 2a is 0.6 to 1 mm. .

【0033】本実施の形態の半導体集積回路装置の製造
方法について説明する。
A method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be described.

【0034】なお、前記半導体集積回路装置の製造方法
は前記BGAの製造方法である。
The method for manufacturing the semiconductor integrated circuit device is the method for manufacturing the BGA.

【0035】まず、半導体チップ1を支持するとともに
素子搭載部2aが非素子搭載部2bと比較して薄く形成
された素子搭載基板2を準備する。
First, an element mounting board 2 supporting the semiconductor chip 1 and having the element mounting portion 2a formed thinner than the non-element mounting portion 2b is prepared.

【0036】ここで、本実施の形態による素子搭載基板
2は、素子搭載基板2の非素子搭載面2dに凹部2eが
形成されて素子搭載部2aが薄く形成され、かつ、ガラ
スエポキシ系の樹脂によって形成された多層(1層であ
ってもよい)のものであり、一般に使用されている多層
のプリント配線基板と同様の製造方法、例えば、貼り合
わせ技術などによって形成される。
Here, the element mounting substrate 2 according to the present embodiment has a concave portion 2e formed on the non-element mounting surface 2d of the element mounting substrate 2, the element mounting portion 2a is formed thin, and a glass epoxy resin is used. (May be a single layer) formed by the same manufacturing method as a generally used multilayer printed wiring board, for example, a bonding technique.

【0037】すなわち、各層ごとの基板において、所望
の配線パターンを形成し、それぞれの基板を積層した
後、スルーホール加工によって層間の電気的接続を行
う。
That is, a desired wiring pattern is formed on a substrate for each layer, and after laminating the substrates, electrical connection between layers is performed by through-hole processing.

【0038】なお、本実施の形態の素子搭載基板2の場
合、凹部2eの形成は、凹部2eに相当する所定の大き
さの領域が四角形(円形などでもよい)に開口した複数
の基板と、開口していない複数の基板とを貼り合わせる
ことによって行われる。
In the case of the element mounting substrate 2 of the present embodiment, the concave portion 2e is formed by forming a plurality of substrates each having an area of a predetermined size corresponding to the concave portion 2e and opening in a square (or a circular shape). This is performed by bonding a plurality of substrates that are not open.

【0039】これにより、素子搭載基板2の非素子搭載
面2dに凹部2eが形成されて素子搭載部2aが薄く形
成された素子搭載基板2を準備できる。
As a result, the element mounting substrate 2 in which the recess 2e is formed in the non-element mounting surface 2d of the element mounting substrate 2 and the element mounting portion 2a is formed thinly can be prepared.

【0040】その後、半導体チップ1のバンプ接続面1
aに格子状に設けられた電極パッドにはんだからなるバ
ンプ3をフラックスによって仮付けする。
Thereafter, the bump connection surface 1 of the semiconductor chip 1
The bumps 3 made of solder are temporarily attached to the electrode pads provided in a lattice pattern by a flux.

【0041】続いて、例えば、前記はんだの融点を越え
る240℃の炉体でリフローすることにより、半導体チ
ップ1にバンプ3を固定する。
Subsequently, the bumps 3 are fixed to the semiconductor chip 1 by, for example, reflowing in a furnace at 240 ° C. exceeding the melting point of the solder.

【0042】その後、バンプ3を介して半導体チップ1
を素子搭載基板2の素子搭載部2aに搭載する。
After that, the semiconductor chip 1 is
Is mounted on the element mounting portion 2a of the element mounting substrate 2.

【0043】すなわち、素子搭載基板2の素子搭載部2
aにフラックスを塗布した後、半導体チップ1をバンプ
3が下向きになる方向で素子搭載基板2に設置された対
応する電極と位置が合うように素子搭載基板2の素子搭
載部2aにおける素子搭載面2cに載せる。
That is, the element mounting portion 2 of the element mounting substrate 2
After the flux is applied to the element mounting surface 2a, the semiconductor chip 1 is placed on the element mounting surface 2a of the element mounting substrate 2 so that the bumps 3 face down and the corresponding electrodes placed on the element mounting substrate 2 are aligned. Place on 2c.

【0044】その後、再び240℃の炉体でリフローす
ることにより、半導体チップ1と素子搭載基板2とをバ
ンプ3によって接続する。
Thereafter, the semiconductor chip 1 and the element mounting substrate 2 are connected by bumps 3 by reflowing again in a furnace at 240 ° C.

【0045】これにより、素子搭載基板2において薄く
形成された素子搭載部2aに半導体チップ1を搭載でき
る。
As a result, the semiconductor chip 1 can be mounted on the element mounting portion 2a formed thin on the element mounting substrate 2.

【0046】その結果、半導体チップ1と素子搭載基板
2とがバンプ3を介して電気的に接続されたBGAを製
造できる。
As a result, a BGA in which the semiconductor chip 1 and the element mounting substrate 2 are electrically connected via the bumps 3 can be manufactured.

【0047】続いて、BGA実装用バンプ4を素子搭載
基板2に設けられた端子電極2fに取り付け、このBG
A実装用バンプ4を介してBGAを実装基板5に実装す
る。
Subsequently, the BGA mounting bumps 4 are attached to the terminal electrodes 2f provided on the element mounting board 2, and the BG
The BGA is mounted on the mounting substrate 5 via the A mounting bumps 4.

【0048】この時、リフローなどによってBGAを実
装基板5に実装するが、前記リフローの際に、半導体チ
ップ1が変形する(反る)。
At this time, the BGA is mounted on the mounting board 5 by reflow or the like, but the semiconductor chip 1 is deformed (warped) during the reflow.

【0049】しかし、図3に示すように、半導体チップ
1の変形の度合いに応じて素子搭載基板2も変形する
(反る)。
However, as shown in FIG. 3, the element mounting board 2 is also deformed (warped) according to the degree of deformation of the semiconductor chip 1.

【0050】これにより、半導体チップ1と素子搭載基
板2とのバンプ接続部3aにかかる応力を低減できる。
Thus, the stress applied to the bump connection portion 3a between the semiconductor chip 1 and the element mounting board 2 can be reduced.

【0051】本実施の形態の半導体集積回路装置および
その製造方法によれば、以下のような作用効果が得られ
る。
According to the semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment, the following operational effects can be obtained.

【0052】すなわち、半導体チップ1を支持する素子
搭載基板2において素子搭載部2aが非素子搭載部2b
と比較して薄く形成されていることにより、素子搭載基
板2における素子搭載部2aの剛性を小さくすることが
できる。
That is, in the element mounting substrate 2 supporting the semiconductor chip 1, the element mounting portion 2a is replaced with the non-element mounting portion 2b.
The rigidity of the element mounting portion 2a in the element mounting substrate 2 can be reduced by being formed thinner than that.

【0053】これにより、BGAが加熱あるいは冷却さ
れ、その結果、素子搭載基板2が膨張または収縮しよう
とする際に、半導体チップ1より熱膨張係数が大きな素
子搭載基板2の素子搭載部2aが柔軟性を有しているた
め、半導体チップ1の変形の度合いに応じて素子搭載基
板2の素子搭載部2aが変形することができる。
As a result, the BGA is heated or cooled. As a result, when the element mounting substrate 2 is about to expand or contract, the element mounting portion 2a of the element mounting substrate 2 having a larger thermal expansion coefficient than the semiconductor chip 1 is flexible. Therefore, the element mounting portion 2a of the element mounting substrate 2 can be deformed according to the degree of deformation of the semiconductor chip 1.

【0054】ここで、前記加熱とは、例えば、リフロー
時の加熱などであり、また、前記冷却とは、加熱後に室
温に戻す際の冷却などである。
Here, the heating is, for example, heating during reflow, and the cooling is, for example, cooling when returning to room temperature after heating.

【0055】その結果、半導体チップ1の変形の度合い
に応じて素子搭載部2aが変形するため、半導体チップ
1のバンプ接続部3aに掛かる応力を低減することがで
き、半導体チップ1のバンプ接続部3aの接続信頼性を
向上させることができる。
As a result, the element mounting portion 2a is deformed according to the degree of deformation of the semiconductor chip 1, so that the stress applied to the bump connection portion 3a of the semiconductor chip 1 can be reduced, and the bump connection portion of the semiconductor chip 1 can be reduced. 3a can be improved in connection reliability.

【0056】したがって、実装基板5への実装の際のリ
フロー時に発生する接続不良も低減することができる。
Therefore, it is possible to reduce connection failures that occur at the time of reflow during mounting on the mounting board 5.

【0057】なお、素子搭載基板2において半導体チッ
プ1直下のマウントエリアすなわち素子搭載部2aだけ
を薄く形成することにより、素子搭載基板2の多層化に
も対応することが可能になる。
It is to be noted that by forming the mount area immediately below the semiconductor chip 1 on the element mounting substrate 2, that is, only the element mounting portion 2 a, to be thin, it is possible to cope with the multilayer mounting of the element mounting substrate 2.

【0058】また、素子搭載基板2における素子搭載部
2aが薄く形成されていることにより、半導体チップ1
のバンプ接続部3aの接続信頼性を向上させることがで
きるため、半導体チップ1と素子搭載基板2との間の空
隙またはバンプ接続部3aを絶縁性樹脂によって補強す
る必要がなくなる。
Also, since the element mounting portion 2a of the element mounting substrate 2 is formed thin, the semiconductor chip 1
Since the connection reliability of the bump connection portion 3a can be improved, there is no need to reinforce the gap between the semiconductor chip 1 and the element mounting substrate 2 or the bump connection portion 3a with an insulating resin.

【0059】これにより、フリップチップ接続を行うB
GAの製造工程において、樹脂封止工程を削除すること
ができ、その結果、前記BGAの製造性を向上させるこ
とができる。
Thus, flip-chip connection B is performed.
In the manufacturing process of the GA, the resin sealing process can be omitted, and as a result, the productivity of the BGA can be improved.

【0060】なお、素子搭載基板2がガラスエポキシ系
の樹脂によって形成されていることにより、半導体チッ
プ1と素子搭載基板2との熱膨張係数の差が大きいた
め、この場合には、バンプ接続部3aの接続信頼性およ
び前記BGAの製造性をさらに向上させることができ
る。
Since the element mounting substrate 2 is formed of a glass epoxy resin, the difference in the coefficient of thermal expansion between the semiconductor chip 1 and the element mounting substrate 2 is large. The connection reliability of 3a and the manufacturability of the BGA can be further improved.

【0061】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。
As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

【0062】例えば、前記実施の形態で説明した半導体
集積回路装置(BGA)は、素子搭載基板の素子搭載面
と反対側の非素子搭載面に凹部が形成されて前記素子搭
載部が薄く形成されている場合であったが、前記半導体
集積回路装置は、図4に示す他の実施の形態の半導体集
積回路装置(BGA)のように、素子搭載基板2の素子
搭載面2cに凹部2eが形成されて素子搭載部2aが薄
く形成されていてもよい。
For example, in the semiconductor integrated circuit device (BGA) described in the above embodiment, a concave portion is formed on the non-element mounting surface of the element mounting substrate opposite to the element mounting surface, and the element mounting portion is formed thin. However, in the semiconductor integrated circuit device, the recess 2e is formed in the element mounting surface 2c of the element mounting substrate 2 like the semiconductor integrated circuit device (BGA) of another embodiment shown in FIG. Thus, the element mounting portion 2a may be formed thin.

【0063】この場合、素子搭載基板2の凹部2eに半
導体チップ1が収容かつ搭載された構造になる。
In this case, the semiconductor chip 1 is housed and mounted in the concave portion 2e of the element mounting board 2.

【0064】これにより、前記実施の形態のBGAと同
様に半導体チップ1のバンプ接続部3aの接続信頼性を
向上させることができるとともに、半導体集積回路装置
(BGA)の高さを低くすることができ、その結果、B
GAの薄形化を実現できる。
Thus, the connection reliability of the bump connection portion 3a of the semiconductor chip 1 can be improved as in the case of the BGA of the above-described embodiment, and the height of the semiconductor integrated circuit device (BGA) can be reduced. And as a result, B
The thickness of the GA can be reduced.

【0065】また、前記半導体集積回路装置は、図5に
示す他の実施の形態の半導体集積回路装置(BGA)の
ように、素子搭載基板2の素子搭載面2cとその反対側
の非素子搭載面2dとの両面に凹部2eが形成されて素
子搭載部2aが薄く形成されていてもよい。
The semiconductor integrated circuit device is similar to the semiconductor integrated circuit device (BGA) of another embodiment shown in FIG. 5 in that the device mounting surface 2c of the device mounting substrate 2 and the non- A concave portion 2e may be formed on both sides of the surface 2d, and the element mounting portion 2a may be formed thin.

【0066】この場合においても、図4に示したBGA
と同様に、素子搭載基板2の凹部2eに半導体チップ1
が収容かつ搭載された構造になる。
In this case also, the BGA shown in FIG.
In the same manner as described above, the semiconductor chip 1
Is housed and mounted.

【0067】なお、素子搭載基板2の素子搭載面2cと
非素子搭載面2dとの両面に凹部2eを形成したことに
より、素子搭載基板2の素子搭載部2aをさらに薄く形
成できるため、素子搭載部2aが有する柔軟性を大きく
することができ、これにより、半導体チップ1のバンプ
接続部3aの接続信頼性をさらに向上させることができ
る。
Since the concave portions 2e are formed on both sides of the element mounting surface 2c and the non-element mounting surface 2d of the element mounting substrate 2, the element mounting portion 2a of the element mounting substrate 2 can be formed thinner. The flexibility of the portion 2a can be increased, whereby the connection reliability of the bump connection portion 3a of the semiconductor chip 1 can be further improved.

【0068】さらに、図4に示したBGAと同様に、半
導体集積回路装置(BGA)の高さを低くすることがで
きるため、BGAの薄形化を実現できる。
Further, similarly to the BGA shown in FIG. 4, the height of the semiconductor integrated circuit device (BGA) can be reduced, so that the BGA can be made thinner.

【0069】ここで、図4および図5に示す半導体集積
回路装置(BGA)の製造方法は、前記実施の形態のB
GAの製造方法と同様であることは言うまでもない。
Here, the method of manufacturing the semiconductor integrated circuit device (BGA) shown in FIG. 4 and FIG.
Needless to say, this is the same as the method of manufacturing the GA.

【0070】なお、図4および図5に示す半導体集積回
路装置(BGA)によって得られるその他の作用効果に
ついては、前記実施の形態のBGAによって得られる作
用効果と同様であるため、その重複説明は省略する。
The other functions and effects obtained by the semiconductor integrated circuit device (BGA) shown in FIGS. 4 and 5 are the same as the functions and effects obtained by the BGA of the above-described embodiment. Omitted.

【0071】また、前記実施の形態および前記他の実施
の形態においては、半導体集積回路装置がBGAの場合
について説明したが、前記半導体集積回路装置は、半導
体チップを支持する素子搭載基板を有し、かつ前記半導
体チップをフリップチップ接続するものであれば、BG
A以外のPGA(Pin Grid Array) などの他の半導体集
積回路装置であってもよい。
In the above-described embodiment and the other embodiments, the case where the semiconductor integrated circuit device is a BGA has been described. However, the semiconductor integrated circuit device has an element mounting substrate for supporting a semiconductor chip. And if the semiconductor chip is flip-chip connected, BG
Other semiconductor integrated circuit devices such as PGA (Pin Grid Array) other than A may be used.

【0072】さらに、前記実施の形態および前記他の実
施の形態のBGAにおいては、半導体チップと素子搭載
基板との間の空隙およびバンプ接続部を樹脂封止しない
場合について説明したが、前記空隙、前記半導体チップ
あるいは前記バンプ接続部を樹脂封止してもよく、ま
た、キャップなどを用いて封止してもよい。
Further, in the BGA of the above-described embodiment and the other embodiments, the case where the gap between the semiconductor chip and the element mounting substrate and the bump connection portion are not sealed with resin has been described. The semiconductor chip or the bump connection portion may be sealed with a resin, or may be sealed with a cap or the like.

【0073】なお、前記実施の形態および前記他の実施
の形態のBGAにおいては、素子搭載基板がガラスエポ
キシ系の樹脂によって形成されている場合について説明
したが、前記素子搭載基板は、セラミックなどの他の材
料によって形成されていてもよい。
In the BGA of the above embodiment and the other embodiments, the case where the element mounting substrate is formed of a glass epoxy resin has been described, but the element mounting substrate is made of ceramic or the like. It may be formed of another material.

【0074】[0074]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。
Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【0075】(1).半導体素子を支持する素子搭載基
板における素子搭載部が非素子搭載部と比較して薄く形
成されていることにより、素子搭載基板の素子搭載部の
剛性を小さくすることができる。これにより、半導体素
子のバンプ接続部に掛かる応力を低減することができ、
半導体素子のバンプ接続部の接続信頼性を向上させるこ
とができる。
(1). Since the element mounting portion of the element mounting substrate supporting the semiconductor element is formed thinner than the non-element mounting portion, the rigidity of the element mounting portion of the element mounting substrate can be reduced. Thereby, the stress applied to the bump connection portion of the semiconductor element can be reduced,
The connection reliability of the bump connection part of the semiconductor element can be improved.

【0076】(2).半導体素子のバンプ接続部の接続
信頼性を向上させることができるため、実装基板への実
装の際のリフロー時に発生する接続不良も低減すること
ができる。
(2). Since the connection reliability of the bump connection portion of the semiconductor element can be improved, connection failures that occur at the time of reflow during mounting on the mounting board can be reduced.

【0077】(3).素子搭載基板における素子搭載部
が薄く形成されていることにより、半導体素子と素子搭
載基板との間の空隙またはバンプ接続部を絶縁性樹脂に
よって補強する必要がなくなる。これにより、フリップ
チップ接続を行う半導体集積回路装置の製造工程におい
て、樹脂封止工程を削除することができ、その結果、前
記半導体集積回路装置の製造性を向上させることができ
る。
(3). Since the element mounting portion of the element mounting substrate is formed to be thin, it is not necessary to reinforce a gap or a bump connection portion between the semiconductor element and the element mounting substrate with an insulating resin. This makes it possible to omit the resin sealing step in the manufacturing process of the semiconductor integrated circuit device performing the flip-chip connection, thereby improving the manufacturability of the semiconductor integrated circuit device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体集積回路装置であるBGAの構
造の実施の形態の一例を示す断面図である。
FIG. 1 is a sectional view showing an example of an embodiment of a structure of a BGA which is a semiconductor integrated circuit device of the present invention.

【図2】本発明の半導体集積回路装置であるBGAの素
子搭載基板の構造の実施の形態の一例を示す底面図であ
る。
FIG. 2 is a bottom view showing an example of an embodiment of the structure of an element mounting substrate of a BGA which is a semiconductor integrated circuit device of the present invention.

【図3】本発明の半導体集積回路装置であるBGAにお
ける素子搭載基板の変形時の構造の実施の形態の一例を
示す断面図である。
FIG. 3 is a cross-sectional view showing an example of an embodiment of a structure when a device mounting substrate in a BGA as a semiconductor integrated circuit device of the present invention is deformed.

【図4】本発明の他の実施の形態である半導体集積回路
装置(BGA)の構造を示す断面図である。
FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor integrated circuit device (BGA) according to another embodiment of the present invention.

【図5】本発明の他の実施の形態である半導体集積回路
装置(BGA)の構造を示す断面図である。
FIG. 5 is a cross-sectional view showing a structure of a semiconductor integrated circuit device (BGA) according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ(半導体素子) 1a バンプ接続面 2 素子搭載基板 2a 素子搭載部 2b 非素子搭載部 2c 素子搭載面 2d 非素子搭載面 2e 凹部 2f 端子電極 3 バンプ 3a バンプ接続部 4 BGA実装用バンプ 5 実装基板 REFERENCE SIGNS LIST 1 semiconductor chip (semiconductor element) 1a bump connection surface 2 element mounting substrate 2a element mounting portion 2b non-element mounting portion 2c element mounting surface 2d non-element mounting surface 2e recess 2f terminal electrode 3 bump 3a bump connection portion 4 BGA mounting bump 5 Mounting board

───────────────────────────────────────────────────── フロントページの続き (72)発明者 菊池 卓 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 三輪 孝志 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Taku Kikuchi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Takashi Miwa 2326 Imai, Ome-shi, Tokyo Device Development Center, Hitachi, Ltd. Inside

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載してなる半導体集積回
路装置であって、バンプを介して前記半導体素子を支持
する素子搭載基板を有し、前記素子搭載基板における素
子搭載部が非素子搭載部と比較して薄く形成されている
ことを特徴とする半導体集積回路装置。
1. A semiconductor integrated circuit device having a semiconductor element mounted thereon, comprising: an element mounting board supporting the semiconductor element via bumps, wherein the element mounting portion of the element mounting board is a non-element mounting section. A semiconductor integrated circuit device characterized in that the semiconductor integrated circuit device is formed to be thinner than a semiconductor integrated circuit device.
【請求項2】 請求項1記載の半導体集積回路装置であ
って、前記素子搭載基板の素子搭載面に凹部が形成され
て前記素子搭載部が薄く形成されていることを特徴とす
る半導体集積回路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein a concave portion is formed on an element mounting surface of said element mounting substrate, and said element mounting portion is formed to be thin. apparatus.
【請求項3】 請求項1記載の半導体集積回路装置であ
って、前記素子搭載基板の素子搭載面と反対側の非素子
搭載面に凹部が形成されて前記素子搭載部が薄く形成さ
れていることを特徴とする半導体集積回路装置。
3. The semiconductor integrated circuit device according to claim 1, wherein a concave portion is formed on a non-element mounting surface of the element mounting substrate opposite to the element mounting surface, and the element mounting portion is formed thin. A semiconductor integrated circuit device characterized by the above-mentioned.
【請求項4】 請求項1記載の半導体集積回路装置であ
って、前記素子搭載基板の素子搭載面とその反対側の非
素子搭載面との両面に凹部が形成されて前記素子搭載部
が薄く形成されていることを特徴とする半導体集積回路
装置。
4. The semiconductor integrated circuit device according to claim 1, wherein concave portions are formed on both sides of an element mounting surface of the element mounting substrate and a non-element mounting surface opposite thereto, so that the element mounting portion is thin. A semiconductor integrated circuit device characterized by being formed.
【請求項5】 請求項1,2,3または4記載の半導体
集積回路装置であって、前記素子搭載基板が樹脂によっ
て形成されていることを特徴とする半導体集積回路装
置。
5. The semiconductor integrated circuit device according to claim 1, wherein the element mounting substrate is formed of a resin.
【請求項6】 請求項1,2,3,4または5記載の半
導体集積回路装置の製造方法であって、 半導体素子を支持するとともに素子搭載部が非素子搭載
部と比較して薄く形成された素子搭載基板を準備する工
程、 バンプを介して前記半導体素子を前記素子搭載基板の素
子搭載部に搭載する工程、 を含むことを特徴とする半導体集積回路装置の製造方
法。
6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor device is supported and the device mounting portion is formed thinner than the non-device mounting portion. Preparing a device mounting substrate, and mounting the semiconductor device on a device mounting portion of the device mounting substrate via a bump.
JP8284771A 1996-10-28 1996-10-28 Semiconductor integrated circuit device and manufacturing method thereof Pending JPH10135369A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8284771A JPH10135369A (en) 1996-10-28 1996-10-28 Semiconductor integrated circuit device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8284771A JPH10135369A (en) 1996-10-28 1996-10-28 Semiconductor integrated circuit device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH10135369A true JPH10135369A (en) 1998-05-22

Family

ID=17682809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8284771A Pending JPH10135369A (en) 1996-10-28 1996-10-28 Semiconductor integrated circuit device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH10135369A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179559A (en) * 2004-12-21 2006-07-06 Nippon Inter Electronics Corp Schottky barrier diode and semiconductor device equipped therewith
US7365426B2 (en) 2001-03-08 2008-04-29 Renesas Technology Corp. Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7365426B2 (en) 2001-03-08 2008-04-29 Renesas Technology Corp. Semiconductor device
JP2006179559A (en) * 2004-12-21 2006-07-06 Nippon Inter Electronics Corp Schottky barrier diode and semiconductor device equipped therewith

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