JPH09321001A - Method for polishing semiconductor wafer - Google Patents
Method for polishing semiconductor waferInfo
- Publication number
- JPH09321001A JPH09321001A JP17534696A JP17534696A JPH09321001A JP H09321001 A JPH09321001 A JP H09321001A JP 17534696 A JP17534696 A JP 17534696A JP 17534696 A JP17534696 A JP 17534696A JP H09321001 A JPH09321001 A JP H09321001A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- polishing
- template
- thickness
- polished
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005498 polishing Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004744 fabric Substances 0.000 claims abstract description 17
- 229920002379 silicone rubber Polymers 0.000 claims abstract description 9
- 239000004945 silicone rubber Substances 0.000 claims abstract description 9
- 238000007517 polishing process Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 43
- 239000000919 ceramic Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 229920001973 fluoroelastomer Polymers 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/27—Work carriers
- B24B37/30—Work carriers for single side lapping of plane surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、半導体ウェハをテンプ
レートにより保持して研磨する半導体ウェハの研磨方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer polishing method for holding and polishing a semiconductor wafer with a template.
【０００２】[0002]
【従来の技術】作業効率の向上と環境汚染対策を目的と
して、近年ワックスを使用しないワックスレス研磨、特
にテンプレートにより半導体ウェハを保持して研磨する
研磨方法により半導体ウェハを製造する工程が増加して
いる。このテンプレートを使用した研磨方法は、図５に
示すように半導体ウェハ１０をテンプレート１ａで保持
し、定盤４に固着された研磨クロス５に当接させて研磨
するものであり、このテンプレート１ａは研磨における
取代を考慮して、半導体ウェハ１０が十分に研磨される
ように、半導体ウェハ１０より約１００μｍ以上薄いテ
ンプレート１ａを使用して研磨している。2. Description of the Related Art In recent years, for the purpose of improving work efficiency and preventing environmental pollution, the number of processes for manufacturing semiconductor wafers has been increased by waxless polishing which does not use wax, particularly by a polishing method in which a semiconductor wafer is held and polished by a template. There is. In the polishing method using this template, as shown in FIG. 5, the semiconductor wafer 10 is held by the template 1a and brought into contact with the polishing cloth 5 fixed to the surface plate 4 to polish the template. In consideration of the allowance in polishing, the template 1a thinner than the semiconductor wafer 10 by about 100 μm or more is used for polishing so that the semiconductor wafer 10 is sufficiently polished.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、近年ラ
ッピングまたは平面研削技術の向上により平坦度の高い
半導体ウェハを研磨しているにもかかわらず、上記した
従来の研磨方法では図４に示すようにその研磨面１１ｂ
にうねり１２ｂが発生する上に、外周部が切り立った状
態となり、ＴＴＶが悪化するという問題点があった。本
発明は、上記問題に鑑みてなされたもので、研磨する前
の形状を損なうことなく、平坦度の高い半導体ウェハに
研磨することができる半導体ウェハの研磨方法を提供す
ることを目的とするものである。However, even though semiconductor wafers having a high degree of flatness have been polished in recent years due to the improvement of lapping or surface grinding techniques, the conventional polishing method described above has a problem as shown in FIG. Polished surface 11b
There is a problem that the swell 12b is generated and the outer peripheral portion is raised, which deteriorates TTV. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor wafer polishing method capable of polishing a semiconductor wafer having high flatness without damaging the shape before polishing. Is.
【０００４】[0004]
【課題を解決するための手段】このため本発明では、半
導体ウェハをテンプレートで保持し、定盤に固着された
研磨クロスに当接させて研磨する半導体ウェハの研磨方
法において、前記定盤と前記研磨クロスの間に弾力性を
有するシートを介在させて研磨するようにしたものであ
る。Therefore, according to the present invention, there is provided a semiconductor wafer polishing method in which a semiconductor wafer is held by a template and brought into contact with a polishing cloth fixed to the surface plate to polish the surface of the semiconductor plate. An elastic sheet is interposed between polishing cloths for polishing.
【０００５】[0005]
【発明の実施の形態】定盤と研磨クロスの間に弾力性を
有するシート、例えばシリコーン等のゴムシートを介在
させて研磨面に発生していたうねりを防止すると共に、
研磨する半導体ウェハと略同じ厚さのテンプレートによ
りこの半導体ウェハを保持し、これにより半導体ウェハ
表面にかかる研磨荷重を均一にするものである。これに
より、前工程で得られた半導体ウェハの形状を損なうこ
となく研磨できる。特に、ラッピングまたは平面研削な
どにより得られた平坦度の高いウェハを研磨することに
より高品質の半導体ウェハを製造することができる。BEST MODE FOR CARRYING OUT THE INVENTION An elastic sheet, for example, a rubber sheet made of silicone or the like is interposed between a surface plate and a polishing cloth to prevent undulation generated on a polishing surface.
This semiconductor wafer is held by a template having substantially the same thickness as that of the semiconductor wafer to be polished, whereby the polishing load applied to the surface of the semiconductor wafer is made uniform. This makes it possible to polish the semiconductor wafer obtained in the previous step without damaging the shape. In particular, a high-quality semiconductor wafer can be manufactured by polishing a wafer having high flatness obtained by lapping or surface grinding.
【０００６】[0006]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１は本発明に係る研磨方法を示す模式図、図２
は本発明の研磨方法により研磨された半導体ウェハの側
断面図、図３は研磨前の半導体ウェハの形状を示す側断
面図、図４は従来技術の研磨方法により研磨された半導
体ウェハの形状を示す側断面図、図５は従来技術の研磨
方法を示す模式図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing a polishing method according to the present invention, FIG.
Is a side sectional view of the semiconductor wafer polished by the polishing method of the present invention, FIG. 3 is a side sectional view showing the shape of the semiconductor wafer before polishing, and FIG. 4 is a shape of the semiconductor wafer polished by the conventional polishing method. FIG. 5 is a schematic side sectional view showing a conventional polishing method.
【０００７】本発明を従来技術と比較するために、便宜
上、研磨を２段階に分割し、それぞれの段階の研磨によ
り得られた半導体ウェハの形状により、本発明の研磨方
法を説明する。In order to compare the present invention with the prior art, polishing is divided into two steps for convenience, and the polishing method of the present invention will be described by the shape of the semiconductor wafer obtained by the polishing in each step.
【０００８】図３に示すように、研磨する前の半導体ウ
ェハ１０は、平坦度の高いウェハである。この半導体ウ
ェハ１０を研磨するに当たっては、まず図１（ａ）に示
すように、半導体ウェハ１０を保持して、研磨クロス５
に押圧するトップリング部３の底面のセラミックプレー
ト３１にバッキングパッド３２を固着し、これに従来技
術と同様に半導体ウェハ１０より薄いテンプレート１ａ
を固着して、これにより半導体ウェハ１０を保持する。
研磨クロス５を固着するセラミック製の定盤４の上面に
シリコーンラバーシート２を固着して、その上に研磨ク
ロス５を固着する。このシリコーンラバーシート２の厚
さは、厚過ぎると研磨クロス５の研磨面の安定度を損な
う恐れがあるため、０．５〜３．０ｍｍ程度が望まし
い。トップリング部３を降ろして、半導体ウェハ１０を
この研磨クロス５に当接させて研磨する。As shown in FIG. 3, the semiconductor wafer 10 before polishing has a high flatness. In polishing the semiconductor wafer 10, first, as shown in FIG. 1A, the semiconductor wafer 10 is held and the polishing cloth 5 is held.
The backing pad 32 is fixed to the ceramic plate 31 on the bottom surface of the top ring portion 3 which is pressed against the template plate 1a thinner than the semiconductor wafer 10 in the same manner as in the prior art.
Are fixed to hold the semiconductor wafer 10.
The silicone rubber sheet 2 is fixed on the upper surface of the ceramic surface plate 4 to which the polishing cloth 5 is fixed, and the polishing cloth 5 is fixed thereon. If the thickness of the silicone rubber sheet 2 is too thick, the stability of the polishing surface of the polishing cloth 5 may be impaired, so that the thickness is preferably about 0.5 to 3.0 mm. The top ring portion 3 is lowered, and the semiconductor wafer 10 is brought into contact with the polishing cloth 5 and polished.
【０００９】図２（ａ）に示すように、この研磨により
得られた半導体ウェハ１０の研磨面１１ａは、従来技術
で発生していたうねり１２ｂ（図４参照）の発生が防止
され滑らかではあるものの、外周部が切り立ち湾曲した
形状となる。As shown in FIG. 2 (a), the polishing surface 11a of the semiconductor wafer 10 obtained by this polishing is smooth because the generation of the waviness 12b (see FIG. 4) which has been generated in the prior art is prevented. However, the outer peripheral portion has a shape that is cut and curved.
【００１０】そこで、次に図１（ｂ）に示すように、テ
ンプレート１ａに替え、研磨する前の半導体ウェハ１０
と略同じ厚さのテンプレート１をバッキングパッド３２
に固着し、これにより半導体ウェハ１０を保持し、これ
を上記と同様にシリコーンラバーシート２の上に固着さ
せた研磨クロス５に当接させて研磨する。Therefore, as shown in FIG. 1B, the semiconductor wafer 10 before polishing is replaced with the template 1a.
The backing pad 32 which is approximately the same thickness as the template 1
The semiconductor wafer 10 is held by this, and this is brought into contact with the polishing cloth 5 fixed on the silicone rubber sheet 2 in the same manner as described above and polished.
【００１１】この研磨方法においては、トップリング部
３の押圧により半導体ウェハ１０とテンプレート１とが
研磨クロス５に同時に当接して研磨され、これにより研
磨圧が均一に負荷され、図２（ｂ）に示すように、半導
体ウェハ１０の研磨面１１が研磨前の形状を損なうこと
なく、平坦に研磨される。In this polishing method, the semiconductor wafer 10 and the template 1 are simultaneously abutted against the polishing cloth 5 by the pressing of the top ring portion 3 to be polished, whereby a polishing pressure is uniformly applied, and FIG. As shown in, the polishing surface 11 of the semiconductor wafer 10 is polished flat without damaging the shape before polishing.
【００１２】尚、テンプレート１の厚さは研磨クロス５
との当接面を考慮し、研磨する前の半導体ウェハ１０の
厚さを基準としており、半導体ウェハ１０の厚さと同じ
厚さのものが望ましいが、厳密に個々の半導体ウェハの
厚さに合わせてテンプレートを選択するのではなく、こ
の研磨方法における取代（２〜１５μｍ程度）を考慮
し、半導体ウェハとテンプレートとの厚さの差は、その
絶対値が１００μｍ以下であることが望ましく、好まし
くは５０μｍ以下、さらに好ましくは２０μｍ以下であ
ることが望ましい。The thickness of the template 1 is the polishing cloth 5
The thickness of the semiconductor wafer 10 before polishing is taken as a reference in consideration of the contact surface with and the thickness of the semiconductor wafer 10 is preferably the same as the thickness of the semiconductor wafer 10. However, it is strictly adjusted to the thickness of each semiconductor wafer. In consideration of the machining allowance (about 2 to 15 μm) in this polishing method, the absolute value of the difference between the thickness of the semiconductor wafer and the template is preferably 100 μm or less, and more preferably, the template is not selected. The thickness is preferably 50 μm or less, more preferably 20 μm or less.
【００１３】また、上記実施例では、定盤４と研磨クロ
ス５との間にシリコーンラバーシート２を介在させてい
たが、これに限られるものではなく、硬度がＪＩＳ規格
Ｋ６３０１（Ａ形）に基づく測定値で２０〜９０度程度
のものであれば同様の効果を得られ、好ましくは３０〜
６０度程度のものが望ましい。したがって、例えばフッ
素ゴムやアクリルゴム、またはもう１枚若しくは複数枚
の研磨クロスを介在させたものでもよい。Further, in the above embodiment, the silicone rubber sheet 2 is interposed between the surface plate 4 and the polishing cloth 5, but the invention is not limited to this, and the hardness is JIS standard K6301 (A type). Based on a measured value of about 20 to 90 degrees, the same effect can be obtained, preferably 30 to 90 degrees.
It is preferably about 60 degrees. Therefore, for example, fluororubber, acrylic rubber, or one or more polishing cloths may be interposed.
【００１４】[0014]
【発明の効果】本発明では以上のように構成したので、
従来技術における研磨で発生していた半導体ウェハの研
磨面のうねり及び湾曲を解消し、平坦度の高い研磨がで
きるという優れた効果がある。According to the present invention, the configuration is as described above.
There is an excellent effect that the waviness and the curvature of the polished surface of the semiconductor wafer, which has been generated by the conventional polishing, can be eliminated, and polishing with high flatness can be performed.
【図１】本発明に係る研磨方法を示す模式図ある。FIG. 1 is a schematic view showing a polishing method according to the present invention.
【図２】本発明の研磨方法により研磨された半導体ウェ
ハの側断面図である。FIG. 2 is a side sectional view of a semiconductor wafer polished by the polishing method of the present invention.
【図３】研磨前の半導体ウェハの形状を示す側断面図で
ある。FIG. 3 is a side sectional view showing the shape of a semiconductor wafer before polishing.
【図４】従来技術の研磨方法により研磨された半導体ウ
ェハの形状を示す側断面図である。FIG. 4 is a side sectional view showing a shape of a semiconductor wafer polished by a conventional polishing method.
【図５】従来技術の研磨方法を示す模式図である。FIG. 5 is a schematic view showing a conventional polishing method.
１‥‥‥テンプレート １ａ‥‥テンプレート ２‥‥‥シリコーンゴムシート ３‥‥‥トップリング部 ３１‥‥セラミックプレート ３２‥‥バッキングパッド ４‥‥‥定盤 ５‥‥‥研磨クロス １０‥‥半導体ウェハ １１‥‥研磨面 １１ａ‥研磨面 １１ｂ‥研磨面 １２ｂ‥うねり 1 ... Template 1a ... Template 2 ... Silicone rubber sheet 3 ... Top ring part 31 ... Ceramic plate 32 ... Backing pad 4 ... Surface plate 5 ... Polishing cloth 10 ... Semiconductor wafer 11 ... Polishing surface 11a ... Polishing surface 11b ... Polishing surface 12b ... Waviness
Claims (6)
定盤に固着された研磨クロスに当接させて研磨する半導
体ウェハの研磨方法において、前記定盤と前記研磨クロ
スの間に弾力性を有するシートを介在させて研磨するこ
とを特徴とする半導体ウェハの研磨方法。1. A semiconductor wafer is held by a template,
In a method for polishing a semiconductor wafer which is brought into contact with a polishing cloth fixed to a surface plate to polish, a semiconductor wafer is characterized in that an elastic sheet is interposed between the surface plate and the polishing cloth for polishing. Polishing method.
プレートにより前記半導体ウェハを保持することを特徴
とする請求項１記載の半導体ウェハの研磨方法。2. The method of polishing a semiconductor wafer according to claim 1, wherein the semiconductor wafer is held by a template having substantially the same thickness as the semiconductor wafer.
シートであることを特徴とする請求項１記載の半導体ウ
ェハの研磨方法。3. The method for polishing a semiconductor wafer according to claim 1, wherein the elastic sheet is a silicone rubber sheet.
差が１００μｍ以下であることを特徴とする請求項２記
載の半導体ウェハの研磨方法。4. The method for polishing a semiconductor wafer according to claim 2, wherein the difference in thickness between the semiconductor wafer and the template is 100 μm or less.
格Ｋ６３０１（Ａ形）に基づく測定値で２０〜９０度で
あることを特徴とする請求項１記載の半導体ウェハの研
磨方法。5. The method for polishing a semiconductor wafer according to claim 1, wherein the hardness of the elastic sheet is 20 to 90 degrees as a measured value based on JIS standard K6301 (A type).
３．０ｍｍであることを特徴とする請求項３記載の半導
体ウェハの研磨方法。6. The thickness of the silicone rubber sheet is 0.5 to.
The method for polishing a semiconductor wafer according to claim 3, wherein the polishing method is 3.0 mm.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17534696A JPH09321001A (en) | 1996-05-31 | 1996-05-31 | Method for polishing semiconductor wafer |
| TW086103793A TW317522B (en) | 1996-05-31 | 1997-03-25 | Surface lapping method for wafer of semiconductor |
| US08/865,892 US5893755A (en) | 1996-05-31 | 1997-05-30 | Method of polishing a semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17534696A JPH09321001A (en) | 1996-05-31 | 1996-05-31 | Method for polishing semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09321001A true JPH09321001A (en) | 1997-12-12 |
Family
ID=15994468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17534696A Pending JPH09321001A (en) | 1996-05-31 | 1996-05-31 | Method for polishing semiconductor wafer |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5893755A (en) |
| JP (1) | JPH09321001A (en) |
| TW (1) | TW317522B (en) |
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|---|---|---|---|---|
| US6749486B2 (en) | 2000-02-24 | 2004-06-15 | Tokyo Electron Limited | Chemical-mechanical polishing device, damascene wiring forming device, and damascene wiring forming method |
| JP2006116675A (en) * | 2004-10-25 | 2006-05-11 | Komatsu Electronic Metals Co Ltd | Abrasive cloth and wafer polishing device |
| WO2014119598A1 (en) * | 2013-01-31 | 2014-08-07 | 株式会社 荏原製作所 | Polishing device, method for applying polishing pad, and method for replacing polishing pad |
| JP2015205389A (en) * | 2014-04-23 | 2015-11-19 | 株式会社ディスコ | Polishing pad and polishing device |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2750354B1 (en) * | 1996-06-28 | 1998-08-07 | Lam Plan Sa | POLISHING DISC HOLDER AND POLISHING METHOD |
| US6017822A (en) * | 1998-09-16 | 2000-01-25 | The United States Of America As Represented By The National Security Agency | Method of thinning semiconductor wafer of smaller diameter than thinning equipment was designed for |
| US6468139B1 (en) | 1998-12-01 | 2002-10-22 | Nutool, Inc. | Polishing apparatus and method with a refreshing polishing belt and loadable housing |
| US6464571B2 (en) * | 1998-12-01 | 2002-10-15 | Nutool, Inc. | Polishing apparatus and method with belt drive system adapted to extend the lifetime of a refreshing polishing belt provided therein |
| US6103628A (en) * | 1998-12-01 | 2000-08-15 | Nutool, Inc. | Reverse linear polisher with loadable housing |
| US6589105B2 (en) | 1998-12-01 | 2003-07-08 | Nutool, Inc. | Pad tensioning method and system in a bi-directional linear polisher |
| US7425250B2 (en) * | 1998-12-01 | 2008-09-16 | Novellus Systems, Inc. | Electrochemical mechanical processing apparatus |
| US6093086A (en) * | 1999-09-24 | 2000-07-25 | Lucent Technologies Inc. | Polishing head release mechanism |
| JP2001179609A (en) * | 1999-12-28 | 2001-07-03 | Roki Techno Co Ltd | Polishing pad |
| DE10009656B4 (en) * | 2000-02-24 | 2005-12-08 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE10012840C2 (en) * | 2000-03-16 | 2001-08-02 | Wacker Siltronic Halbleitermat | Process for the production of a large number of polished semiconductor wafers |
| DE10058305A1 (en) * | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Process for the surface polishing of silicon wafers |
| US6939203B2 (en) * | 2002-04-18 | 2005-09-06 | Asm Nutool, Inc. | Fluid bearing slide assembly for workpiece polishing |
| US7648622B2 (en) * | 2004-02-27 | 2010-01-19 | Novellus Systems, Inc. | System and method for electrochemical mechanical polishing |
| US7226345B1 (en) | 2005-12-09 | 2007-06-05 | The Regents Of The University Of California | CMP pad with designed surface features |
| CN106992112A (en) * | 2016-01-21 | 2017-07-28 | 苏州新美光纳米科技有限公司 | The polishing method of ultra thin wafer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4910155A (en) * | 1988-10-28 | 1990-03-20 | International Business Machines Corporation | Wafer flood polishing |
| US5232875A (en) * | 1992-10-15 | 1993-08-03 | Micron Technology, Inc. | Method and apparatus for improving planarity of chemical-mechanical planarization operations |
| US5736427A (en) * | 1996-10-08 | 1998-04-07 | Micron Technology, Inc. | Polishing pad contour indicator for mechanical or chemical-mechanical planarization |
-
1996
- 1996-05-31 JP JP17534696A patent/JPH09321001A/en active Pending
-
1997
- 1997-03-25 TW TW086103793A patent/TW317522B/en not_active IP Right Cessation
- 1997-05-30 US US08/865,892 patent/US5893755A/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6749486B2 (en) | 2000-02-24 | 2004-06-15 | Tokyo Electron Limited | Chemical-mechanical polishing device, damascene wiring forming device, and damascene wiring forming method |
| JP2006116675A (en) * | 2004-10-25 | 2006-05-11 | Komatsu Electronic Metals Co Ltd | Abrasive cloth and wafer polishing device |
| WO2014119598A1 (en) * | 2013-01-31 | 2014-08-07 | 株式会社 荏原製作所 | Polishing device, method for applying polishing pad, and method for replacing polishing pad |
| JP2015205389A (en) * | 2014-04-23 | 2015-11-19 | 株式会社ディスコ | Polishing pad and polishing device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW317522B (en) | 1997-10-11 |
| US5893755A (en) | 1999-04-13 |
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