JPH09245491A - Audio filing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten recording time of a digital voice signal by shortening erasion time of a memory element. SOLUTION: A continuous address is applied sequentially to blocks at the same positions of chips 11-1n of a flash memory 1. An erasion demand processing part 21 of a memory erasion/writing control section 2 sets an erasion demand/erasion executing duration flag 25 based on an erasion demand from outside. An erasion start processing section 22 issues an erasion command almost simultaneously to the blocks of the chips 11-1n to be erased based on the set contents of the erasion demand/erasion executing duration flag 25 in the sequence of continuous addresses. An erasion end processing section 23 sets the erasion demand/erasion executing duration flag 25 based on an erasion end interruption from the flash memory 1. A writing processing part 24 performs a writing into blocks of the chips 11-1n demanded for writing from outside based on the set contents of the erasion demand/erasion executing duration flag 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio file device, and more particularly to an audio file device for recording a large amount of data such as voice data in a flash memory.

[0002]

2. Description of the Related Art Conventionally, in this type of audio file apparatus, programs and C are mainly used in broadcasting stations such as televisions and radios.
It is used to record audio material such as M (commercial) and broadcast the recorded content.

That is, this audio file apparatus converts an analog signal into a digital audio signal by A / D (analog / digital) conversion and records it on a recording medium such as a hard disk, an optical disc, and a semiconductor memory, and the recording medium is recorded on this recording medium. It is used in a device or the like for reproducing a voice by converting a recorded voice material into an analog voice signal by D / A (digital / analog) conversion.

Some of the above audio file devices use a flash memory as a recording medium for digital audio signals. The flash memory is an electrically erasable non-volatile memory and has a structure divided into a plurality of erasing units which are memory spaces. Less than,
The part divided by this erase unit is a block.

Normally, only one block can be erased in the same flash memory. When recording a digital voice signal in the flash memory, it is necessary to erase the block in advance and then write the digital voice signal. Therefore, the recording time of the flash memory is the sum of the erasing time and the recording time.

When assigning addresses to a memory, it is general that addresses are consecutively assigned in the same memory. If you assign an address to the flash memory in this way,
Blocks of the same flash memory are assigned consecutive addresses.

That is, as shown in FIG. 6, blocks 1, 2, 3, 4, 5, ...
2, a-1 and a have addresses "1", "2",
"3", "4", "5", ..., "a-3", "a-"
2 ”,“ a-1 ”, and“ a ”are assigned.

Blocks 1, 2, 3 in the next chip 2
4,5, ..., a-3, a-2, a-1, a has "a +
1 ”,“ a + 2 ”,“ a + 3 ”,“ a + 4 ”,“ a +
5 ", ...," 2a-3 "," 2a-2 "," 2a- "
"1" and "2a" are allocated.

Further, blocks 1, 2, 3, 4, 5, ..., A-3, a-2, a-1, in the chip (n-1)
a is "(n-2) a + 1", "(n-2) a + 2",
"(N-2) a + 3", "(n-2) a + 4", "(n
-2) a + 5 ", ...," (n-1) a-3 "," (n
-1) a-2 "," (n-1) a-1 "," (n-1) "
a ”is assigned.

Furthermore, the block 1 in the chip n is
2, 3, 4, 5, ..., A-3, a-2, a-1, a have "(n-1) a + 1", "(n-1) a + 2",
"(N-1) a + 3", "(n-1) a + 4", "(n
-1) a + 5 ", ...," na-3 "," na-2 ",
"Na-1" and "na" are assigned.

When erasing the contents of the flash memory, only one block in the same flash memory can be erased. Therefore, when erasing all the blocks of one flash memory, it is included in one flash memory. The time required is a product of the number of blocks to be erased and the time required to erase one block.

[0012]

In the conventional audio file apparatus described above, when the flash memory is used as the recording medium, the memory space of the flash memory is divided into a plurality of blocks. When a digital audio signal is recorded on a device, the block must be erased in advance and then the writing operation of the digital audio signal must be performed. Therefore, the flash memory needs a recording time that is the sum of the erasing time and the recording time. Become.

Further, the erasing time requires a product of the number of blocks contained in one flash memory and the time required to erase one block.
It takes a lot of time to record the digital voice signal in the flash memory.

Japanese Patent Publication No. 1-57438 discloses EEPR.
OM (electrically erasable programmable fixed memory)
Discloses a technique in which an erase signal is connected to all columns or rows to erase one column or one row of a memory device in one operation.

However, in column or row erasing, the next column or row cannot be erased until the erasing of each column or row is completed, so the erasing time is the same for column erasing and row erasing, and the erasing time can be shortened. I can't.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and to provide an audio file apparatus which can shorten the erasing time of a memory element and the recording time of a digital audio signal.

[0017]

SUMMARY OF THE INVENTION An audio file device according to the present invention is an audio file device for storing digital audio signals, which comprises a plurality of electrically erasable non-volatile memory elements each composed of a plurality of blocks. , Means for erasing blocks at the same position of each of the plurality of nonvolatile memory elements at substantially the same time.

Another audio file device according to the present invention is an audio file device for storing a digital audio signal, which comprises a plurality of electrically erasable non-volatile memory devices each composed of a plurality of blocks, and a plurality of said plurality of non-volatile memory devices. And a means for erasing the contents of the blocks of the non-volatile memory element at substantially the same time in the order of successive addresses sequentially assigned.

Another audio file device according to the present invention is an audio file device for storing a digital audio signal, which is electrically erasable and comprises a plurality of non-volatile memory elements each comprising a plurality of blocks, and a plurality of said plurality of nonvolatile memory elements. An erase request flag which is provided corresponding to a block and holds an erase request for the corresponding block, and an erase execution flag which is provided corresponding to the plurality of blocks and holds information indicating that the corresponding block is being erased And means for generating the erase requests at substantially the same time in the order of consecutive addresses sequentially assigned to the blocks at the same position in each of the plurality of nonvolatile memory devices, and the contents of the erase request flag and the erase in-progress flag And means for continuously writing to the corresponding block.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

Each chip that constitutes an electrically erasable flash memory is composed of a plurality of blocks, and consecutive addresses are allocated to blocks at the same position. The contents of the blocks at the same position of each of the plurality of chips are erased substantially at the same time.

As a result, the erasing time in the flash memory can be shortened and the recording time of the digital audio signal can be shortened.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, an audio file device according to an embodiment of the present invention includes a flash memory 1 and a memory erasing / writing control unit 2.

The flash memory 1 is composed of chips 11 to 1n, and each of the chips 11 to 1n is composed of a plurality of blocks. Consecutive addresses are sequentially given to blocks at the same position of each of the chips 11 to 1n.

The memory erase / write control unit 2 includes an erase request processing unit 21, an erase start processing unit 22, and an erase end processing unit 2.
3, a write processing section 24, and an erase request / erase execution flag 25.

The erase request processing unit 21 sets an erase request / erase execution flag 25 corresponding to a block of the chips 11 to 1n to be erased based on an erase request from the outside.
The erasure start processing unit 22 uses the erasure request / erase execution flag 25.
The erase commands for the blocks of the chips 11 to 1n to be erased are issued in the order of consecutive addresses based on the setting contents of.

That is, the erase start-up processing unit 22 sends 1 to the erase command for the blocks of the chips 11 to 1n to be erased.
Since it is issued continuously without waiting until the erase of the contents of one block is completed, these erase commands are issued almost at the same time.

The erase start processing unit 22 generates and stores the corresponding erase command while confirming the setting contents of the erase request / erase execution flag 25, and after storing the erase command for each of the chips 11 to 1n, erases them. It is also possible to output the commands to the flash memory 1 at the same time.

The erasing end processing unit 23 is the flash memory 1
The erase request / erase execution flag 25 corresponding to the blocks of the chips 11 to 1n that have been erased is set based on the erase end interrupt from

The write processing unit 24 reads the setting contents of the erase request / erase in progress flag 25 corresponding to the blocks of the chips 11 to 1n to be written based on the write request from the outside, and writes based on the setting contents. Chips 11 to
Write to the 1n block. The erase request / erase execution flag 25 holds in advance an erase request flag and an erase execution flag corresponding to each block of each of the chips 11 to 1n.

FIG. 2 is a diagram showing address allocation to the flash memory 1 of FIG. In the figure, each of the chips 11 to 1n of the flash memory 1 is composed of a plurality of blocks, and consecutive addresses are sequentially given to the blocks at the same position.

That is, in the block 1 of each of the chips 11 to 1n, consecutive addresses "1", "2", ...
"N-1" and "n" are allocated, and consecutive addresses "n + 1" and "n + 1" are assigned to the blocks 2 of the chips 1 to n, respectively.
“N + 2”, ..., “2n−1”, “2n” are assigned.

Similarly, consecutive addresses "2n + 1" and "2n +" are assigned to the blocks 3 of the chips 11 to 1n, respectively.
2 ”, ...,“ 3n-1 ”,“ 3n ”are assigned,
Addresses “3n + 1”, “3n + 2”, ..., “4n−” that are continuous in the block 4 of each of the chips 11 to 1n.
1 ”and“ 4n ”are allocated, and consecutive addresses“ 4n + 1 ”, respectively, are assigned to the blocks 5 of the chips 11 to 1n.
“4n + 2”, ..., “5n−1”, “5n” are assigned.

The blocks (a-3) of each of the chips 11 to 1n have consecutive addresses "(a-4) n +".
1 "," (a-4) 2n + 2 ", ...," (a-3) n "
-1 "and" (a-3) n "are assigned to the chip 11
Each of the blocks (a-2) of 1 to 1n has consecutive addresses “(a-3) n + 1”, “(a-3) n + 2”, ...
..., "(a-2) n-1", "(a-2) n" are assigned.

Further, in the block (a-1) of each of the chips 11 to 1n, consecutive addresses "(a-2) n +" are provided.
1 "," (a-2) n + 2 ", ...," (a-1) n- "
1 ”and“ (a-1) n ”are allocated, and chips 11 to 11 are allocated.
In each of the 1n blocks a, consecutive addresses “(a
-1) n + 1 "," (a-1) n + 2 ", ...," an
"-1" and "an" are assigned.

Therefore, when the data is continuously written to the flash memory 1 in the above-mentioned address order, it becomes possible to erase the same block from the chip 11 to the chip 1n, for example, the block 1 substantially at the same time. So
When the erasing of the block 1 of the chip 11 is completed, continuous data writing from the address "1" to the address "n" becomes possible.

That is, when data is written to consecutive addresses, the writing operation is performed on different chips for each address to be written, so that the erasing operation is also performed for each chip. In this case, since the erase time of the blocks in each chip is the same, the erase operation from the block 1 of the chip 12 to the block 1 of the chip 1n ends almost at the same time when the erase of the contents of the block 1 of the chip 11 ends. , When writing continuous data, it is not necessary to wait for the end of all blocks to be written.

FIG. 3 is a flow chart showing an erase request process for the flash memory 1 of FIG. These figures 1
The erase request processing for the flash memory 1 according to the embodiment of the present invention will be described with reference to FIGS.

When the erase request processing unit 21 issues an erase request to the flash memory 1, the erase request processing unit 21 first inputs the initial value (n = 0) of the chip number n of the block that needs to be erased. From (step S1 in FIG. 3), the initial value (a = 0) of the block number a is input (step S2 in FIG. 3).

After that, the erase request processing section 21 sets the erase request flag of the block number a of the chip number n to "1" (step S3 in FIG. 3). In this case, the erase request flag is "1" to indicate that there is an erase request, and "0" to indicate that there is no erase request.

Subsequently, the erase request processing section 21 sets the erase in-execution flag of the block number a of the chip number n to "0".
(Step S4 in FIG. 3). In this case, the erasing execution flag is "0" to indicate that erasing has not been executed and "1" to indicate that erasing is being executed.

When the setting of the erasing execution flag is completed, the erasing request processing section 21 confirms whether the chip number n is the final number (step S5 in FIG. 3). When it is confirmed that the chip number n is the final number, the erase request processing unit 21 returns the chip number to the initial value (n = 0) (step S7 in FIG. 3) and determines whether the block number a is the final number. Is confirmed (step S8 in FIG. 3).

If it is not confirmed that the chip number n is the final number, the erasure request processing section 21 determines the chip number n.
Is incremented by 1 (n = n + 1) (step S6 in FIG. 3) to set the erase request flag and the erase in-progress flag for the block number a of the chip number n (step S3 in FIG. 3).
S4). That is, the erase request processing unit 21 sets the erase request flag and the erase in-progress flag for the same block of different chips for all the same blocks.

When it is confirmed that the block number a is the final number, the erase request processing section 21 ends the process. If it is not confirmed that the block number a is the final number, the erase request processing unit 21 adds 1 to the block number a (a = a + 1) (step S9 in FIG. 3), and erase request for this block number a. The flag and the erasure execution flag are set (steps S3 to S6 in FIG. 3). That is, the erasure request processing unit 21 executes the settings of the erasure request flag and the erasure in progress flag for all the blocks that need to be erased.

FIG. 4 is a flowchart showing the erase start processing for the flash memory 1 of FIG. These figures 1
The erase start processing for the flash memory 1 according to the embodiment of the present invention will be described with reference to FIGS. 2 and 4.

When erasing and activating the flash memory 1 by the erasing activation processing section 22, the erasing activation processing section 22 first inputs the initial value (n = 0) of the chip number n of the block that needs to be erased. From (step S11 in FIG. 4), the initial value (a = 0) of the block number a is input (step S12 in FIG. 4).

After that, the erase start processing unit 22 confirms whether the erase request flag of the block number a of the chip number n is "1" and the erase execution flag is "0" (steps S13 and S14 in FIG. 4). ). When these conditions are satisfied, the erase activation processing unit 22 issues an erase command for the block number a of the chip number n (step S15 in FIG. 4), and sets the erase in progress flag to “1” (step S16 in FIG. 4).

Then, the erase start processing section 22 confirms whether the chip number n is the final number (step S17 in FIG. 4). When it is confirmed that the chip number n is the final number, the erase start processing unit 22 sets the chip number to the initial value (n
= 0) (step S19 in FIG. 4), block number a
Is the final number (step S in FIG. 4).
20).

If it is not confirmed that the chip number n is the final number, the erase start processing section 22 sets 1 to the chip number n.
Are added (n = n + 1) (step S18 in FIG. 4), and the erase request flag and the erasure execution flag for the block number a of the chip number n are confirmed (step S1 in FIG. 4).
3, S14).

When it is confirmed that the block number a is the final number, the erase start processing section 22 ends the process. If it is not confirmed that the block number a is the final number, the erase start processing unit 22 adds 1 to the block number a (a = a + 1) (step S21 in FIG. 4), and issues an erase request to the block number a. The flag and the erasing execution flag are confirmed (steps S13 and S14 in FIG. 4). That is, the erase start processing unit 22 executes the above-described issuance of the erase command and the setting of the erase-execution flag for all the blocks that need to be erased.

FIG. 5 is a flow chart showing an erase end process for the flash memory 1 of FIG. These figures 1
The erasing end process for the flash memory 1 according to the embodiment of the present invention will be described with reference to FIGS.

When the erasing end interrupt is generated from the flash memory 1, the erasing end processing unit 23 reads the status of the erasing of the contents of which block of which chip has been completed from the status from the flash memory 1 (step S31 in FIG. 5).

The erase end processing section 23 sets the erase request flag of the read chip number n and block number a to "0" and the erase in progress flag to "0" (steps S32 and S3 in FIG. 5).
3), end the process.

FIG. 6 is a flow chart showing a writing process to the flash memory 1 of FIG. A writing process to the flash memory 1 according to the embodiment of the present invention will be described with reference to FIGS. 1, 2, and 6.

When the write processing unit 24 performs write processing on the flash memory 1, the write processing unit 24 first writes the initial value (n) of the chip number n of the block that needs to be written.
= 0) is input (step S41 in FIG. 6), and then the initial value (a = 0) of the block number a is input (step S42 in FIG. 6).

After that, the write processing unit 24 confirms whether the erase request flag of the block number a of the chip number n is "0" and the erase execution flag is "0" (steps S43 and S44 in FIG. 6). . When these conditions are satisfied, the write processing unit 24 executes the write processing for the block number a of the chip number n (step S45 in FIG. 6).

Then, the write processing unit 24 determines the chip number n.
Is the final number (step S in FIG. 6).
46). When it is confirmed that the chip number n is the final number, the writing processing unit 24 sets the chip number to the initial value (n =
0) (step S48 in FIG. 6), and it is confirmed whether the block number a is the final number (step S4 in FIG. 6).
9).

If it is not confirmed that the chip number n is the final number, the write processing unit 24 adds 1 to the chip number n (n = n + 1) (step S47 in FIG. 6), and the block number of the chip number n. The erasure request flag and the erasure execution flag for a are confirmed (step S4 in FIG. 6)
3, S44).

When it is confirmed that the block number a is the final number, the write processing unit 24 ends the process. If it is not confirmed that the block number a is the final number, the write processing unit 24 adds 1 to the block number a (a = a + 1) (step S50 in FIG. 6) and erase request flag for the block number a. Then, the erasure execution flag is confirmed (steps S43 and S44 in FIG. 6). That is, the write processing unit 24 executes the above-described write processing for all the blocks that need to be written.

In this way, consecutive addresses are allocated to blocks at the same positions of the respective chips 11 to 1n of the flash memory 1, and the erase request processing unit 21 and the erase start processing unit 22 allocate each of these chips 11 to 1n. By erasing the contents of the block at the same position substantially at the same time, the erasing time in the flash memory 1 can be shortened and the recording time of the digital audio signal can be shortened.

That is, assuming that the time required for erasing one block is t, the time t1 for erasing n blocks in the conventional audio file apparatus is t1 = t × n. In other words, the erasing of the next block is made to wait until one block is completed. Therefore, the erasing time is the time t required to erase one block multiplied by the number of blocks to be erased.

On the other hand, in the embodiment of the present invention, since the erase command is issued to each of the n blocks continuously at the time t2 for erasing the n blocks,
If the issuing time is b, then t2 = t + b. In this case, in one embodiment of the present invention, erasing for n blocks becomes erasing for each of the chips 11 to 1n, and the issuing time b of the erase command for each of the n blocks is almost 0, so t2≈t. Become. That is, the erase time of the block according to the embodiment of the present invention is shortened to about 1 / n of the conventional method.

[0063]

As described above, according to the present invention, the contents of the blocks at the same position of each of the plurality of electrically erasable non-volatile memory elements each including a plurality of blocks are erased substantially at the same time. There is an effect that the erase time of the contents of the non-volatile memory can be shortened and the recording time of the digital audio signal can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing address allocation for the flash memory of FIG.

FIG. 3 is a flowchart showing an erase request process for the flash memory of FIG.

FIG. 4 is a flowchart showing an erase start process for the flash memory of FIG.

5 is a flowchart showing an erase end process for the flash memory of FIG.

FIG. 6 is a flowchart showing a writing process to the flash memory of FIG.

FIG. 7 is a diagram showing address allocation to a conventional flash memory.

[Explanation of symbols]

 1 Flash Memory 2 Memory Erase / Write Control Unit 11 to 1n Chip 21 Erase Request Processing Unit 22 Erase Activation Processing Unit 23 Erase End Processing Unit 24 Write Processing Unit 25 Erase Request / Erase Execution Flag

Claims (3)

[Claims] 1. An audio file device for storing digital audio signals, comprising a plurality of electrically erasable non-volatile memory elements each comprising a plurality of blocks.
An audio file device, comprising means for erasing blocks at the same position of each of the plurality of nonvolatile memory elements substantially at the same time. 2. An audio file device for storing a digital audio signal, comprising a plurality of electrically erasable non-volatile memory elements each composed of a plurality of blocks.
An audio file apparatus comprising: means for erasing the contents of blocks of the same position in each of the plurality of non-volatile memory elements at substantially the same time in the order of consecutive addresses. 3. An audio file device for storing digital audio signals, comprising a plurality of electrically erasable non-volatile memory elements each comprising a plurality of blocks,
An erase request flag provided corresponding to the plurality of blocks and holding an erase request for the corresponding blocks,
An erase-in-progress flag that is provided corresponding to the plurality of blocks and holds information indicating that the erase is being performed in the corresponding blocks, and a sequentially-applied flag to blocks at the same position in each of the plurality of nonvolatile memory elements. A means for generating the erase requests at substantially the same time in the order of successive addresses, and means for continuously writing to a corresponding block in accordance with the contents of the erase request flag and the erase in-progress flag. Audio file device.