JPH09134594A - Semiconductor nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable, highly integrated nonvolatile ferroelectric memory exerting a long life to a fatigue of a ferroelectric capacitor, by constituting the memory of a memory cell for storing information and a dummy cell for judging stored information. SOLUTION: The drawing shows a constitution of a cell of a ferroelectric memory. A pair of data lines DLMm and BLMm wherein (m) is the order of an array are coupled to one sense amplifier per unit array. To each data line are connected (n) memory cells consisting of a ferroelectric capacitor CFE and a field effect transistor, and a dummy cell of a combination of a cell of the same shape as the memory cell and a cell of a paraelectric capacitor CO and a field effect transistor. The ferroelectric capacitor of the dummy cell is polarized in a direction not to cause a polarization inversion during the operation. A capacity of the paraelectric capacitor CO is determined to be lower than an intermediate value of potentials of two signals output to the data line corresponding to binary information stored in the memory cell.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a nonvolatile semiconductor memory using a ferroelectric substance.

[0002]

2. Description of the Related Art A memory using a ferroelectric material is a dynamic random access memory (D) which is widely used at present.
Reading and writing can be done in a short time almost equal to that of RAM). In addition, it has a non-volatile property in which information is held even without a power source. Ferroelectric memories are mainly classified into a capacitor type with a transistor having a cell structure similar to that of a DRAM and a MOS transistor type using a ferroelectric film as an insulating film of a MOS transistor. The former is a two-transistor / two-capacitor (hereinafter referred to as 2Tr2C) type in which two cells having mutually opposite remanent polarization directions are set as one set and one piece of information is recorded by a combination of polarizations, and one cell records one piece of information. There is a one-transistor-one-capacitor (1Tr1C) type.
In the 1Tr1C type suitable for high integration, it is necessary to generate a reference potential (reference potential) in order to determine the direction of remanent polarization when reading.

Several methods using a dummy cell have been proposed as methods for generating a reference potential. As an example, FIG. 10 shows an array configuration using dummy cells described in Japanese Patent Laid-Open No. 63-201998. In this example, the capacitor area of the dummy cell is made twice or more the memory cell capacitor area, and the capacity of the dummy cell at the time of non-inversion of polarization is
The capacitance value is between the capacitance of the memory cell capacitor when the polarization is inverted and the capacitance when the polarization is not inverted. During reading, the dummy cell capacitor is used without being inverted to generate a potential between the inverted and non-inverted potentials of the memory cell side data line on the dummy cell side data line. The reference potential has been conventionally determined, for example, by ISSC 1994 Digest of Technical Papers (ISSCC Dig.Tech.Pap.) 26.
As shown on pages 8 to 269, the optimum middle point between the data line potentials on the memory cell side during inversion and non-inversion has been optimized.

[0004]

The method of generating a reference potential using the dummy cell described above has the following problems. (1) It is not considered that the ferroelectric capacitor of the memory cell is fatigued and the data line potential at the time of reading changes due to repeated polarization inversion. The question of how to set it up.

(2) In the method of doubling the capacitor area of the dummy cell more than twice, it is difficult to control the film quality of a fine ferroelectric film, and the capacitance is not always proportional to the area, and it is difficult to obtain a desired capacitance. Problem.

The present invention provides a method for generating a reference potential of a 1Tr1C type ferroelectric memory for solving the problems (1) and (2).

[0007]

In a ferroelectric memory having a 1Tr1C type memory cell structure of the present invention, a memory cell for storing information and a reference potential for judging binary storage information of the memory cell are stored as data. A dummy cell generated in a line, the dummy cell including a paraelectric capacitor and a ferroelectric capacitor having the same shape as the memory cell. The reference potential output to the data line by the dummy cell is output to the data line corresponding to the binary storage information of the memory cell when the ferroelectric capacitor of the memory cell is in a state before fatigue. Of the dummy cells, so that it is lower than just the middle potential of the two signal potentials, preferably higher than the lower potential of the two signal potentials, and the difference is the minimum detectable potential difference of the sense amplifier. Determine the capacitance of the paraelectric capacitor. By making the reference potential lower than the potential just between the two signal potentials,
It is possible to realize a larger number of times of memory access with respect to a decrease in signal amount due to the fatigue phenomenon of the ferroelectric capacitor of the memory cell. Moreover, a ferroelectric capacitor having the same shape as that of the memory cell is used as a dummy cell to generate the lower potential of the above two signal potentials, which is an established technology.
By using the reference potential generation method that generates the potential difference amplified by the sense amplifier using a paraelectric capacitor such as O ₂ or Si ₃ N _{4, the} variation in the signal amount of the memory cell due to the variation in the processing of the ferroelectric film, etc. It is possible to generate a reference potential that is highly reliable and that can set the reading margin with respect to the decrease in the signal amount largely and precisely.

According to another ferroelectric memory of the 1Tr1C type memory cell structure of the present invention, a part of the data lines belonging to the dummy cell is used as a power supply voltage, the other data line parts and a desired memory cell paired with this are provided. The data line to be connected is precharged to another potential and a read operation is performed. When the reference potential generated by the above method is in a state before the ferroelectric capacitor of the memory cell is fatigued, the memory cell outputs exactly the two signal potentials corresponding to binary storage information to the data line. The data for generating the reference potential so that the reference potential is lower than the intermediate potential, preferably higher than the lower potential of the two signal potentials and the difference is the minimum detectable potential difference of the sense amplifier. Precharge lines separately. By setting the reference potential lower than the potential just between the two signal potentials described above, it is possible to realize a larger number of times of memory access with respect to the reduction in the signal amount due to the fatigue phenomenon of the ferroelectric capacitor of the memory cell.
Further, by generating the above-mentioned reference potential by using a dummy cell having the same shape as the memory cell and a part of the precharged data line, it is possible to cope with variations in the signal amount of the memory cell due to variations in processing of the ferroelectric film. The effect that a highly reliable and highly integrated ferroelectric memory can be realized can be obtained.

Another ferroelectric memory having a 1Tr1C type memory cell structure of the present invention is a first ferroelectric memory having a memory cell for storing information and a ferroelectric capacitor having the same shape as the memory cell.
Data line pairs attached with dummy cells and data line pairs attached with second dummy cells each including a paraelectric capacitor and a ferroelectric capacitor having the same shape as the memory cell are alternately arranged and adjacent to each other. Differential sense amplifiers placed between all the two data lines, a selection circuit that can selectively drive two adjacent differential sense amplifiers, and a precharge circuit that can simultaneously select three adjacent data lines. Have. At the time of reading, reference potentials are generated from the first and second dummy cells on two data lines adjacent to the data line outputting the information of the memory cell, and the reference potential and the information of the memory cell are output. The potential of the data line is compared by selectively driving two sense amplifiers connected to the data line to which the information of the memory cell is output, and the information of the memory cell is determined.

The capacitance of the paraelectric capacitor corresponds to binary storage information of the memory cell when the reference potential generated by the second dummy cell is in a state before the ferroelectric capacitor of the memory cell is in a fatigue state. Therefore, it should be lower than the intermediate potential of the two signal potentials output to the data line, preferably higher than the lower potential of the above two signal potentials, and the difference between them should be the minimum detection of the sense amplifier. Determine so that the potential difference is possible. The first dummy cell generates a reference potential having the same potential as the lower potential of the above two signal potentials. By setting the reference potential generated from the second dummy cell to be lower than the intermediate potential between the above-mentioned two signal potentials, a larger memory access can be achieved against a decrease in the signal amount due to the fatigue phenomenon of the ferroelectric capacitor of the memory cell. The number of possible times can be realized. In addition, by generating two reference potentials, the lower output potential of the memory cell is determined by the higher reference potential, and the higher output potential of the memory cell is determined by the lower reference potential. In addition, the sensitivity of the sense amplifier is improved, and a large number of times of memory access can be obtained even when the signal amount is reduced due to the fatigue phenomenon of the ferroelectric capacitor of the memory cell.

In any of the above inventions, the word line attached to the dummy cell is controlled before the potential difference is amplified by the sense amplifier to make the transistor included in the dummy cell non-conductive, and at the end of a series of read operation, the word line is attached. Is preferably controlled so that the transistor becomes conductive and the voltage applied to the capacitor included in the dummy cell becomes zero. By this driving method, destructive reading of the ferroelectric capacitor of the dummy cell can be avoided, and stable generation of the reference potential can be realized.

[0012]

1 is a first embodiment of the present invention showing a cell structure of a ferroelectric memory. In one array unit, two paired data lines DLM _m and BLM _m are coupled to one sense amplifier. m represents the order of the array. Memory cells are n consisting of the ferroelectric capacitor CFE and the field effect transistor to the data line _{(DLM m MC 2n-1 2m} -1 from MC _{1 2m} in, the BLM _m MC ₂ from _2m MC _{2n 2M- 1} ) and a memory cell and a cell of the same shape, and a cell composed of a paraelectric capacitor CO and a field-effect transistor are combined into one dummy cell (DC for DLM _m).
Are DC _2m) bind to _2m-1, BLM _m. The ferroelectric capacitor of the dummy cell is polarized in a direction in which polarization reversal does not occur during operation. The capacitance of the paraelectric capacitor CO is (VREF-VSS) / (VCC-VREF) * CD
-CFE ₀ (CFE ₀ is the non-inverting capacity of CFE, VREF
Is the reference potential).

FIG. 2 is a reference potential generated in the embodiment of FIG. At the time of reading, the potential generated on the data line is a non-inversion signal when the polarization of the ferroelectric capacitor of the memory cell is non-inversion, and the potential generated when the polarization is inverted is an inversion signal. The reference potential VREF is lower than the intermediate potential between the inverted signal and the non-inverted signal, preferably higher than the non-inverted signal, and the difference between them is a potential difference (for example, 20
The potential is 0 mV).

FIG. 3 shows the read operation in FIG. An example of MC _{1 2m-1} cell selection is shown. The dummy cell is a data line pair of the selected memory cell, and DC _2m coupled to the data line BLM _m that is not on the selected memory cell side is selected. First, the PCS switch is turned off to separate the data line pair that has been precharged to VSS and put it in a floating state. At the same time, the word line VW _{1 of the} memory cell and the word line VWD _{2 of the} dummy cell are driven. In this state, the plate lines VP ₁ and VPD ₂ that were precharged to VSS are driven to VCC. At this time, the dummy cell side data line B
The reference potential VREF shown in FIG. 1 is generated at LM _m .
On the other hand, an inverted signal or a non-inverted signal (see FIG. 2) is generated in the memory cell side data line DLM _m , depending on the polarization direction written. After that, VWD ₂ is closed so that the CFE of the dummy cell is not inverted, and the sense amplifier amplifies the potential difference between DLM _m and BLM _m to VSS and VCC. The amplified data line potential is read out to the I / O line by YS _m . After the reading is completed, the plate lines VP ₁ and VPD ₂ are returned to VSS, the CFE of the memory cell is rewritten, and the sense amplifier is turned off. DLM _m and BLM _m to V
The SS is precharged again, VWD ₂ is turned on, and the potential difference applied to the capacitor of the dummy cell is set to zero.
VWD ₂ is turned off, and a series of read operations is completed.

According to this embodiment, a non-inverted signal amount of the memory cell is generated by using a ferroelectric capacitor having the same shape as the memory cell for the dummy cell, and a sense amplifier is formed by using a paraelectric capacitor having an established technology. The potential difference detected by is generated with high accuracy. For this reason, it is possible to accurately supply the reference potential that has high reliability against variations in the characteristics of the ferroelectric capacitors of the memory cells and can have a large allowable number of times of memory access with respect to a decrease in signal amount due to fatigue.

FIG. 4 shows the reference potential VREF of the first embodiment.
An example of a dummy cell other than the embodiment shown in FIG. In FIG. 4A, the non-inversion capacitance of the ferroelectric capacitor is CD. (VREF-VSS) / (VCC-VRE).
It is a 1Tr1C type dummy cell of F). If it has a capacitance, it can be replaced with a paraelectric capacitor. FIG.
(b) is a 1Tr1C type dummy cell having the same shape as the memory cell. However, when reading, the dummy cell plate line is set to (1 + CD / CFE0) × VREF-CD instead of VCC.
Drive to / CFE0 × VSS. Even if the dummy cell shown in FIG. 1 is replaced with the dummy cell shown in FIG. 4, there is an effect that a large number of allowable memory accesses can be taken against the decrease in the signal amount due to fatigue.

FIG. 5 is a second embodiment of the present invention showing a cell structure of a ferroelectric memory. In this embodiment as well, the same reference potential VREF as in the first embodiment is generated. The dummy cell has the same shape as the memory cell. The data line DLM _m is PCB ₁ ,
BLM _m memory cell side by the PCB ₂ (DLM _1m, BL
M _1m ) and the dummy cell side (DLM _2m , BLM _2m ). However, when the data line capacitance of the memory cell side DLM _1m and BLM _1m is CD ₁ and the data line capacitance of the dummy cell side DLM _2m and BLM _2m is CD ₂ , VREF = (CFE
₀ + CD ₂ ) VCC / (CFE ₀ + CD ₁ + CD ₂ ) is established. A VSS precharge circuit is attached to the data line on the memory cell side, and a VCC precharge circuit is attached to the data line on the dummy cell side.

FIG. 6 shows the read operation in FIG. An example of MC _{1 2m-1} cell selection is shown. During standby, PCA, PCB ₁ and PCB ₂ are on, and the data line is precharged to VSS with the memory cell side and the dummy cell side connected. When starting to read P
CB ₂ is turned off to separate the data line on the selected dummy cell side, and PCC ₂ is turned on to precharge BLM _2m to VCC. After that, PCC ₂ and PCA are turned off to float the data line, PCB ₂ is turned on, and the read operation is performed by the same procedure as in the first embodiment.

According to this embodiment, the same effect as the embodiment of FIGS. 1 to 3 is obtained. In addition, since a paraelectric capacitor is unnecessary, a highly integrated ferroelectric memory can be realized.

FIG. 7 is a third embodiment of the present invention showing a cell structure of a ferroelectric memory for reading by another reference potential generating method.
This is an embodiment of the present invention. The data lines are continuously connected by a sense amplifier. For example, during the data line DLM _x-1 and DLM _x, the sense amplifier between the DLM _x and DLM _{x + 1} are disposed one by one. Two dummy cells of the same shape as the first embodiment and two dummy cells of the same shape as the memory cells are alternately attached to each data line. For example, the data line DLM _x-1
, DLM _x is a dummy cell composed of a cell having the same shape as the memory cell and a cell having a paraelectric capacitor, DLM _{x + 1} ,
DLM _{x + 2} has a dummy cell of the same shape as the memory cell. The ferroelectric capacitor of the dummy cell is polarized in a direction in which polarization reversal does not occur during operation. Further, the data line is provided with a VSS precharge circuit which is controlled by PC _x or the like and which can simultaneously select three data lines. The sense amplifier includes a circuit that can selectively drive two of them by PCS _x or the like.

FIG. 8 shows the reference potential generated in the embodiment of FIG. At the time of reading, the potential generated on the data line is a non-inversion signal when the polarization of the ferroelectric capacitor of the memory cell is non-inversion, and the potential generated when the polarization is inverted is an inversion signal. The reference potential VREF ₁ is the reference potential VR of the first embodiment.
It has the same potential as EF. Another reference potential VREF ₂ has the same potential as the non-inverted signal amount. The sense amplifier amplifies the difference between the inverted signal and VREF ₂ and the difference between the non-inverted signal and VREF ₁ .

FIG. 9 shows the read operation in FIG. An example of MC _{2 x} cell selection is shown. During standby, all data lines are precharged to VSS. At the start of reading, PC _x is turned off and the three data lines DLM
Floating _x-1 , DLM _x , DLM _{x + 1} . At the same time, VW ₂ and VWD ₂ are turned on to select the memory cell MC _2x and the dummy cells DC _x-1 and DC _{x + 1} . Also, PCS _x
Is turned on and two sense amplifiers adjacent to DML _x are selected. Next, the plate lines VP _x , VPD _x-1 , V
When the PD _{x + 1} is driven from VSS to VCC, DLM _x-1 reference to the potential VREF _1, DLM inverted signal or a non-inverted signal potential in accordance with the polarization direction in the _x, DLM _{x + 1} reference to the potential VREF ₂ Occurs (see FIG. 8). After turning off VWD ₂ so that polarization inversion does not occur in the dummy cell, the sense amplifier is turned on to turn on DLM _x and DML _x-1 , DML.
The potential difference from _{x + 1} is amplified to VCC. At this time, the inverted signal potential of the memory cell is mainly amplified with VREF ₂ and the non-inverted signal potential is mainly amplified with VREF ₁ . Therefore, even if the ferroelectric capacitor of the memory cell fatigues and the inverted signal potential gradually decreases, the difference from the apparent non-inverted signal potential (which does not decrease even if fatigued) is VREF ₁
The polarization information of the memory cell can be read until it becomes −VREF ₂ or less. I / O by YS _x after amplification
The polarization information of the memory cell is read out on the line. After that, the driven plate lines VP _x , VPD _x-1 , and VPD _{x + 1} are returned to VSS and the original information is rewritten in the memory cell, and then the sense amplifier is turned off. PC _x is turned on to precharge the three data lines DLM _x-1 , DLM _x , DLM _{x + 1} to VSS again. At the same time, PCS _x is turned off and the sense amplifier is returned to the non-selected state. Finally, VWD ₂ is turned on to reset the voltage applied to the capacitor of the dummy cell to 0, and VW ₂ and VWD ₂ are turned off.

According to the present embodiment, even if the inversion signal gradually decreases due to the fatigue of the memory cell, reading is performed until the difference between the inversion signal amount and the non-inversion signal amount becomes the minimum potential difference that can be detected by the sense amplifier. Therefore, there is an effect that the sensitivity of the sense amplifier is effectively improved.

In all of the above-mentioned three embodiments, the system for driving the plate line to VCC for reading and writing has been described, but the system for fixing the plate line at VCC / 2 for reading and writing also generates the reference potential of the present invention. The law is valid.

[0025]

According to the present invention, it is possible to obtain a highly integrated nonvolatile ferroelectric memory having high reliability against fatigue of the ferroelectric film.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an array configuration using a reference potential generation dummy cell of the present invention.

FIG. 2 is a characteristic diagram of a reference potential according to the generation method of the present invention.

3 is a timing chart of a read operation in the array of FIG.

FIG. 4 is an explanatory diagram of an example of a dummy cell that generates the reference potential of FIG.

FIG. 5 is an explanatory diagram of an array structure of the present invention.

6 is a timing chart of a read operation in the array of FIG.

FIG. 7 is an explanatory diagram of an array configuration using a reference potential generation dummy cell of the present invention.

FIG. 8 is a characteristic diagram of a reference potential according to the generation method of the present invention.

9 is a timing chart of a read operation in the array of FIG.

FIG. 10 is an explanatory diagram of an array configuration using a conventional reference potential generating dummy cell.

[Explanation of symbols]

VREF ... Reference potential, DLM _m , BLM _m , DLM, DL
M _1m , DLM _2m , BLM _1m , BLM _2m , DLM, BL
M ... Data line, VW ₁ , VW ₂ , VW _2n-1 , VW _2n , VW
... Word lines of memory cells, VWD ₁ , VWD ₂ , VWD ...
Dummy cell word lines, VP ₁ , VP ₂ , VP _x-1 , V
P _x , VP _{x + 1} , VP _{x + 2} ... Plate line of memory cell, V
PD ₁ , VPD ₂ , VPD, VPDD, VPD _x-1 , VP
D _x , VPD _{x + 1} , VPD _{x + 2} ... Plate line of dummy cell.

Claims (6)

[Claims] 1. In a ferroelectric memory having a one-transistor, one-capacitor type memory cell structure, a memory cell for storing information and a reference potential for determining binary storage information of the memory cell are generated in a data line. A semiconductor non-volatile memory having a dummy cell, wherein the dummy cell includes a paraelectric capacitor and a ferroelectric capacitor having the same shape as the memory cell. 2. The reference potential output from the dummy cell to the data line according to claim 1, corresponds to binary storage information of the memory cell when the ferroelectric capacitor of the memory cell is in a state before fatigue. Then, it becomes lower than the intermediate potential of the two signal potentials output to the data line,
A semiconductor non-volatile memory in which the capacitance of a paraelectric capacitor of a dummy cell is set. 3. The semiconductor nonvolatile memory according to claim 1, wherein the paraelectric capacitor comprises a part of the data line. 4. A data line pair to which a memory cell for storing information and a first dummy cell having a ferroelectric capacitor of the same shape as the memory cell are attached, and a second data line pair according to claim 1 or 2. The data line pairs to which the dummy cells are attached are alternately arranged, and the differential type sense amplifier placed between all two adjacent data lines and the two adjacent differential type sense amplifiers can be selectively driven at the same time. 3 adjacent to the circuit
A semiconductor nonvolatile memory having a precharge circuit capable of simultaneously selecting two data lines. 5. A reference potential is generated from each of the first and second dummy cells on two data lines adjacent to a data line for outputting information of a memory cell at the time of reading, and these data lines are generated. The reference potential and the potential of the data line that outputs the information of the memory cell are compared by selectively driving two sense amplifiers connected to the data line that outputs the information of the memory cell, and the information of the memory cell is compared. Semiconductor non-volatile memory to judge. 6. A sense amplifier is used to control a word line attached to a dummy cell for outputting a reference potential before amplifying the potential difference to make a transistor included in the dummy cell non-conductive, and at the end of a series of read operations, the word line is connected. 5. The method of driving a semiconductor non-volatile memory according to claim 1, claim 3 or claim 4, wherein the voltage applied to the capacitor included in the dummy cell is set to 0 by controlling the transistor to make the transistor conductive.