JPH0864774A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor integrated circuit device, wherein an N-type field effect transistor and a P-type field effect transistor are separately controlled in threshold voltage through a single process. CONSTITUTION: An N-type transistor forming semiconductor layer which contains an electron supply layer 24 and a P-type transistor forming semiconductor layer which contains a hole supply layer 28 are laminated on a substrate 21, the P-type transistor forming semiconductor layer located on an N-type transistor forming predetermined region is selectively removed so as to form a resist film 35 provided with an opening 35P located at the gate electrode forming predetermined part of a P-type transistor and an opening 35N located at the gate electrode forming predetermined part of an N-type transistor. Two etching operations are carried out almost simultaneously for controlling a P-type transistor and an N-type transistor in threshold voltage separately using a dilute mixed solution composed of hydrofluoric acid and hydrogen peroxide and another dilute mixed solution composed of citric acid water solution and hydrogen peroxide without replacing the resist film 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention manufactures a semiconductor integrated circuit device in which an n-type field effect transistor (hereinafter, n-type FET) and a p-type field effect transistor (hereinafter, p-type FET) are formed on the same semiconductor substrate. A suitable method for doing so.

Currently, semiconductor integrated circuit devices are being advanced in speed and power consumption, and even in the case of using a compound semiconductor, realization of a complementary circuit is desired.

[0003]

2. Description of the Related Art Conventionally, complementary circuits have been formed by applying ion implantation technology on a flat wafer.
Type FET and p type FET, or n type F
A two-stage structure in which a semiconductor layer for ET and a semiconductor layer for p-type FET are independently epitaxially grown is implemented.

[0004]

In a method for forming an n-type FET and a p-type FET by applying an ion implantation technique, an ohmic contact region is formed by a self-alignment method in which ions are implanted using a gate as a mask. However, since the impurities diffuse in the gate direction during the heat treatment process of 800 [° C.] to 900 [° C.] for activating the implanted impurities, the short channel FET is well controlled. Is difficult to form.

Further, a semiconductor layer for an n-type FET and a p-type FE
In the case of the two-stage structure in which the semiconductor layer for T is independently epitaxially grown, it is possible to control the two threshold voltages independently, but the gate electrode forming process, especially the threshold voltage is adjusted. The process for this is required twice for n-type and p-type.

According to the present invention, although the threshold voltages of the n-type field effect transistor and the p-type field effect transistor can be independently controlled, they are realized by a single gate electrode forming process. It can be so.

[0007]

FIG. 1 is a side sectional view showing a semiconductor integrated circuit device forming a complementary circuit at a process step for explaining the principle of the present invention.

In the figure, 1 is a substrate, 2 is a buffer layer,
3 is a channel layer, 4 is a carrier supply layer (ie, a gate electrode contact layer), 5 is a cap layer, 6 is a source, 7 is a drain, 8 is a buffer layer, 9 is a channel layer, and 10 is a carrier supply layer (ie, Gate electrode contact layer), 11
Is a cap layer, 12 is a source, 13 is a drain, 14 is an element isolation region, 15 is a resist film, 4A is a gate recess, 10A is a gate recess, and 16 and 17 are gate electrodes, respectively.

In the illustrated semiconductor integrated circuit device, the element isolation region 14 is interposed between the n-type transistor portion on the right side and the p-type transistor portion on the left side.

Immediately below the gate electrode 16 in the p-type transistor portion, a carrier supply layer 1 made of a certain material A is provided.
0 exists, and the carrier supply layer 4 made of a certain material B exists just below the gate electrode 17 in the n-type transistor portion.

In order to manufacture the gate portion in the semiconductor integrated circuit device shown in the figure, a resist film 15 having an opening for forming a gate electrode is formed, and first, the cap layer 11 and the material A are formed.
A part of the carrier supply layer 10 made of is selectively etched, the current flowing between the source 12 and the drain 13 is measured, and the gate recess 10A is formed to control the threshold voltage of the p-type transistor portion. .

Next, the cap layer 5 and a part of the carrier supply layer 4 made of the material B are selectively etched to form a gate recess 4A while measuring the current flowing between the source 6 and the drain 7. Controls the threshold voltage of the n-type transistor portion.

After that, the gate electrode 16 in the p-type transistor portion and the gate electrode 17 in the n-type transistor portion are formed and completed.

As is apparent from the above description, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, (1) one conductivity type transistor portion (eg, n-type transistor) is formed on the same substrate (eg, substrate 21). Required semiconductor layers (for example, buffer layer 22, channel layer 23, electron supply layer 24, cap layer 25, etc.) for one-conductivity-type transistor partial configuration including gate electrode contact layer (for example, electron supply layer 24) and opposite conductivity. Required semiconductor layers (for example, buffer layer 26) for forming a transistor portion of the opposite conductivity type including the gate electrode contact layer (for example, hole supply layer 28) of the n-type transistor portion (for example, p-type transistor portion).
Channel layer 27, hole supply layer 28, cap layer 29, etc.), and then removing the required semiconductor layer for the opposite conductivity type transistor partial configuration on the one conductivity type transistor partial formation planned region. Selectively exposing the surface of the required semiconductor layer for forming the one conductivity type transistor portion, and then forming an opening (for example, the opening 3) in the gate electrode formation planned portion of the opposite conductivity type transistor portion.
5P) and forming a resist film (for example, a resist film 35) having an opening (for example, an opening 35N) in a portion where a gate electrode is to be formed in the one conductivity type transistor portion, and then, a gate for the opposite conductivity type transistor portion. An etchant having a high etching rate with respect to the electrode contact layer and a low etching rate with respect to the gate electrode contact layer of the transistor portion of the one conductivity type (for example, a dilute aqueous solution in which hydrofluoric acid and hydrogen peroxide solution are mixed) and the one conductivity type An etchant having a high etching rate with respect to the gate electrode contact layer of the transistor portion and a low etching rate with respect to the gate electrode contact layer of the opposite conductivity type transistor portion (for example, a dilute aqueous solution obtained by mixing an aqueous solution of citric acid and hydrogen peroxide solution) is used. This Replacing the resist film as a mask with etching of each gate electrode contact layer for selectively controlling the threshold voltage of the opposite conductivity type transistor portion and controlling the threshold voltage of the one conductivity type transistor portion. Characterized in that it includes the steps to be carried out one after the other, or,

(2) In (1) above, the material forming the gate electrode contact layer in the one conductivity type transistor portion is Al _x Ga _{1 -x} As (x ≦ 0.5) and the material has opposite conductivity. The material forming the gate electrode contact layer in the _p- type transistor portion is Al _x Ga _1-x As (x ≧
0.75) and Al _x Ga _1-x As (x ≦ 0.
The etching solution for 5) is a mixed solution of hydrofluoric acid and hydrogen peroxide, and Al _x Ga _1-x As (x ≧ 0.
The etching solution for 75) is a mixed solution of an aqueous citric acid solution and a hydrogen peroxide solution.

[0016]

By adopting the above means, the threshold voltage of the p-type transistor portion and the threshold voltage of the n-type transistor portion can be controlled independently, but the gate formation process is Therefore, the complementary circuit can be manufactured in a simple and short process.

[0017]

2 and 3 are cross-sectional side views showing essential parts of a semiconductor integrated circuit device (complementary circuit) at a process key point for explaining the process of one embodiment of the present invention. Will be described with reference to FIG.

See FIG. 2A. 2 (A) -1 Molecular beam epitaxial growth (molecular be)
substrate 2 by applying the am epitaxy (MBE) method.
A buffer layer 22, a channel layer 23, an electron supply layer (gate electrode contact layer) 24, a cap layer 25, a buffer layer 26, a channel layer 27, a hole supply layer (gate electrode contact layer) 28, and a cap layer 29 are formed on the first layer. Form.

The buffer layer 22, the channel layer 23, the electron supply layer 24, and the cap layer 25 are constituent elements for forming the n-type transistor portion, and the buffer layer 26, the channel layer 27, the hole supply layer 28, The cap layer 29 is a component for forming the p-type transistor portion.

Here, the main data regarding each part are as follows. Substrate 21 Material: Semi-insulating GaAs buffer layer 22 Material: Undoped GaAs Thickness: 2000 [Å] Channel layer 23 Material: Undoped InGaAs Thickness: 140 [Å] Electron supply layer 24 Material: n-Al _x Ga _1-x As x value: 0.5 Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 400 [Å]

In this case, the reason why the x value is set to 0.5 is that it is a value that properly operates as an electron supply layer and exhibits an appropriate effect on etching.

About cap layer 25 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 500 [Å] Buffer layer 26 Material: Undoped GaAs Thickness: 2000 [Å] Channel layer 27 Material: undoped InGaAs Thickness: 140 [Å] Regarding hole supply layer 28 Material: p-Al _x Ga _1-x As x value: 0.75 Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ] Thickness: 300 〔Å〕

In this case, the reason for setting the x value to 0.75 is that it is a value that properly operates as a hole supply layer and exhibits an appropriate effect on etching.

Cap layer 29 Material: p-GaAs Impurity concentration: 2 × 10 ¹⁹ [cm ⁻³ ] Thickness: 500 [Å]

By applying the 2 (A) -2 ion implantation method, oxygen ions are implanted at the boundary between the p-type transistor portion and the n-type transistor portion and in the vicinity thereof to form the element isolation region 30.

2 (A) -3 Resist Process in Lithography Technology, and
By applying the wet etching method, the cap layer 29 in the n-type transistor portion, the hole supply layer 2
8, the channel layer 27 and the buffer layer 26 are removed to expose the cap layer 25.

2 (A) -4 By applying the resist process in the lithography technique, the vacuum deposition method, and the lift-off method twice, the source electrode 31 and the drain in the n-type transistor portion are applied. The electrode 32 and the source electrode 33 and the drain electrode 34 in the p-type transistor portion are formed.

The source electrode 31 and the drain electrode 32 in the n-type transistor portion are made of AuGe / Au, and the source electrode 33 and the drain electrode 34 in the p-type transistor portion are made of AuZn / Au.

See FIG. 2B. 2 (B) -1 By applying a resist process in the lithography technique, a gate electrode formation planned part in the n-type transistor part and a p-type transistor part are applied. A resist film 35 having an opening 35N and an opening 35P is formed in the portion where the gate electrode is to be formed.

2 (B) -2 Dilute aqueous solution (H
F: H ₂ O ₂ : H ₂ O = 5: 84: 26350) is used to apply a wet etching method to form a cap layer in the opening 35P in the p-type transistor portion. 29 and the hole supply layer 28 are etched to control the threshold voltage of the p-type transistor portion.

In this case, the etching rate of GaAs is about 180 [Å / min], and Al _x Ga _1-x As (x =
The etching rate of 0.5) is about 240 [Å / min], Al
_Since the etching rate of _x Ga _1-x As (x = 0.75) is about 420 [Å / min], at this time, the cap layer exposed in the opening 35N in the n-type transistor portion is exposed. 25 is etched in the same manner as the cap layer 29, but the electron supply layer 24 is slightly etched until the threshold voltage control of the p-type transistor portion is completed.

See FIG. 3A. 3 (A) -1 Dilute aqueous solution obtained by mixing an aqueous solution of citric acid and hydrogen peroxide (citric acid (50%): H ₂ O ₂ : H ₂ O = 5: 1:
By applying the wet etching method using 6) as an etchant, the electron supply layer 24 exposed in the opening 35N in the n-type transistor portion is etched to obtain the threshold value of the n-type transistor portion. Performs voltage control.

In this case, the etching rate of GaAs is about 1800 [Å / min], and Al _x Ga _1-x As (x =
The etching rate of 0.5) is about 1350 [Å / min], A
Since the etching rate of l _x Ga _1-x As (x = 0.75) is about 0 [Å / min], at this time, it is expressed in the opening 35P in the p-type transistor portion. The hole supply layer 28 is hardly etched until the threshold voltage control of the n-type transistor portion is completed. Therefore, the threshold voltage of the p-type transistor portion does not change, and only the threshold voltage of the n-type transistor portion changes.

See FIG. 3B. 3 (B) -1 By applying the vacuum deposition method and the lift-off method while leaving the resist film 35 used as the etching mask for controlling the threshold voltage, For example, the gate electrode 36 of the n-type transistor portion and the gate electrode 37 of the p-type transistor portion made of Al are formed.

In the present invention, it is important to use, as an etching solution for Al _x Ga _1-x As, a diluted aqueous solution obtained by mixing an aqueous solution of citric acid and an aqueous solution of hydrogen peroxide whose etching rate changes depending on the x value. From here,
The characteristics will be described.

FIG. 4 shows citric acid (50%): H ₂ O ₂ : H
It is a diagram for explaining the etching characteristics of ₂ O = 5: 1: 6, and the x value in Al _x Ga _1-x As is plotted on the horizontal axis.
The vertical axis represents the etching rate [Å / min].

From the figure, when x = 0.5, the etching rate is about 1350 [Å / min], and x =
At 0.75, it is observed that the etching rate is about 0 [Å / min].

The present invention is not limited to the above embodiment, and many modifications can be realized without departing from the constituent features of the invention described in the claims.

For example, in the above embodiment, n-Al _{x is} used as the material of the electron supply layer 24 in the n-type transistor portion.
Ga _1-x As (x = 0.5) was used.
It may be replaced with l _x Ga _1-x As (x = 0.3).

In this case, of course, it is necessary to change the etching solution for controlling the threshold voltage of the n-type transistor portion. For example, an aqueous solution of citric acid solution and hydrogen peroxide solution (citric acid solution) is mixed. (50%): H ₂ O ₂ = 1
5: 1) is used.

In this case, the etching rate of GaAs is about 1500 [Å / min], and Al _x Ga _1-x As (x =
The etching rate of 0.3) is about 1200 [Å / min], A
Since the etching rate of l _x Ga _1-x As (x = 0.75) is about 0 [Å / min], at this time, it is expressed in the opening 35P in the p-type transistor portion. The hole supply layer 28 is hardly etched until the threshold voltage control of the n-type transistor portion is completed. Therefore, the threshold voltage of the p-type transistor portion does not change, and only the threshold voltage of the n-type transistor portion changes.

Further, the semiconductor layer with which the gate electrode 36 or 37 contacts may be undoped.

[0043]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a required semiconductor layer for forming one conductivity type transistor portion including a gate electrode contact layer of one conductivity type transistor portion on the same substrate and the opposite. A required semiconductor layer for the opposite conductivity type transistor partial structure including a gate electrode contact layer of the conductivity type transistor part is laminated and formed, and a required semiconductor layer for the opposite conductivity type transistor partial structure is present on one conductivity type transistor part formation planned region. To selectively expose the surface of the required semiconductor layer for forming the one-conductivity-type transistor portion, and to provide an opening in the gate-electrode formation-scheduled portion of the opposite-conductivity-type transistor portion and the gate-electrode-formation portion of the one-conduction-type transistor portion. Form a resist film with an opening in the gate electrode contact layer of the transistor of opposite conductivity type Etchant having a high etching rate and a low etching rate for the gate electrode contact layer of the one conductivity type transistor portion, and a high etching rate for the gate electrode contact layer of the one conductivity type transistor portion and a gate electrode of the opposite conductivity type transistor portion Etching of each gate electrode contact layer for controlling the threshold voltage of the transistor of opposite conductivity type and the threshold voltage of the transistor of one conductivity type is masked by separately using etchants having low etching rates for the contact layer. It is carried out one after another without changing the resist film.

By adopting the above structure, the threshold voltage of the p-type transistor portion and the threshold voltage of the n-type transistor portion can be controlled independently, but the gate formation process is Therefore, the complementary circuit can be manufactured in a simple and short process.

[Brief description of drawings]

FIG. 1 is a fragmentary side view showing a semiconductor integrated circuit device forming a complementary circuit in a process key point for explaining the principle of the present invention.

FIG. 2 is a side sectional view showing an essential part of a semiconductor integrated circuit device at a process key point for explaining the process of one embodiment of the present invention.

FIG. 3 is a side sectional view showing an essential part of a semiconductor integrated circuit device at a process key point for explaining a process of an embodiment of the present invention.

FIG. 4: Citric acid (50%): H ₂ O ₂ : H ₂ O = 5:
It is a diagram for explaining the etching characteristics of 1: 6.

[Explanation of symbols]

 21 substrate 22 buffer layer 23 channel layer 24 electron supply layer (gate electrode contact layer) 25 cap layer 26 buffer layer 27 channel layer 28 hole supply layer (gate electrode contact layer) 29 cap layer 30 element isolation region 31 source electrode 32 Drain electrode 33 Source electrode 34 Drain electrode 35 Resist film 35N Opening 35P Opening 36 Gate electrode 37 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/812

Claims (2)

[Claims] 1. A required semiconductor layer for forming a transistor portion of one conductivity type including a gate electrode contact layer of a transistor portion of one conductivity type on the same substrate, and a transistor portion of an opposite conductivity type including a gate electrode contact layer of a transistor portion of the opposite conductivity type. A step of laminating and forming a required semiconductor layer for a structure, and then removing the required semiconductor layer for a transistor part configuration of the opposite conductivity type existing on the one conductivity type transistor part formation scheduled region, Selectively exposing the surface of the required semiconductor layer for use in forming a gate electrode formation portion of the opposite conductivity type transistor portion and an opening in the gate electrode formation portion of the one conductivity type transistor portion. A step of forming a resist film, and then a gate of the opposite conductivity type transistor portion An etchant having a high etching rate for the polar contact layer and a low etching rate for the gate electrode contact layer of the one conductivity type transistor portion, and a high etching rate for the gate electrode contact layer of the one conductivity type transistor portion and the opposite conductivity type For controlling the threshold voltage of the opposite conductivity type transistor portion and the threshold voltage of the one conductivity type transistor portion by selectively using etchants having a low etching rate for the gate electrode contact layer of the type transistor portion. And a step of successively performing etching of each gate electrode contact layer without changing the resist film as a mask, the manufacturing method of the semiconductor integrated circuit device. 2. The material forming the gate electrode contact layer in the one-conductivity-type transistor portion is Al _x Ga _{1 -x} As.
(X ≦ 0.5) and the material forming the gate electrode contact layer in the transistor portion of opposite conductivity type is A
l _x Ga _1-x As (x ≧ 0.75) and Al _x
The etching solution for Ga _1-x As (x ≦ 0.5) is a mixed solution of hydrofluoric acid and hydrogen peroxide water, and Al
_{2. The} method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the etching solution for _x Ga _1-x As (x ≧ 0.75) is a mixed solution of citric acid aqueous solution and hydrogen peroxide solution.