JPH08335396A - Non-voltage semiconductor memory - Google Patents

Abstract

PURPOSE: To shorten a writing time for data by injecting electrons into a floating gate of a memory cell with channel hot electrons. CONSTITUTION: Before data is written in a memory array 1, data is successively read out of an external memory circuit 3, the total number of memory cells to which data is to be written is counted by a counter circuit 4. Information whether data writing in the memory array 1 is performed while holding the phase or reversing the phase is sent to a data control circuit 5 depending on this counted result. Data is transferred to a read-out/write-in circuit 2 from the circuit 5, and successively written in the prescribed memory cell in the memory array 1. Finally, phase information from the circuit 4 is sent to the circuit 2, and written in a phase information recording section 1a.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electrically programmable non-volatile memory, such as UV erase EPROMs,
The present invention relates to a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art As an electrically programmable semiconductor non-volatile memory device, an ultraviolet erasable EPROM or flash in which data is written by injecting electrons from a drain side into a floating gate by channel hot electrons (CHE) A semiconductor nonvolatile memory device having a NOR type structure such as an EEPROM is known.

The write operation of the NOR type semiconductor nonvolatile memory device will be briefly described below with reference to FIG.

In FIG. 8, WL_m-1, WL_m, WL
_{m + 1}Is the word line, BL_n-1, BL_n, BL_{n + 1}Is a bit
Line, SRL is common source line, MT_{m-1, n-1}, M
T_{m-1, n}, MT _{m-1, n + 1}, MT_{m, n-1}, MT_{m, n}, MT
_{m, n + 1}, MT_{m + 1, n-1}, MT_{m + 1, n}, MT_{m + 1, n + 1}Hame
The molycells are shown respectively.

The write example of FIG. 8 shows a case where data is written in the memory cell MT _{m, n} . In this case, 12 V is applied to the selected word line WL _m , 7 V is applied to the selected bit line BL _n , and the other word lines WL
0V is applied to _m-1 , WL _{m + 1} , bit lines BL _n-1 , BL _{n + 1} and common source line SRL. As a result, electrons are injected into the floating gate by channel hot electrons (CHE) only in the selected memory cell MT _{m, n} , and the threshold voltage V _th becomes 5 V or higher.

Here, in the case of a NOR type semiconductor nonvolatile memory device, electrons are injected into the floating gate by channel hot electrons, and when the threshold voltage V _th is 5 V or more, the first data (hereinafter referred to as data 1). 2) state and there is no electron in the floating gate and the threshold voltage V _th is about 1.5 V, the second data (hereinafter data 0) state is set.

[0007]

By the way, the above-mentioned N
A problem in the write operation of the OR type semiconductor nonvolatile memory device is that it takes a long time to write data by channel hot electrons.

For example, in the standard write operation example shown in FIG. 8, the time required for writing is about 10 μsec.

Moreover, the data writing by the channel hot electrons is about 5 per memory cell.
Since it is necessary to pass a channel current of as much as 00 μA between the drain and the source, generally when writing data by channel hot electrons, data writing is performed every 1 bit, or at most every 4 to 8 bits. Is common.

Therefore, for example, when writing data to a NOR type semiconductor non-volatile memory device having a memory cell of 4 Mbits, when writing data at the maximum by 1 bit, it takes about 40 seconds, and writing data at every 4 bits. The data writing requires about 10 seconds for writing, and about 5 seconds for writing data every 8 bits.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor nonvolatile memory device capable of shortening the data writing time and capable of writing data in a short time. It is in.

[0012]

In order to achieve the above object, the semiconductor nonvolatile memory device of the present invention controls the amount of charges accumulated in the charge accumulation portion of a memory cell,
A semiconductor nonvolatile memory device in which either first data or second data having opposite phases is electrically written, and the first data or the second data written in the entire memory array at the time of data writing. Circuit for counting the total number of data of the data, a writing circuit for writing data by inverting or inverting the phase of the data at the time of data writing based on the result of the counting circuit, and writing data by the writing circuit. And a recording unit that records the phase information that has been obtained.

Further, according to the present invention, by controlling the amount of electric charge accumulated in the electric charge accumulating portion of the memory cell, either the first data or the second data of opposite phases is electrically written. In the semiconductor nonvolatile memory device, a memory array is divided into a plurality of blocks, a recording unit for recording phase information at the time of writing the data is provided for each block, and the memory block is provided at the time of writing the data. A counting circuit that counts the total number of the first data or the second data that is written every time, and the data is written by inverting or inverting the phase of the data when writing the data based on the result of the counting circuit. And a writing circuit.

According to the present invention, the write circuit is
When the total number of memory cells to which the first data is written is less than half of the memory cells to be written, the data is written while the phase of the data at the time of writing is held in the normal state, and the first data is When the total number of memory cells to be written is more than half of the memory cells to be written, the phase of the data at the time of writing is inverted to write the data.

Further, according to the present invention, when reading data,
The circuit has a circuit for reading data from the addressed memory cell, reading phase information at the time of writing to the memory cell recorded in the recording section, and determining the content of the read data based on the phase information.

Furthermore, in the present invention, the recording section is provided in the memory array area.

[0017]

According to the semiconductor nonvolatile memory device of the present invention, for example, a semiconductor having a NOR type structure in which the first data is written by injecting electrons into the floating gate of the memory cell by channel hot electrocroton. In the nonvolatile memory device, when the total number of memory cells to which the first data is written is counted by the counting circuit in the entire memory array and the counting result is less than half of all the memory cells, when writing by the writing circuit The data is written while the phase of the data is held in the normal state. Further, when the total number of memory cells to which the first data is written is more than half of all the memory cells, the phase of the data at the time of writing is inverted to write the data and the phase at the time of writing the data. Information is recorded in the recording unit.

When the memory array area is divided into a plurality of memory blocks, phase information is also set for each block when writing data, and data writing is performed.

As a result, the total number of memory cells into which electrons are to be injected into the floating gates of the memory cells by channel hot electrons is less than half of all the memory cells, and the time required for writing data at the maximum is reduced to, for example, half. it can.

When reading data, the data is read from the addressed memory cell, and
The phase information at the time of writing to the memory cell recorded in the recording unit is read, and the content of the read data is determined based on the phase information.

[0021]

FIG. 1 is a block diagram showing an embodiment of a semiconductor nonvolatile recording device according to the present invention, specifically, a NOR type semiconductor nonvolatile memory device in which data is written by channel hot electrons.

In FIG. 1, 1 is a memory array, 1a is a phase information recording section of the memory array provided in the memory array 1, 2 is a read / write circuit of the memory array 1 including a sense amplifier, and 3 is An external data storage circuit 4 in which data to be rewritten is stored in the memory array 1 is a counter circuit, and 5 is a data control circuit. Further, D1 to D7 in the figure show the flow of data. The external data storage circuit is, for example, a DRA.
Semiconductor memory such as M, SRAM, or magnetic tape,
It is composed of a storage device such as a magnetic disk or an optical disk.

The counter circuit 4 includes the external data storage circuit 3
The data is sequentially read from the
Count the total number of data. The counting result is stored in the register of the most significant bit MSB to the least significant bit LSB in the counter circuit 4. The data control circuit 5 sequentially reads out the data from the external data storage circuit 3 based on the counting result of the counting circuit 4, and holds the phase of the data in the normal state or inverts the phase of the data. Output.

Next, referring to the block diagram of FIG.
The data write operation of the NOR type semiconductor nonvolatile memory device in the present invention will be described step by step.

First, before the data write operation to the memory array 1, the data flow D by the counter circuit 4 is performed.
3, the data is sequentially read from the external data storage circuit 3, and one of the read data is the total number of data,
That is, the total number of memory cells in which data writing by channel hot electrons should be performed in the normal phase rotation state is counted.

The counting result is stored in the register in the counter circuit 4, and when the most significant bit MSB of the register is in the state of logic 1, it is judged that the total number of 1 data is more than half of all the memory cells. , When the most significant bit MSB is in the logic 0 state, it is determined that the total number of 1 data is less than half of all the memory cells.

Next, based on the above judgment result, whether the data write operation to the memory array 1 should be performed while holding the phase forward rotation state, or whether the data should be written by inverting the phase. Information is sent from the counter circuit 4 to the data control circuit 5 along the data stream D4.

Next, in the data control circuit 5, the data is sequentially read again from the external data storage circuit 3 along the data flow D5, and the read data is rotated normally or based on the phase information. Flipped. Subsequently, the data is transferred from the data control circuit 5 to the read / write circuit 2 along the data flow D6, and the data is sequentially written into appropriate memory cells in the memory array 1 along the data flow D2. Be done.

Finally, the phase information from the counter circuit 4 is sent to the read / write circuit 2 along the data flow D7, and further to the phase information recording section 1a along the data flow D2. Information is written.

As a result of the above-described write operation, the total number of memory cells into which electrons are to be injected into the floating gate by channel hot electrons is always less than half of all the memory cells, and the time required for data writing at the maximum is halved. Can be shortened.

FIG. 2 shows the threshold voltage V _th in the normal memory cell in the memory array 1 and the phase memory cell of the phase information recording section 1a and the phase relationship when data is written in the memory array 1. It is a figure.

As shown in FIG. 2, when the phase is normal, it is in phase with a normal NOR type semiconductor non-volatile memory device, the threshold voltage V _th of the normal memory cell is 5 V or more, and the data "1". , The threshold voltage V _th is about 1.5 V, the data is “0”, and the threshold voltage V in the phase memory cell is
_th is set to 5 V or more.

On the other hand, when the phase is inverted, the phase is opposite to that of the normal NOR type semiconductor non-volatile memory device, the threshold voltage V _th of the normal memory cell is about 1.5 V, and the data "1". ", The threshold voltage V _th is 5 V or more, the data is" 0 ", and the threshold voltage V _th in the phase memory cell is set to about 1.5 V.

Further, in the case of reading the data of the regular memory cell in the memory array 1, at the time of reading the data, the data is read from the addressed memory cell and the memory cell recorded in the phase information recording section 1a. It is possible to discriminate the data by simultaneously reading the phase information at the time of writing to, and determining the content of the read data based on the phase information.

FIG. 3 is a diagram showing the relationship between the threshold voltage V _th of the normal memory cell in the memory array 1 and the phase memory cell of the phase information recording section 1a and the data judgment in the normal memory cell.

As shown in FIG. 3, by the threshold voltage V _th of the normal memory cell is more than 5V, when the threshold voltage V _th in the phase memory cell is set to 5V or more is
In the normal state, the data in the normal memory cell is determined to be "1". By the threshold voltage V _th is about 1.5V in the normal memory cell, the threshold voltage V _th in the phase memory cell
Is set to 5 V or more, it is in the normal rotation state, and the data of the normal memory cell is determined to be “0”. By the threshold voltage V _th of the normal memory cell is more than 5V, when the threshold voltage V _th in the phase memory cell is set to about 1.5, an inverted state, the data of normal memory cells Is determined to be "0". By the threshold voltage V _th is about 1.5V in the normal memory cell, when the threshold voltage V _th in the phase memory cell is set to approximately 1.5V is a reversed state, the normal memory cell Is determined to be "1".

4 (a) and 4 (b) show the case where the phase information recording section 1a is provided inside the memory array 1.
It is a figure which shows the specific example of a kind.

FIG. 4A shows a case where the phase information recording section 1a provided in the memory array 1 is a memory cell connected to a normal one word line in the memory array 1. FIG.
In (a), WL1 to WLN are normal word lines and BL
1 to BLM are bit lines, and WLn is one word line for the phase information recording unit 1a normally provided in the word line.
Also, ○ is a memory cell used as a normal memory cell, ●
Represents a memory cell used as a phase information recording unit. Basically, one memory cell used in the phase information recording unit is sufficient in the memory array 1. Therefore, information such as a file name and rewriting date / time may be recorded in other memory cells.

FIG. 4B shows a case where the phase information recording section 1a provided in the memory array area is a memory cell connected to one word line provided auxiliary to the memory array. In FIG. 4B, WL1 to WLN are normal word lines, BL1 to BLM are bit lines, and WLC is an auxiliary word line provided outside the normal word line for the phase information recording unit. Further, ◯ indicates a memory cell used as a normal memory cell, and ● indicates a memory cell used as a phase information recording unit. The memory cell used as the phase information recording unit is
Basically, one memory cell in the memory array 1 is sufficient, so that information such as a file name and rewriting date / time may be recorded in other memory cells.

4 (a) and 4 (b) are two specific examples of the case where the phase information recording portion is provided in the area of the memory array 1, but the present invention is not limited to these. Needless to say, it extends to various other aspects.

In the above-described embodiment, data is mainly written in all the memory cells in the memory array 1, and the phase information at the time of writing the data is also determined in the memory array 1. In the above application, the unit for writing the data or determining the phase information at the time of writing the data may be performed for each word line sector or each block obtained by dividing the region of the memory array 1 into a plurality of regions.

By writing data or determining phase information at the time of writing data for each word line sector or each block obtained by dividing the area of the memory array 1 into a plurality of areas, a data writing unit such as page writing is divided. Is preferred.

FIG. 5 shows a case in which the phase information recording section 1a for each word line sector provided in the memory array 1 is a memory cell connected to a 1-bit line provided auxiliary to each memory array. Is. In FIG. 5, WL1
~ WLN is a normal word line, BL1 to BLM are bit lines,
BLC is an auxiliary bit line for the phase information recording unit which is usually provided outside the bit line. Further, ◯ indicates a memory cell used as a normal memory cell, and ● indicates a memory cell used as a phase information recording unit.

FIG. 5 shows a specific example of the case where the phase information recording section is provided for each word line sector in the area of the memory array 1, but the present invention is not limited to this and various other types are provided. It goes without saying that it extends to the embodiments.

FIG. 6 shows a case where the area of the memory array 1 is divided into a plurality of memory blocks. Figure 6
, The memory array 1 is MBLK11, MBLK
It is divided into four blocks of 12, MBLK21 and MBLK22. Also, in the figure, WL11 to WL1N, WL2
1 to WL2N are word lines, BL11 to BL1M, BL2
1 to BL2M indicate bit lines.

In FIG. 7, the memory array area of FIG. 6 is divided into a plurality of memory blocks, and the phase information recording section 1a is formed in a part of each memory block, specifically, a part of the memory block MBLK12. It is a figure which shows the specific example at the time of providing.

In FIG. 7, the memory block MBLK
This is a case where the phase information recording unit 1a provided in 12 is a memory cell connected to a normal 1 word line in the memory block MBLK12. In FIG. 7, WL11 to W
L1N is a normal word line, BL21 to BL2M are normal bit lines, and WL1n is a word line for the phase information recording section provided in the normal word line. Further, ◯ indicates a memory cell used as a normal memory cell, and ● indicates a memory cell used as a phase information recording unit. Phase information recording unit 1
The memory cell used as a is basically 1 in each block.
Since the number is sufficient, the file name of the block and information at the time of rewriting may be recorded in other memory cells.

FIG. 7 shows a specific example of the case where the phase information recording section is provided in the memory cell connected to the normal one word line in each memory block array area, but the present invention is not limited to this. Needless to say, it extends to various other aspects.

As described above, according to this embodiment,
The total number of memory cells into which electrons are to be injected into the floating gate is less than half of all the memory cells by the channel hot elecroton, and the time required for data writing at the maximum can be reduced to half.

[0050]

As described above, according to the semiconductor nonvolatile memory device of the present invention, the data writing time can be shortened and the data can be written in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a NOR type semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is a diagram showing a relationship between a threshold voltage V _th in a normal memory cell and a phase memory cell and a phase when data writing is performed.

FIG. 3 is a diagram showing a relationship between threshold voltage V _th in a normal memory cell and a phase memory cell and data determination in a normal memory cell.

FIG. 4 is a diagram showing two specific examples in the case of providing a phase information recording unit inside a memory array.

FIG. 5 is a diagram showing a specific example in the case where the phase information recording section for each word line sector in the memory array is provided in the memory cell connected to the 1-bit line auxiliary provided in the memory array. .

FIG. 6 is a diagram showing an example in which the memory array area is divided into a plurality of blocks.

FIG. 7 is a diagram showing a specific example in which a phase information recording unit is provided in each memory block when the memory array area is divided into a plurality of blocks.

FIG. 8 is a diagram showing a bias at the time of writing in a NOR type semiconductor nonvolatile memory device.

[Explanation of symbols]

1 ... memory array 1a ... phase information recording unit 2 ... read / write circuit 3 ... external data storage circuit 4 ... counter circuit 5 ... data control circuit _{WL m-1, WL m,} WL m + 1 ... word - word line BL _{n −1} , BL _n , BL _{n + 1} ... Bit line SRL ... Common source line MT _{m-1, n-1} , MT _{m-1, n} , MT _{m-1, n + 1} , M
T _{m, n-1} , MT _{m, n} , MT _{m, n + 1} , MT _{m + 1, n-1} , MT
_{m + 1, n} , MT _{m + 1, n + 1} ... Memory cells MBLK11, MBLK12, MBLK21, MBLK
22 ... Memory block

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory in which either the first data or the second data having mutually opposite phases is electrically written by controlling the amount of charge stored in the charge storage portion of the memory cell. A storage device, which counts the total number of first data or second data written to the entire memory array when writing data, and the phase of the data when writing data based on the result of the counting circuit. A semiconductor non-volatile memory device having a write circuit for writing data by reversing or reversing the data, and a recording section for recording phase information in which the data is written by the write circuit. 2. A non-volatile semiconductor in which either the first data or the second data of opposite phases is electrically written by controlling the amount of charge accumulated in the charge accumulating portion of the memory cell. A storage device, in which a memory array is divided into a plurality of blocks, a recording unit for recording the phase information at the time of writing the data is provided for each block, and is written for each memory block at the time of writing data. A counting circuit for counting the total number of the first data or the second data and a writing circuit for writing the data by inverting or inverting the phase of the data at the time of writing the data based on the result of the counting circuit. A semiconductor nonvolatile memory device having. 3. The write circuit, wherein when the total number of memory cells to which the first data is written is less than half of the memory cells to be written, the write circuit retains the phase of the data at the time of writing and stores the data in the normal state. 2. The semiconductor nonvolatile according to claim 1, wherein writing is performed, and when the total number of memory cells to which the first data is written is more than half of the memory cells to be written, the phase of the data at the time of writing is inverted to write the data. Sex memory device. 4. When reading data, the data is read from the addressed memory cell, the phase information at the time of writing to the memory cell recorded in the recording section is read, and the read data is read based on the phase information. The semiconductor nonvolatile memory device according to claim 1, further comprising a circuit for determining the contents of 5. The semiconductor nonvolatile memory device according to claim 1, wherein the recording section is provided in the memory array area.