JPH08190622A - Method and device for image processing - Google Patents

Abstract

PURPOSE: To enable an image processing device able to fast transfer image and improve the use efficiency of a bus by mounting a palette converting circuit for converting a logical palette number into a hardware palette number in an image generating circuit. CONSTITUTION: The logical palette conversion part 120 in the image generating circuit 100 performs a logical palette converting process that an OS performs on a CPU 500 through hardware instead, and converts respective pixel values of image data generated by an image generation part 110 into proper hardware palette numbers. At this time, a palette conversion table is referred to by the palette conversion part 120 when the respective pixel values of the image data generated by the image generation part 110 are converted into the hardware palette numbers. In this case, the palette conversion table 121 is actualized by using a RAM and contents from the CPU can be altered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a personal computer or a workstation, and more particularly to an image processing apparatus for handling multicolor images such as natural images.

[0002]

2. Description of the Related Art An image processing apparatus such as a personal computer may handle a natural image such as a landscape image or a portrait of a person, or a computer graphics image of multicolor display. In this case, if the capacity of the display memory that stores the image to be displayed is sufficient and the number of colors required by a display device such as a CRT can be displayed, the pixel value in the display memory and the pixel value on the display device are displayed. It is usual to make one-to-one correspondence. This example will be described with reference to FIG.

The image processing apparatus has a CPU 5 for performing drawing processing.
00, a display memory 600 for storing the data to be displayed,
It is composed of a display device 800 such as a CRT and a controller 700 for displaying the data stored in the display memory 600 on the display device 800. The pixel data (4036 in this example) output from the drawing program 501 executed by the CPU 500 is stored in the display memory 600.
Is written to the display device 800 and this value is output as it is on the display device 800. In this way, although the required memory capacity increases, many colors can be used at one time to display an image. For example, if a memory of 24 bits in total, that is, 8 bits of RGB for each pixel, is allocated for the display memory, it is possible to use 2 24, that is, 16,777,216 colors at one time. When displaying a normal natural image (still image or moving image), an image of practically sufficient image quality can be obtained if 16777,216 colors can be displayed.

This method requires a large-capacity display memory. However, when cost reduction and miniaturization are required, it may be necessary to reduce the capacity of the display memory. In this case, the number of colors that can be used is limited even if the display device has sufficient capability. For example, even if the CRT can display 16777216 colors, if only 8 bits of memory per pixel are allocated for the display memory, only 2 8 at the maximum, that is, 256 colors can be used. . This 256
If colors are simply assigned, the quality of the displayed image will be considerably degraded. As a means for solving this, a method called color conversion using a hardware palette is generally used. This is the following method.

Generally, even when a natural image is displayed in an image processing apparatus capable of displaying 16777216 colors, the number of colors used simultaneously in one screen is considerably smaller than 16777216 colors. It is normal. what if,
Assuming a case where only 256 colors are used at the same time in one screen, even if only 8 bits of memory per pixel are allocated for the display memory, by devising the usage method of the memory, there is no deterioration in image quality. It is possible to display. That is, 256 that are actually used
It suffices to prepare a mechanism for converting colors into 256 kinds of values that can be expressed by 8 bits of the display memory. One of these mechanisms is the hardware palette. As a method of realizing a hardware palette, a method using a table called a palette conversion table is generally used. This example will be described with reference to FIG.

The image processing apparatus has a CPU 5 for performing drawing processing.
00, a display memory 600 for storing the data to be displayed,
It is composed of a display device 800 such as a CRT and a controller 700 for displaying the data stored in the display memory 600 on the display device 800. The hardware palette number (124 in this example) output from the drawing program 501 executed by the CPU 500 is written in the display memory 600. This hardware palette number is set to the pixel value (403 in this example) by the hardware palette conversion circuit 701 in the controller 700.
6), and this value is output on the display device 800. As a method similar to this, there is a monochrome / color conversion used in the "image processing apparatus" of JP-A-2-59868.

On the other hand, in recent years, in the world of personal computers and workstations, multitasking OSs have become the mainstream.
In these OSs, a plurality of programs create independent windows and share one image display circuit.
In this case, since a plurality of programs being executed use one palette conversion table, a mechanism is required to prevent a change in the palette conversion table by one program from affecting another program. . These OSs solve this problem by means called a logical palette. In this method, each program expresses a color by a logical palette number that specifies an entry of the logical palette, and the OS converts this into a hardware palette number and outputs it to the image display circuit. The image display circuit converts the hardware palette number into an actual display color and outputs it. This example will be described with reference to FIG.

The image processing apparatus has a CPU 5 for performing drawing processing.
00, a display memory 600 for storing the data to be displayed,
It is composed of a display device 800 such as a CRT and a controller 700 for displaying the data stored in the display memory 600 on the display device 800. The logical palette number (3 in this example) output from the drawing program 501 executed in the CPU 500 is converted into a hardware palette number (124 in this example) by the logical palette conversion program 502 executed in the CPU. And is written in the display memory 600. This hardware palette number is converted into a pixel value (4036 in this example) by the hardware palette conversion circuit 701 in the controller 700, and this value is output by the display device 800. For this method, see "Windows
s API Bible 1: Shoeisha June 24, 1993
It is described in detail in documents such as "Issuing daily."

[0009]

SUMMARY OF THE INVENTION In the above conventional method,
The conversion process from the logical palette number to the hardware palette number is executed by the OS on the CPU. In a general application, since the program on the CPU writes the image data to the display memory, there is no particular problem in performing the palette conversion process. However, when handling a large amount of data such as moving image processing, it is conceivable to use a dedicated image generation circuit (image processing circuit) instead of performing image processing by the CPU. In this case, since the conversion from the logical palette to the hardware palette has to be performed, the access is not via DMA transfer but via the CPU, that is, the image generation circuit to the CPU and the CPU to the image display circuit. Data transfer is required. As described above, since it is not possible to directly send data from the image generation circuit to the image display circuit by the DMA transfer, there is a problem that the bus usage efficiency is lowered and the image data transfer speed is lowered.

Further, since image data in a direct color format cannot be displayed on an image display circuit which handles colors in the hardware palette number format, conversion to a hardware palette number must be performed using a logical palette or the like. There wasn't. Furthermore, depending on the method of the image display circuit,
There was a problem that the drawing performance was affected. In view of the above problems, it is an object of the present invention to directly transfer image data from an image generation circuit to an image display circuit by DMA even when a logical palette is used, thereby improving high-speed transfer and bus usage efficiency. And In addition, the image generation circuit enables generation of two types of image data in the hardware palette number format and the direct color format, and the DMA to the image display circuit etc. in the selected image data format.
The other purpose is to enable transfer.

[0011]

In order to solve this problem, in the image processing apparatus and the image processing method of the present invention, a palette for converting a logical palette number into a hardware palette number is provided inside the image generation circuit. Equipped with a conversion circuit. Also, a selector circuit for switching the image data format output by the image generation circuit to either the hardware palette number or direct color is mounted. The palette conversion table used for this palette conversion is updated at any time, and holds the same contents as the palette conversion table inside the CPU even when the palette conversion table inside the CPU is changed.
The designation of switching to the selector circuit can be changed from the CPU at any time.

[0012]

In the image processing apparatus of the present invention, a palette conversion circuit for converting a logical palette number into a hardware palette number is installed inside the image generation circuit. Therefore, it is possible to directly send data from the image generation circuit to the image display circuit by the DMA transfer, and it is possible to improve the use efficiency of the bus. In this case, since the image generation circuit performs the image transfer processing, the CPU load is reduced,
The performance of the entire system can be improved. Further, since the selector circuit for switching the format of the output image data is installed, the image generation circuit can generate two types of image data of the hardware palette number format and the direct color format.

Further, in the case of a system equipped with an image display circuit that handles colors in the form of hardware palette numbers,
If the selector circuit is set to output the image data in the hardware palette number format, the selector circuit outputs the image data in that format. Further, in the case of a system including an image display circuit that handles image data in direct color format, if the selector circuit is set to output image data in direct color format, the selector circuit Output image data.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic block diagram of an embodiment of an image processing apparatus according to the present invention. The image processing apparatus uses a central processing unit (CP) when a large amount of data processing or large-scale calculation is required such as moving image processing or three-dimensional graphics.
U) An image generation circuit 10 that performs drawing processing instead of 500
0, image display circuit 200, CPU 500, CRT or LC
It is composed of a display device 800 such as D. The image generation circuit 100, the image display circuit 200, and the CPU 500 are connected to each other by a system bus 300. The image display circuit 200 includes a display memory 60 that stores data to be displayed.
0, the control circuit 210 of the display memory 600, and the data stored in the display memory 600 to the display device 800.
It is composed of a controller 700 and the like for displaying. Although not shown in FIG. 1, it is possible to incorporate a simple drawing circuit such as a straight line drawing in the image display circuit 200 in order to improve drawing performance. Image generation circuit 1
The image generated by 00 is C by DMA transfer.
It is stored in the display memory 600 inside the image display circuit 200 without passing through the PU 500. Further, the image display circuit 200 can be accessed from the CPU 500 as in the conventional case.

FIG. 2 is an example of a block diagram of the image generation circuit 100. The image generation circuit 100 includes an image generation unit 110 that generates image data, a logical palette conversion unit 120 that converts a logical palette to a hardware palette, and the generated image data to a device on the system bus 300.
It is composed of a DMA transfer control unit 130 for MA transfer. The logical palette conversion unit 120 replaces the logical palette conversion process performed by the OS on the CPU 500 with hardware when the CPU 500 performs the drawing process, and each pixel of the image data generated by the image generation unit 110. Convert the value to the appropriate hardware palette number. Then, at this time, the palette conversion table 121 converts the pixel values of the image data generated by the image generation unit 110 into hardware palette numbers when the palette conversion unit 1 is used.
Referenced from 20. In the present embodiment, the palette conversion table 121 is realized by the RAM, and the CPU
The content can be changed from.

An example of the configuration of the logical palette conversion unit 120 is shown in FIG.
Shown in This is a circuit for converting a 4-bit logical palette number into a 4-bit hardware palette number. The logical palette converter 120 includes a decoder 122.
1, AND gates 122a-p, latches 123a-p,
It consists of a selector 124. The decoder 121 decodes the 4-bit binary number represented by the four input signals 1210 to generate 16 signals 1211a to 1211p. Only one of the signals 1211a to 1211p is active at all times corresponding to the input signal 1210.

An example of the internal structure of the decoder 121 is shown in FIG.
The input / output relationship is shown in the table of FIG. Decoder 121
Means AND gates 1212a to 1212p, and the circles attached to the respective inputs mean that the logic of the signal is inverted. For example, when all the input signals 1210a to 1210d are 0 (L level), the output 1 of the AND gate 1212a is 1
Only 211a becomes 1 (H level), and the outputs 1211b to 1211p of the other AND gates 1212b to 1212p become 0 (L level). Each of the latches 123a to 123p is a circuit for holding 4-bit data.

The selector 124 is a circuit which selects one from 16 inputs and outputs it. An example of the configuration of the selector 124 is shown in FIG. 5, and its input / output relationship is shown in the table of FIG. The selector 124 includes an OR gate 1248 and an AND gate 12
45a-p and 1247a-p, and the circles attached to the respective inputs mean that the logic of the signal is inverted. For example, when all the input signals 1241a to 1241d are 0 (L level), the output 1 of the AND gate 1245a
Only 246a becomes 1 (H level), and the outputs 1246b-p of the other AND gates 1245b-p become 0 (L level). As a result, the output 1 of the select circuit composed of AND gates 1247a-p and OR gate 1248
At 242, the value of signal 1240a will appear.

Next, the operations of the logical palette conversion unit 120 and the selector unit 125 will be described with reference to FIGS. First, the operation when converting from a logical palette to a hardware palette will be described. Latch 123a
It is assumed that the palette conversion table values as shown in the example of the table of FIG. 9 have already been set in to p. Here, when a 4-bit logical palette number is input from the logical palette input terminal 1241, one of the output signals 1240a to 1240p of the latches 123a to 123p is selected by the selector 124, and the content thereof is the hardware palette output terminal. It is output from 1242. For example, when "3" is input as the logical palette number, the content of the output 1240d of the latch 123d is output to the output terminal 1242 of the selector 124 according to Table 2. Here, since "7" is stored in the latch 123d from Table 3,
As the hardware palette number, “7” is output to the output terminal 1242. That is, as a result of this series of operations, the logical palette number "3" has been converted into the hardware palette number "7".

The selector unit 125 includes a palette conversion circuit 1
The image data in the hardware palette number format from 20 and the image data in the direct color format from the image generation unit 110 are input, and the image data in either format is output. A register 126 is used by the CPU to specify the format of the image data output by the selector unit 125. The image data generated by the image generation unit 110 is input to the palette conversion unit 120 and the selector unit 125.
The palette conversion unit 120, which has input the image data, detects which entry in the palette conversion table 121 the RGB value of each pixel matches, and outputs the hardware palette number described in the entry.

The selector unit 125 includes a palette conversion unit 12
The hardware palette number is input from 0 and the RGB value is input from the image generation unit 110. Selector unit 12
Reference numeral 5 refers to the register 126 and outputs data in the designated format. When the CPU changes the contents of the register 126, the selector unit 125 switches the output image data format. The output from the selector unit 125 is DM
It becomes an input of the A transfer control unit 130. DMA transfer control unit 1
The input image data 30 is sequentially DM-displayed on the image display circuit.
A transfer.

Next, a method of changing the logical palette conversion table will be described. Since the contents of the logical palette conversion table are stored in the latches 123a to 123p, this can be changed. If you change this,
First, the logical palette number to be changed is input from the logical palette input terminal 1210. Next, the hardware pallet number to be newly associated with the designated logical pallet number is set in the input terminal 1230. After that, when a pulse is input to the write clock signal 1220, the change of the palette conversion table is completed. In the above description, the number of bits of the logical palette and the number of bits of the hardware palette are both 4 bits for simplification of description, but it is also possible to use a bit number other than 4 bits.
Also, the logical palette and the hardware palette do not have to have the same number of bits. Furthermore, the logical palette conversion unit 1
If 20 and the selector unit 125 are integrated in the same LSI as the image generating unit 110 and the like, it is advantageous in terms of cost, mounting area, and the like.

When the conversion method of the logical palette conversion program operating on the CPU 500 is changed, the logical palette conversion table in the image generating circuit 100 is always updated so that the logical palette conversion program operates on the CPU 500. It is possible for the logical palette conversion program and the logical palette conversion unit 120 inside the image generation circuit 100 to perform the same conversion. By doing so, the display memory 600 is displayed on the single screen from the CPU 500.
The data transferred to the display memory 600 and the data transferred to the display memory 600 can coexist without adversely affecting the other access.

[0024]

According to the present invention, since the image data can be directly DMA-transferred from the image generation circuit to the image display circuit even when the logical palette is used, high-speed transfer can be performed and the bus usage efficiency can be improved. It is possible to increase the display performance and the system performance at the same time. Further, the image data can be DMA-transferred from the image generation circuit to the image display circuit capable of displaying the image data of the hardware palette number format and / or the direct color format. Therefore, regardless of the format of the image data, high-speed transfer can be performed similarly, the bus usage efficiency can be improved, and the display performance and the system performance can be improved at the same time. In addition, since a wide variety of image data formats can be handled, the versatility of the image generation circuit can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a configuration example of an image generation circuit.

FIG. 3 is a configuration example of a logical palette conversion unit.

FIG. 4 is a configuration example of a decoder.

FIG. 5 is a configuration example of a selector.

FIG. 6 shows an example of an image data transfer method.

FIG. 7 is a table showing an example of input / output relationships of a decoder.

FIG. 8 is a table showing an example of input / output relationships of selectors.

FIG. 9 is a table showing an example of the contents of a palette conversion table.

[Explanation of symbols]

 100 image generation circuit 110 image generation unit 120 logical palette conversion unit 121 decoder 123 latch 125 selector unit 126 register 130 DMA transfer control unit 200 image display circuit 210 display memory control unit 300 system bus 500 CPU 501 CPU drawing program 502 CPU Logical palette conversion program 600 Display memory 700 Display controller 701 Hardware palette 800 Display device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyokazu Nishioka 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. System Development Laboratory (72) Inventor, Koichi Terada 1099, Ozen-ji, Aso-ku, Kawasaki, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Nouki Kurokawa 1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Stock Company Hitachi Systems Development Laboratory (72) Inventor Yoshifumi Fujikawa 1099, Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside the Hitachi, Ltd. System Development Laboratory (72) Koichi Haneda Koichi Haneda, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within Hitachi Microsoft Wear Systems (72) Inventor Takusho Himine Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho Hitachi Microsof Co., Ltd. (72) Inventor Shigeo Tsujioka 810 Shimoimaizumi, Ebina-shi, Kanagawa Hitachi Ltd. Office Systems Division (72) Inventor Toshio Tanaka 810 Shimoimaizumi, Ebina, Kanagawa Hitachi Ltd. Office Systems Within the business unit

Claims (7)

[Claims] 1. A CPU comprising at least a CPU, an image generation circuit for generating image data, an image display circuit for displaying image data, and a bus interconnecting these components.
When the image data is transferred from the image display circuit to the image display circuit, the palette conversion that is executed in the CPU is executed by the palette conversion mechanism installed in the image generation circuit, and the image data generated by the image generation circuit is transferred by DMA transfer. , An image processing method characterized by high-speed transfer to an image display circuit without passing through a CPU. 2. An image processing apparatus comprising at least a CPU, an image generating circuit for generating image data, an image display circuit for displaying image data, and a bus interconnecting these, wherein the image generating circuit generates Since the image data is transferred to the image display circuit at high speed by DMA transfer without passing through the CPU, a mechanism for executing the palette conversion which is executed in the CPU when transferring the image data from the CPU to the image display circuit is provided. An image processing device characterized by being installed. 3. The image processing apparatus according to claim 2, wherein the palette conversion mechanism is an image generation LSI mounted in the same chip as an image generation circuit that generates image data. 4. The pallet conversion mechanism includes a pallet conversion method changing unit, and the pallet converting method changes the CP.
By implementing the same conversion method as the palette conversion by U, the image data sent from the CPU to the image display circuit and the data sent from the image generation LSI to the image display circuit on a single screen adversely affect each other. The image processing apparatus according to claim 3, wherein the image processing apparatus can coexist without being present. 5. At least a color that can be displayed simultaneously with a CPU is in a hardware palette number format that specifies a color with a hardware palette and its index number, or a direct color format that specifies a color without using the hardware palette. An image display circuit that displays image data in either or both formats, an image generation circuit that generates image data, an image display circuit, the image generation circuit, and a bus that interconnects the CPUs. A palette conversion mechanism for converting the image data into the hardware palette number format in place of the CPU in the image generation circuit;
The format of the output image data is direct color format,
By providing a selector mechanism for switching to a designated one of the hardware palette number formats, the image generation circuit generates image data of a format suitable for the image display circuit, and the CPU is provided to the image display circuit. An image processing apparatus characterized by direct DMA transfer without passing through. 6. A CPU, an image display circuit for displaying image data in at least one of a hardware palette number format and a direct color format, or both, and an image generation circuit for generating image data. In an image processing device comprising a bus interconnecting the image display circuit, the image generation circuit, and the CPU,
The image data of a format suitable for the image display circuit is the C
Since the DMA transfer is performed directly without passing through the PU, the image generation circuit converts the image data into the hardware palette number format on behalf of the CPU, and the format of the output image data is the direct color format. Or a selector mechanism for switching to a specified one of hardware palette number formats. 7. The pallet conversion mechanism and the selector mechanism are image generation LSIs mounted in the same chip as an image generation circuit that generates image data. The image processing device described.