JPH0793478B2 - Printed circuit board for mounting semiconductor chips - Google Patents
Printed circuit board for mounting semiconductor chipsInfo
- Publication number
- JPH0793478B2 JPH0793478B2 JP63068585A JP6858588A JPH0793478B2 JP H0793478 B2 JPH0793478 B2 JP H0793478B2 JP 63068585 A JP63068585 A JP 63068585A JP 6858588 A JP6858588 A JP 6858588A JP H0793478 B2 JPH0793478 B2 JP H0793478B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- circuit board
- printed circuit
- epoxy resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Reinforced Plastic Materials (AREA)
- Laminated Bodies (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Organic Insulating Materials (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は電子機器の回路構成に利用することができるプ
リント回路板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board that can be used in a circuit configuration of electronic equipment.
従来の技術 プリント配線板の基材には、紙基材フェノール樹脂板，
ガラス布基材エポキシ樹脂板などが一般に用いられ、こ
の種の基板上に銅箔導体層を張り付けて、回路配線導体
としている。また、最近では、メタ系アーラミド繊維布
にポリイミド樹脂を含浸させた基材構成も試みられてい
る。Conventional technology As a base material for a printed wiring board, a paper-based phenol resin board,
A glass cloth-based epoxy resin plate or the like is generally used, and a copper foil conductor layer is attached to a substrate of this type to form a circuit wiring conductor. In addition, recently, a base material structure in which a meta-based aramide fiber cloth is impregnated with a polyimide resin has been attempted.
発明が解決しようとする課題 近年、プリント配線板上に半導体集積回路チップ（以
下、単に半導体チップと記す）を直接搭載して、ハイブ
リッド回路板を形成する用途が生まれているが、かかる
用途には、従来のプリント配線板は必ずしも適合しな
い。すなわち、紙基材板は半導体チップ搭載の過程の高
温プロセスに不適合であり、ガラス布基材板では不純
物、とりわけ、ナトリウム成分の半導体チップへの作用
を排除するのが困難である。さらに、樹脂含浸のプリン
ト配線板では、半導体チップとの熱的整合、すなわち、
温度による伸縮率が半導体と樹脂とで著しく異なるの
で、温度サイクルで接着剥離を起こしたり、半導体チッ
プが破断するという問題を有していた。この種の問題
は、従来のメタ系アーラミド繊維紙にポリイミド樹脂含
浸の基板の場合も同様に生じていた。Problems to be Solved by the Invention In recent years, a semiconductor integrated circuit chip (hereinafter simply referred to as a semiconductor chip) is directly mounted on a printed wiring board to form a hybrid circuit board. , The conventional printed wiring board is not always suitable. That is, the paper base plate is incompatible with the high temperature process of mounting the semiconductor chips, and it is difficult to eliminate the action of impurities, especially sodium components, on the semiconductor chips in the glass cloth base plate. Furthermore, in a resin-impregnated printed wiring board, thermal matching with the semiconductor chip, that is,
Since the expansion and contraction rate depending on the temperature is remarkably different between the semiconductor and the resin, there are problems that adhesive peeling occurs in the temperature cycle and the semiconductor chip breaks. This kind of problem also occurs in the case of a substrate in which a conventional meta-type aramide fiber paper is impregnated with a polyimide resin.
本発明の目的は、半導体チップを直接搭載しても、高信
頼性が達成できるプリント回路板を提供することにあ
る。An object of the present invention is to provide a printed circuit board which can achieve high reliability even when a semiconductor chip is directly mounted.
課題を解決するための手段 本発明は、パラ系アーラミド基材にエポキシ樹脂を55〜
60重量％の割合で含浸させ、表面に導体層を被着した構
成のプリント回路板である。パラ系アーラミドはポリパ
ラフェニレン３−４′ディフェニルエーテルテレフタラ
ミドを使用すると好適である。また、このエポキシ樹脂
含浸ポリパラフェニレン３−４′ディフェニルエーテル
テレフタラミド基材回路板を用い、スルーホールをもっ
て、他方の基板の配線層と導電接続するとき、その導電
接続材にはエポキシ樹脂系導電塗布層を使用したものが
適当である。Means for Solving the Problems The present invention provides a para-based aramide base material with an epoxy resin of 55-
It is a printed circuit board having a structure in which it is impregnated at a ratio of 60% by weight and a conductor layer is adhered on the surface. The para-based aramide is preferably polyparaphenylene 3-4 'diphenyl ether terephthalamide. When this epoxy resin-impregnated polyparaphenylene 3-4 'diphenyl ether terephthalamide substrate circuit board is used to conductively connect to the wiring layer of the other board through the through holes, the conductive connecting material is epoxy resin. It is suitable to use a system conductive coating layer.
作用 本発明によると、−40℃〜150℃の温度範囲にわたっ
て、シリコン基材の半導体チップと同等の伸縮率を有す
る回路板が得られる。ポリパラフェニレン３−４′ディ
フェニルエーテルテレフタラミド基材は温度に対して負
の係数をもち、エポキシ樹脂の正の温度係数を相殺し
て、半導体チップと同等の温度係数を実現できる。こう
して、温度及び湿度のサイクル的変化に対して、信頼性
の高い半導体チップ搭載用プリント回路板が得られる。Effect According to the present invention, a circuit board having the same expansion / contraction ratio as that of a silicon-based semiconductor chip can be obtained over a temperature range of -40 ° C to 150 ° C. The polyparaphenylene 3-4 'diphenyl ether terephthalamide base material has a negative coefficient with respect to temperature, and can cancel the positive temperature coefficient of the epoxy resin to realize a temperature coefficient equivalent to that of a semiconductor chip. In this way, it is possible to obtain a semiconductor chip mounting printed circuit board that is highly reliable against cyclic changes in temperature and humidity.
実施例 つぎに、本発明を実施例によって詳しくのべる。Examples Next, the present invention will be described in detail with reference to Examples.
第１図は本発明実施例回路板の適用装置の断面図であ
り、絶縁性基板１を、芳香族ポリアミンアダクト硬化剤
配合のエポキシ樹脂を重量比55〜60％で含浸させたポリ
パラフェニレン３−４′ディフェニルエーテルテレフタ
ラミド紙または布基材板で形成し、この絶縁性基板１上
に、厚さ35μｍの銅箔導体２および厚さ５〜７μｍの銀
めっき層３を設け、半導体チップ４を接着し、ワイヤ５
で接続したものである。絶縁性基板１上への銅箔導体２
の張り付けは、含浸材のエポキシ樹脂の硬化過程を利用
して、その半硬化状態で貼り合わせ、完全硬化過程で接
着すればよい。また、半導体チップ４の接着は、同チッ
プ裏面側に金層を形成しておき、その金属を介して圧着
することで可能である。また、半導体チップ４の接着
に、芳香族ポリアミンアダクトを硬化剤としたエポキシ
樹脂配合の導電性接着剤を用いることもでき、これによ
ると、銀の移行を抑止する効果がある。さらに、銀めっ
き層３の代わりに、ニッケルまたはニッケルと金との二
重層を用いることができる。FIG. 1 is a cross-sectional view of a device for applying a circuit board according to an embodiment of the present invention, in which an insulating substrate 1 is impregnated with an epoxy resin containing an aromatic polyamine adduct curing agent at a weight ratio of 55 to 60% by weight of polyparaphenylene 3 -4 ′ diphenyl ether terephthalamide paper or cloth base plate, and a copper foil conductor 2 having a thickness of 35 μm and a silver plating layer 3 having a thickness of 5 to 7 μm are provided on the insulating substrate 1 to form a semiconductor. Bond the chip 4 and wire 5
It was connected with. Copper foil conductor 2 on insulating substrate 1
The sticking may be carried out by utilizing the curing process of the epoxy resin of the impregnating material, bonding in the semi-cured state, and adhering in the complete curing process. Further, the semiconductor chip 4 can be adhered by forming a gold layer on the back surface side of the chip and press-bonding it through the metal. Further, a conductive adhesive compounded with an epoxy resin using an aromatic polyamine adduct as a curing agent can be used for bonding the semiconductor chip 4, which has an effect of suppressing migration of silver. Further, instead of the silver plating layer 3, nickel or a double layer of nickel and gold can be used.
絶縁性基板１の基材であるパラ系アーラミドのポリパラ
フェニレン３−４′ディフェニルエーテルテレフタラミ
ドは、メタ系アーラミドのポリパラフェニレンテレフタ
ラミドより塩素等の不純物の含有量が１〜２桁少ない。
また、このパラ系アーラミド紙は、高い耐熱性をもつ
が、エポキシ樹脂含浸により、絶縁性基板１の耐熱性
は、その含浸材に依存し、たとえば、結晶化温度（Tg）
が125〜150℃となる。しかし、半導体チップ４の接着あ
るいは、ワイヤボンディングの際の短時間の高温なら
ば、約350℃までの耐久性は得られる。The para-type aramide polyparaphenylene 3-4 ′ diphenyl ether terephthalamide, which is the base material of the insulating substrate 1, has a content of impurities such as chlorine of 1 to 2 compared to the meta-type aramide polyparaphenylene terephthalamide. Digit less.
Moreover, although this para-type aramide paper has high heat resistance, the heat resistance of the insulating substrate 1 depends on the impregnating material due to the epoxy resin impregnation. For example, the crystallization temperature (Tg)
Becomes 125-150 ℃. However, if the semiconductor chip 4 is bonded or wire bonding is performed at a high temperature for a short time, durability up to about 350 ° C. can be obtained.
実施例として、芳香族ポリアミンアダクト硬化剤配合エ
ポキシ樹脂含浸（含浸率60重量％）のパラ系アーラミド
基材基板１上に、35μｍの銅箔２を張り付け、これに、
銀めっき層３を介して、半導体チップ（チップサイズ:4
×4mm）４を接着したもので、その温度サイクル（−65
℃〜150℃）および温度サイクル（120℃,100％〜120
℃，ドライ）の各テストを行ったところ、基板寸法10×
10cm,厚さ1.6mmの場合、上記温度サイクル:450〜500
回，上記湿度サイクル:100〜150回の耐久性が確認さ
れ、また、基板の厚さを0.4mmになしたもので、温度サ
イクル:200回〜250回，湿度サイクル:75〜125回の耐久
性が得られた。As an example, a 35 μm copper foil 2 is attached to a para-type aramide base substrate 1 impregnated with an aromatic polyamine adduct curing agent and impregnated with an epoxy resin (impregnation rate 60% by weight).
The semiconductor chip (chip size: 4
X4mm) 4 bonded together, the temperature cycle (-65
℃ ~ 150 ℃) and temperature cycle (120 ℃, 100% ~ 120
When each test (° C, dry) was performed, the board size was 10 x
For 10 cm and 1.6 mm thickness, the above temperature cycle: 450 to 500
, The above humidity cycle: durability of 100 to 150 times is confirmed, and the thickness of the substrate is 0.4 mm, temperature cycle: 200 to 250 times, humidity cycle: 75 to 125 times of durability Sex was obtained.
第２図は、別の実施例のプリント回路板を示す断面図で
ある。このプリント回路板は、芳香族ポリアミンアダク
ト硬化剤配合のエポキシ樹脂を含浸率60重量％で含浸さ
せたパラ系アーラミド繊維紙基材の第１基板21に、厚さ
35μｍの銅箔導体23を貼り合わせ、これに、上記第１基
板21と同組織の第２基板22および厚さ35μｍの銅箔導体
24を、それぞれ、重ねて貼り合わせたものである。そし
て、第１基板21には、スルーホールを形成し、このスル
ーホールを第２基板22上の銅箔導体24の位置に合わせて
貼り合わせたのち、スルーホールを、芳香族ポリアミン
アダクト硬化剤配合エポキシ樹脂中に銀粉を混合した導
電接着材の塗布によって埋め、導電層25を形成した。こ
の導電層25の形成は、金属マスクを使って、印刷形成す
ることができる。なお、各基板および銅箔の貼り合わせ
の工程ならびにスルーホールの形成工程は、エポキシ樹
脂を、初めに、130℃,30分で半硬化（いわゆる、Ｂステ
ージ硬化）の状態で行い、これらを重ね合わせたのち
に、160〜165℃,15〜10分の再硬化処理を行うことによ
って、完全硬化（Ｃステージ硬化）の状態にできる。ま
た、塗布導電層25の硬化条件も、基板形成時とほとんど
同じでよいが、流動性を考慮すると、150℃,30分程度の
低温、長時間を採用するのが適当である。FIG. 2 is a sectional view showing a printed circuit board of another embodiment. This printed circuit board has a thickness of the first substrate 21 made of a para-based aramide fiber paper substrate impregnated with an epoxy resin containing an aromatic polyamine adduct curing agent at an impregnation rate of 60% by weight.
A copper foil conductor 23 having a thickness of 35 μm is attached to the second substrate 22 having the same structure as the first substrate 21 and a copper foil conductor having a thickness of 35 μm.
Each of 24 is laminated and pasted. Then, a through hole is formed in the first substrate 21, the through hole is aligned with the position of the copper foil conductor 24 on the second substrate 22, and then the through hole is mixed with an aromatic polyamine adduct curing agent. The conductive layer 25 was formed by filling the epoxy resin with a conductive adhesive in which silver powder was mixed. The conductive layer 25 can be formed by printing using a metal mask. In addition, the step of attaching each board and the copper foil and the step of forming the through hole are performed by first using epoxy resin in a semi-cured state (so-called B stage curing) at 130 ° C. for 30 minutes, and stacking these. After the combination, a complete curing (C stage curing) state can be obtained by performing a re-curing treatment at 160 to 165 ° C. for 15 to 10 minutes. The coating conductive layer 25 may be cured under almost the same conditions as when forming the substrate, but considering fluidity, it is appropriate to employ a low temperature of 150 ° C. for about 30 minutes and a long time.
第３図は、四層配線をもつ積層基板構造の実施例プリン
ト回路板の断面図である。この実施例構成で、第1,第２
および第３基板31,32および33は、いずれも、ポリパラ
フェニレン３−４′ディフェニルエーテルテレフタラミ
ド繊維紙に、芳香族ポリアミンアダクト硬化剤配合のエ
ポキシ樹脂を55〜60重量％に含浸させた、厚さ0.1〜1.0
mmの構成物であり、導体層34,35,36,37は、厚さ35μｍ
あるいは70μｍの銅箔で形成される。また、互いの導体
層を接続するためのスルーホール導電層38,39は、芳香
族ポリアミン硬化剤配合エポキシ樹脂に銀分混合の導電
性接着剤の塗布層で形成される。なお、この導電層の抵
抗率は12〜15mΩ／□であった。FIG. 3 is a sectional view of an embodiment printed circuit board having a laminated substrate structure having four-layer wiring. With this embodiment configuration, the first and second
And the third substrates 31, 32 and 33 are all made by impregnating polyparaphenylene 3-4 'diphenyl ether terephthalamide fiber paper with an epoxy resin containing an aromatic polyamine adduct curing agent in an amount of 55 to 60% by weight. Thickness 0.1-1.0
mm composition, the conductor layers 34, 35, 36, 37 have a thickness of 35 μm.
Alternatively, it is formed of 70 μm copper foil. Further, the through-hole conductive layers 38, 39 for connecting the conductor layers to each other are formed of a coating layer of a conductive adhesive containing a mixture of an epoxy resin containing an aromatic polyamine curing agent and a silver content. The resistivity of this conductive layer was 12 to 15 mΩ / □.
この実施例構成は、所望の多層配線を得るのに適し、耐
熱性，耐湿性にすぐれたものである。The structure of this embodiment is suitable for obtaining a desired multilayer wiring, and has excellent heat resistance and moisture resistance.
発明の効果 本発明によれば、芳香族ポリアミンアダクト硬化剤配合
エポキシ樹脂含浸ポリパラフェニレン３−４′ディフェ
ニルエーテルテレフタラミド基材を用いて、プリント回
路板を構成したことにより、耐熱性，耐湿性のよいもの
が実現され、とくに、同基板上に半導体チップを直接搭
載しても、両者の温度伸縮率が同等なため、熱的破損が
避けられる。また、本発明のプリント回路板は、銀の移
行性をも十分に抑止する効果があり、多層構造で、高密
度配線構造を採用して、その配線間相互の影響を抑制し
て、高度の信頼性を達成することができる。EFFECTS OF THE INVENTION According to the present invention, a printed circuit board is formed by using an aromatic polyamine adduct curing agent-containing epoxy resin-impregnated polyparaphenylene 3-4 ′ diphenyl ether terephthalamide base material. High moisture resistance is realized, and even if a semiconductor chip is directly mounted on the same substrate, thermal expansion and contraction rates of both are equal, so thermal damage can be avoided. Further, the printed circuit board of the present invention has an effect of sufficiently suppressing the migration of silver, and has a multilayer structure, adopts a high-density wiring structure, and suppresses the mutual influence between the wirings, Reliability can be achieved.
第１図〜第３図は本発明の各実施例プリント回路板の断
面図である。 1,21,22,31,32,33……エポキシ樹脂含浸パラ系アーラミ
ド基材基板、2,23,24,34〜37……銅箔導体。1 to 3 are sectional views of printed circuit boards according to respective embodiments of the present invention. 1,21,22,31,32,33 …… Epoxy resin impregnated para-based aramide substrate, 2,23,24,34〜37 …… Copper foil conductor.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−35593（ＪＰ，Ａ) 特開 平３−91988（ＪＰ，Ａ) 特開 平１−241195（ＪＰ，Ａ) 特開 昭62−250689（ＪＰ，Ａ) 特開 昭59−175184（ＪＰ，Ａ) 特開 昭62−165393（ＪＰ，Ａ) 特開 昭63−107091（ＪＰ，Ａ) 特開 昭63−233593（ＪＰ，Ａ) 特開 昭58−178905（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-35593 (JP, A) JP 3-91988 (JP, A) JP 1-241195 (JP, A) JP 62- 250689 (JP, A) JP 59-175184 (JP, A) JP 62-165393 (JP, A) JP 63-107091 (JP, A) JP 63-233593 (JP, A) JP 58-178905 (JP, A)
Claims (2)
エーテルテレフタラミド基材にエポキシ樹脂を55〜60重
量％の割合で含浸させ、表面に導体層を被着し、前記導
体層の一部に半導体チップが搭載される半導体チップ搭
載用プリント回路板。1. A polyparaphenylene 3-4 'diphenyl ether terephthalamide base material is impregnated with an epoxy resin in a proportion of 55 to 60% by weight, and a conductor layer is adhered to the surface of the base material to form a part of the conductor layer. A semiconductor chip mounting printed circuit board on which a semiconductor chip is mounted.
ルを有する第１の基材をエポキシ樹脂含浸のポリパラフ
ェニレン３−４′ディフェニルエーテルテレフタラミド
基材で構成し、前記第１の基板を、少なくとも一面に導
体層を有する第２の基板に重ね、前記第１の基板上の導
体層と前記第２の基板上の導体層とをエポキシ樹脂系導
電塗布層で導電接続した半導体チップ搭載用プリント回
路板。2. A first substrate having a conductor layer and a through hole on one side or both sides is made of an epoxy resin-impregnated polyparaphenylene 3-4 'diphenyl ether terephthalamide substrate, and the first substrate is provided. On a second substrate having a conductor layer on at least one surface, and a semiconductor chip mounted in which the conductor layer on the first substrate and the conductor layer on the second substrate are conductively connected by an epoxy resin-based conductive coating layer. Printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068585A JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068585A JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01241194A JPH01241194A (en) | 1989-09-26 |
| JPH0793478B2 true JPH0793478B2 (en) | 1995-10-09 |
Family
ID=13378017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63068585A Expired - Fee Related JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793478B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6235593A (en) * | 1985-08-09 | 1987-02-16 | 東芝ケミカル株式会社 | Metal substrate for circuit |
-
1988
- 1988-03-23 JP JP63068585A patent/JPH0793478B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01241194A (en) | 1989-09-26 |
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