JPH0766721A - Frequency divider and digital signal processor - Google Patents

Abstract

PURPOSE:To provide a frequency divider capable of dividing the frequency of a clock input with high frequency. CONSTITUTION:This frequency divider is constituted of a shift register 1 including plural flip flops(FFs) previously initialized at the same level by a reset signal RESET and having an input signal as a clock and a circuit means 3 for inverting an output from the register 1, feeding back the inverted signal to the input of the register 1, and when a frequency dividing number is an odd number, by-passing one stage of the register 1 in accordance with the output level of the register 1. A circuit means for by-passing one stage of the register 1 in accordance with the output level of the register 1 when the frequency dividing number is an even number is omitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider for a semiconductor integrated circuit and a digital signal processor using the same,
In particular, the present invention relates to a frequency dividing technique suitable for an integrated circuit that uses a high frequency clock.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a conventional frequency divider. Figure 7
A clock signal is input to the clock input terminal of the flip-flop 4, and the counter circuit 5 is formed by connecting in series the flip-flops 4 that divide the input clock signal by two, and the number of clocks output from the counter circuit. Has reached a predetermined numerical value and resets the counter circuit, a reset condition detection circuit 7, an output waveform synthesizing circuit 6 for obtaining a desired output signal by a logical operation between outputs of the flip-flops, and a final circuit. It is a frequency divider composed of a feedback circuit that feeds back the output of the first-stage flip-flop to the first-stage flip-flop via an inverter. To further explain the principle of operation, in the conventional circuit, by inputting the output data of each flip-flop to the reset condition detection circuit 7 as an output from the counter circuit 5, a decoder built in the reset condition detection circuit 7 previously The number of clock pulses is counted to detect the set frequency division number, a reset pulse is generated when the number of clock pulses corresponding to the predetermined frequency division number is detected, and the counter operation is initialized and counted. The counter is reset so that the output waveform synthesizing circuit 6 forms an output waveform having a clock width of the reset period and outputs it. According to such an operation principle, the conventional circuit obtains an output clock whose output waveform has a waveform whose half cycle is a period in which the cycle of the input clock signal is multiplied by a frequency division number.

[0003]

As described above, in the conventional circuit, since the frequency divider includes the reset condition detection circuit and the like described above, it is possible to prevent the signal from passing through the circuit configuration including the number of gates of about 6 stages. In addition, the circuit delay for this is also a factor that determines the overall operating frequency. The circuit delay is, for example, about 6 stages of gates, and the delay time per stage of gates is assumed to be 1
Assuming ns, the upper limit of the frequency of the input signal is 160 MH
There was a problem that it had to be limited to about z. When a variable frequency divider is implemented so that the frequency division number can be controlled externally, the counter circuit is reset by detecting that the number of clocks of the output of the counter circuit has reached a predetermined value. The scale of the circuit required for doing so becomes larger, as can be seen at first glance from the configuration example of FIG. 8 showing the conventional example, and the number of gate stages described above reaches about 10 stages. Therefore, there is a problem that the upper limit of the frequency of the input signal is further limited to about 100 MHz.

It is an object of the present invention to provide a frequency divider capable of dividing a high frequency clock input,
At the same time, it is an object of the present invention to provide a digital signal processor effective for obtaining an optimum clock by using the frequency divider.

[0005]

In order to achieve the above object, in the present invention, as shown in FIG. 1, for example, N (N is 2
The above cascade connection circuit has cascade connection circuits of the flip-flops 4, and the cascade connection circuits mutually connect the reset signal input terminals of the flip-flops to reset the flip-flops to the same level in advance by a reset signal. Reset terminal RESET and an output clock terminal for obtaining the divided output from the output of the flip-flop of the cascade connection circuit, that is, an OUTPUT-CLOCK terminal,
Further, when the number of frequency divisions is an odd number, odd number frequency division is performed by a characteristic configuration including circuit means 3 that bypasses one stage of the next stage flip-flop in accordance with the output level of a certain stage flip-flop. To do. A (2N-1) frequency division output is obtained from the output of the Nth stage. The cascade connection circuit of the N-stage flip-flops 4 in the present invention constitutes an N-stage shift register to which a clock signal is input.

In the present invention, except for the bypass circuit 3, as shown in FIG. 2, for example, N (N is an integer of 2 or more)
A cascade connection circuit of the flip-flops 4 in stages, and the cascade connection circuit connects reset signal input terminals of the flip-flops to each other and resets the flip-flops to the same level in advance by a reset signal. And an output clock terminal that obtains the divided output from the output of the flip-flop, that is, OUTPUT-
If the terminal of CLOCK is provided, even division can be performed. A 2N frequency division output is obtained from the output of the Nth stage.

In these frequency dividers, for example, as shown in FIG. 3, the output of the feedback circuit is given to the input terminal position of the predetermined stage of the cascade connection circuit in accordance with the control signal for setting the frequency division number. If the circuit means 2 for selecting is provided, the frequency division number can be selected by a simple circuit by selecting the feedback position by the program control signal, which is preferable.

In order to achieve another object, the digital signal processor of the present invention, as shown in, for example, FIG.
A configuration including the above-described frequency divider, which includes circuit means 2 for selecting the output terminal of the feedback circuit at the input terminal position of a predetermined stage of the cascade connection circuit, that is, the frequency divider is shown in FIG.
The variable frequency divider 1 and the variable frequency divider 2 are provided with a means for generating a variable clock by a configuration having, for example, a PLL oscillator (phase locked oscillator).

[0009]

The operation of the circuit of FIG. 2 when the frequency division number is an even number is as follows. The number of stages of the shift register 1 is N.
The initial level of the output is inverted and input to the first stage of the shift register 1. When the input signal of the first stage of the shift register 1 reaches the Nth stage of the shift register 1 by the clock input INPUT-CLOCK, the level of the output terminal OUTPUT-CLOCK of the Nth stage is inverted by the inverter 11. This inverted output level is further applied to the output terminal OUTPUT-CLOC when the clock cycle input corresponding to the number of stages N of the shift register 1 is applied.
Appear in K. Therefore, the input clock signal IN
PUT-CLOCK is divided by 2N and output. If the frequency division number shown in FIG. 1 is odd, the shift register 1
By providing the bypass circuit 3 that bypasses the next stage in accordance with the output level of a certain stage,
High level (or L for UTPUT-CLOCK)
LOW level) is output for the number of clock cycles corresponding to the number of stages of the shift register, and is set to Low level (or High level).
Is output for one clock cycle less than the number of stages of the shift register. As a result, the frequency division number becomes 2N-1. The circuit of the present invention shown in FIG. 1 and the modified circuit of FIG. 2 form a reset signal from the output of the counter circuit 5 through the reset condition detection circuit 7 as in the conventional example shown in FIG. It becomes unnecessary to obtain the output of OUTPUT-CLOCK by synthesizing the output waveforms from the counter circuit 5, and the number of gate stages of the signal path is significantly reduced. For example, in the case of FIG. 2 showing an even frequency divider,
The number of gate stages includes only one stage for the inverter of the feedback circuit, and in the case of the odd frequency divider of FIG. 1, about two stages are added to the odd frequency divider bypass circuit. Not too much. Therefore, it becomes possible to divide the frequency of a clock input having a frequency several times higher than the conventional one, which required about six gate stages.

When it is desired to realize a variable frequency divider by externally controlling the frequency division number, a circuit means for feeding back the inverted shift register output to a predetermined position of the shift register is provided to effectively shift the frequency. The number N of stages of registers can be controlled externally. When the number of frequency divisions is an even number, a circuit for stopping the operation of the bypass circuit of the shift register is provided, so that a variable frequency divider having a number of frequency divisions that is an even number and an odd number is realized. As described above with reference to FIG. 8, the conventional variable frequency divider has a configuration in which a signal passes through a large number of gate stages, such as about 10 stages. By simplifying the circuit configuration so as not to detect the above, the number of gate stages through which a signal passes between the rising edge of a clock and the next rising edge can be reduced to about 3 to 5 at most. For this reason, it is possible to divide the frequency into a frequency several times higher than in the past. Therefore, if such a frequency divider is used as a variable frequency divider to generate the reference clock of the digital signal processor, it is effective for frequency division of a high frequency and optimal clock generation for the processor. In this case, if the configuration of the PLL oscillator as shown in FIG. 6 is used for clock generation by using the above-mentioned variable frequency divider, it becomes possible to obtain a highly accurate clock.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG. 1 and its modification is shown in FIG. 1 shows a frequency divider having an odd number of frequency divisions, and FIG. 2 shows a frequency divider having an even number of frequency divisions. As shown in FIG. 2, in a frequency divider having an even number of divisions, it is initialized to the same level in advance by a reset signal RESET, and the input signal INPUT-
A shift register 1 having CLOCK as a clock and circuit means for inverting its output and feeding back to the input of the shift register 1 are provided. Further, as shown in FIG. 1, in a frequency divider having an odd number of frequency divisions, a shift register 1 which has been initialized to the same level in advance by a reset signal RESET and which has an input signal as a clock INPUT-CLOCK,
A circuit means is provided which inverts the output and feeds it back to the input of the shift register 1, and bypasses one stage of the shift register 1 according to the output level of the shift register 1 when the frequency division number is an odd number. For the sake of explanation, the number of stages of the shift register 1 is N. The initial level of the output of the shift register 1 is inverted and input to the first stage of the shift register 1.
As shown in FIG. 2, in the frequency divider having an even number of frequency divisions, the input signal of the first stage of the shift register 1 is the clock input INPU.
When the Nth stage of the shift register 1 is reached by T-CLOCK, the level of the output terminal OUTPUT-CLOCK is inverted by the inverter 11. This inverted output level is further applied to the output terminal O when the input of the clock cycle corresponding to the number N of stages of the shift register 1 is applied.
Appears in UTPUT-CLOCK. Therefore, the input clock signal INPUT-CLOCK is divided by 2N and output. When the frequency division number shown in FIG. 1 is an odd number, depending on the output level of a stage of the shift register 1,
By providing a circuit 3 that propagates the output to the next stage or the next stage, the output terminal is set to the high level (or L
ow level) is output for the number of clock cycles corresponding to the number of stages of the shift register 1, and low level (or High level) is output for one clock cycle less than the number of stages of the shift register. As a result, the frequency division number becomes 2N-1.

A second embodiment of the present invention is shown in FIG. Figure 3
Is an example of realizing a variable frequency divider by allowing the frequency division number to be controlled externally. The circuit of the embodiment shown in FIG. 1 is provided with circuit means 2 for feeding back the inverted shift register output at a predetermined position of the shift register 1 according to a control signal for setting the frequency division number. Circuit means 2 for feeding back the inverted shift register output to a predetermined position of the shift register
By providing, the number N of stages of the shift register 1 can be effectively controlled from the outside. Further, by providing a circuit for stopping the operation of the bypass circuit 3 of the shift register 1 (corresponding to the selection circuit 25 in FIG. 3) when the number of frequency divisions is an even number, frequency division with an even number and an odd number is performed. A variable number of frequency dividers is realized. FIG. 3 shows a configuration in which the output of the shift register is inverted and fed back to the middle stage of the shift register, which is composed of the shift register 1 of 6 stages and the control circuit, and is selected by the control signals a, b, c, d. It is a variable frequency divider with a frequency division of 3 to 12, which adopts a configuration of selecting an odd number or an even number based on a signal e. Control signal a for setting the frequency division number,
FIG. 4 shows the relationship between b, c, d and e and the frequency division numbers that are set. Control signals a, b, c, d, e are 0, 0,
The operation when 0, 0, 1 is set is shown. It is assumed that the RESET signal is input and the output O1 is set to Low. After that, the output O1 is the input clock INPU.
After T-CLOCK is input 5 times, it becomes High,
When it is input 6 more times, it returns to Low. Therefore, division by 11 is realized. Other output terminals O2, O3, O4, O5, O
Reference numeral 6 is a frequency division output whose phase is different from each other. It is particularly effective when supplying a clock to a system using a multiphase clock. The feature of this circuit is that it can be easily changed even when the clock frequency is high. However, if the number of divisions is limited to an even number, it is possible to divide a clock with a higher frequency. Can be realized. When the controllable frequency division range is, for example, 7 to 12, FIG.
The selection circuits 23 and 24 can be omitted from the configuration shown in FIG. As described above, the frequency divider of the present invention is a frequency divider having an arbitrary frequency division number or a variable frequency divider, by changing the number of stages of the shift register and the position and number of the selection circuit inserted in the middle thereof. In addition, there is a feature that the upper limit value of the frequency of the input clock that can be divided by all the division numbers is almost unchanged. This feature is an extremely important feature in designing, and simplifies a synthesis algorithm when a frequency divider having an arbitrary frequency division number is automatically synthesized by an ASIC (application-specific IC).

As another embodiment of the present invention, an example used in a digital signal processor (hereinafter abbreviated as DSP) is shown below. The clock required by the DSP largely depends on the amount of software processing. Here, it is necessary to design the hardware in parallel with the software development. However, if the frequency of the DSP reference clock that determines the operating speed of the DSP is too slow with respect to the processing amount of the software, the required processing is performed. Cannot be performed, and if it is too fast, power consumption will increase, so it is necessary to set the operating speed to match the amount of software processing. Also usually
Since the system clock input from the outside is determined by one type, it is necessary to be able to change the clock frequency inside the DSP later. Therefore, the variable frequency divider built-in type PL using the variable frequency divider in the PLL oscillation circuit is used.
FIG. 5 shows an L oscillator mounted on a DSP so that the operating speed can be adapted to the processing amount of software by a control signal output to the outside of the DSP. This circuit makes it possible to variably divide a high frequency clock. FIG. 6 shows the configuration of a PLL oscillator with a built-in variable frequency divider. With this configuration, a low jitter clock can be created. However, although this configuration requires a high-speed frequency divider, the circuit configuration of FIG. 6 can be realized by using the frequency divider of the present invention. This circuit makes it possible to create a clock with high accuracy and high frequency. Therefore, it is possible to generate a high-frequency DSP reference clock suitable for the amount of software processing for one type of system clock. As a result, the DSP can be operated at the optimum operating speed, and thus low power consumption can be achieved.

[0014]

According to the present invention, when the frequency division number is an even number, the shift register output is inverted and fed back to the shift register input. The speed performance of the circuit in each case is determined by the delay time of the circuit to be bypassed or, if variable, the delay time of the selection circuit provided to make it variable. In either case, the number of stages of gates that determine the delay time is at most 5 stages, so the speed performance of the frequency divider is improved several times as compared with the conventional one. Further, by using the frequency divider of the present invention, it is possible to provide a variable clock digital signal processor in which a high frequency is divided. This also makes it possible to supply an optimum clock to the digital signal processor.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment (odd frequency divider) of the present invention.

FIG. 2 is a configuration diagram of a modification (even frequency divider) of the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment (variable frequency divider) of the present invention.

FIG. 4 is a chart showing a relationship between a control signal for setting a frequency division number and a frequency division number.

FIG. 5 is a configuration diagram of another embodiment (digital signal processor having a variable clock) of the present invention.

FIG. 6 shows a PLL oscillator with a built-in variable frequency divider.

FIG. 7 is a configuration diagram of a conventional example.

FIG. 8 is a configuration example diagram of a conventional variable frequency divider.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Shift register 2 ... Feedback circuit means for frequency division setting 3 ... Bypass circuit means 4 ... Flip flop for dividing by 2 5 ... Counter circuit 6 ... Output waveform synthesis circuit 7 ... Reset condition detection circuit 11 ... Inverter 21, 22 , 23, 24, 25 ... Return position setting selection circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H03L 7/183 (72) Inventor Yuji Hatano 1-280, Higashi Renegakubo, Kokubunji, Tokyo Hitachi, Ltd. Central In the laboratory

Claims (3)

[Claims] 1. A cascade connection circuit of N (N is an integer of 2 or more) stages of flip-flops, and an output of a flip-flop of a final stage of the cascade connection circuit is connected to an input of a flip-flop of a first stage through an inverter. A feedback circuit and an input clock terminal for connecting a clock input terminal of each flip-flop to each other and applying a clock signal to the feedback circuit are provided, and the clock signal input to the input clock terminal is divided into a predetermined frequency division number. In the frequency divider for outputting, the cascade connection circuit includes reset terminals for connecting reset signal input terminals of the flip-flops to each other and resetting the flip-flops to the same level in advance by a reset signal, and the flip-flops. The output clock terminal that obtains the divided output from the output of 1. A frequency divider comprising circuit means for bypassing one stage of a flip-flop of the next stage in accordance with the output level of the group and performing an odd frequency division. 2. The frequency divider according to claim 1, wherein the output of the feedback circuit via the inverter is provided to the input terminal position of a predetermined stage of the cascade connection circuit according to a control signal for setting the frequency division number. A frequency divider having a selecting means for selecting the frequency divider. 3. A digital signal processor comprising means for generating a variable clock with the configuration including the frequency divider according to claim 2.