JPH07200542A - Vector processor - Google Patents

Abstract

PURPOSE:To improve the performance of a vector processor which successively calculate a series of data stored in a main storage device after supplying them to an arithmetic pipeline by performing the arithmetic processing without deteriorating the overall computing efficiency for the arithmetic pipeline of small throughput and by separating the converging period of a vector macroinstruction from the outrun prevention control in regard of the sum total, the retrieval, etc. CONSTITUTION:If a pipeline that has small throughput compared with other pipelines is detected, a bank management part prescribes the access timing to a vector register of the pipeline. Under such conditions, the pipeline of small throughput uses the timing (SR) set for a memory access pipeline as the access timing (DR1/DR2/DW3) set to the vector register. In addition, a changing part is added on a transmission line of an outrun prevention signal. Thus the outrun prevention signal is variable by a notification signal which notifies a converging period of the relevant instruction.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIG. 19) Problem to be Solved by the Invention (FIG. 19) Means for Solving the Problem (FIGS. 1 and 2) Action Example (a) Description of the first embodiment (FIGS. 3 to 7) (b) Description of the second embodiment (FIGS. 8 to 18)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device for sequentially inputting a series of data stored in a main storage device to a calculation pipeline for calculation.

[0003]

2. Description of the Related Art Generally, in a vector processing device,
For example, the element data b belonging to the vector B₀, b
₁, ... and / or the element data belonging to the vector C
Data c ₀, c₁, ... are calculated by pipeline processing and
A obtained as a result of₀, a₁, ... belong to vector A
Extraction as input data. This place
In case of replacement, it is replaced and loaded from the main memory to the operation pipeline.
Input or replace from arithmetic pipeline to main memory
The access speed of the main memory is restricted
The processing speed is slowed down.

For this reason, it is common practice to provide a vector register having a unit of a plurality of banks and having an interleave structure between the main memory device and the arithmetic pipeline. This vector register is 1
For example, the i-th data and the (i + 1) -th data of the element data belonging to one vector register are configured to be stored in different bank units, and the read output of each bank unit is different from each other. In addition to being configured to be supplied to the operation pipeline via the operation pipeline, the operation result obtained from the operation pipeline is written to each bank unit via different paths.

When there are a plurality of arithmetic pipelines, the number of simultaneously accessible parallel vector registers in response to a request from the arithmetic pipeline is interleaved in units of, for example, 8 banks.
Up to 8 are possible. Therefore, in accessing the vector register from each operation pipeline, access to the vector register is prevented so that the same bank unit is not accessed at the same time, and each bank unit or each operation pipeline operates efficiently.・ It is extremely important to manage the timing.

When storing each element data in the vector register, for example, the above-mentioned element data b
₀ , b ₁ , ..., C ₀ , c ₁ , ... Are conveniently located in different bank units as much as possible because it is convenient to read at the same timing because the data of the same element number is calculated. Is stored as. So in the hardware to access the vector register,
A means for storing the first storage address of each element data (for example, bank information for the 0th element) is required, and an operation for not accessing the same bank unit at the same time is required. The hardware becomes complicated.

Therefore, conventionally, a vector register for storing a plurality of element data in a unit of a plurality of interleaved banks, and an arithmetic pipeline and a memory access pipeline for accessing each element data of the vector register. In a vector processing device having a bank management unit that manages a bank slot indicating the timing at which these pipelines can access each bank unit, a bank slot signal is sent from the bank management unit at the time of activating each pipeline. By doing so, the access timing of each pipeline is regulated (for example, JP-A-57-31).
079).

An example of the bank slot timing in such a conventional vector processing apparatus will be described with reference to FIG. In FIG. 19, B0 to B7
Indicates a unit of 8 banks, and LW indicates a memory
The load pipeline of the access pipeline indicates the timing of writing data from the main memory (memory) to the vector register, and SR is the store pipeline of the memory access pipeline. The timing of reading from the memory to the main memory is shown.

Further, E and F indicate the distinction between bank slots in which, for example, two types of operation pipelines (multiplication or addition pipelines) operate, and R and W attached to each E and F depend on each operand. It corresponds to reading from the vector register to each operation pipeline (READ) and writing from each operation pipeline to the vector register (WRITE), and the numbers 1, 2, and 3 attached to R and W.
Respectively correspond to the numbers of the operands OP1, OP2, OP3 (OP1 * OP2⇒OP3; * is an operator).

Further, (0) to (7) indicate count values. As shown in FIG. 19, ER1, ER2, and EW3 are conventionally assigned to bank slots that are conventionally assigned as fixed pipeline lengths like arithmetic pipelines, and pipeline lengths are undefined like memory access pipelines. LW or SR is assigned to the pipeline.

On the other hand, in the vector processing device, in order to speed up the processing, execution of the subsequent instruction is started without waiting for the completion of the execution of one instruction, but the result operand and the input are input between pipelines having different processing throughputs. If there is a dependency relationship with the operand, it is necessary to perform overtaking prevention control. To accurately check the status of data links between multiple pipelines and perform appropriate overtaking prevention control, the physical impact will be large and the delay time will be large.
Not realistic.

Therefore, a simple method, which lacks appropriateness, has been used conventionally. One of them is a method of applying overtaking prohibition control not only to the target arithmetic pipeline but also to all arithmetic pipelines when performing the overtaking prohibition control when at least one arithmetic pipeline is in the link state. Is. In other words, the conventional overtaking control prevention unit receives the information that the load instruction starts the link operation (also called chaining) from another pipeline from the instruction transmitting / managing unit, and the overtaking control is completed until the load instruction is completed. Activate preventive control. The overtaking prevention control unit is
When it is detected that the throughput may fall below a predetermined throughput due to a memory bus conflict or the like, the execution of the arithmetic pipeline and the store pipeline is suspended by raising the overtaking prevention control signal.

[0013]

By the way, when setting the timing of the bank slot as shown in FIG.
Among fixed length pipelines, the multiplication pipeline and the addition pipeline can obtain the operation result in each cycle, but like the division pipeline, only a few bits of result can be obtained in each cycle. There is also a pipeline (1/3 or less compared to the case of multiplication / addition, for example, 1/7
Throughput).

Such an arithmetic pipeline with a low throughput, that is, an arithmetic pipeline with a small bank usage time required for reading or writing, is a bank slot (ER1, ER2, EW3, FR1, FR2, FW3).
Occupancy of the vector reduces the overall calculation efficiency and lowers the throughput of the entire vector processing device.

Further, in the conventional overtaking prevention control system, the pipeline may be excessively stopped because it does not participate in the operation phase of other pipelines. For example,
In an operation that finally obtains one result, such as a summation instruction, a search instruction, and an extraction instruction, there is a convergence period for collecting intermediate results that occur in the middle of the operation, but such a convergence period is Although it is possible in principle to operate independently of the above-mentioned link operation, in the conventional overtaking prevention control, even the convergence processing is stopped due to the processing stop by the overtaking prevention control signal, There were also problems such as a decrease in processing speed.

The present invention has been made in view of the above problems, and a first object of the present invention is to enable an arithmetic pipeline having a low throughput to perform arithmetic processing without lowering the overall arithmetic efficiency. Thus, it is an object of the present invention to provide a vector processing device aiming to improve the calculation throughput. A second object of the present invention is to perform processing by controlling not to perform overtaking prevention control when the operation pipeline is executing a sequence of convergence processing of vector macro instructions such as summation and search. It is an object of the present invention to provide a vector processing device with an improved speed.

[0017]

FIG. 1 illustrates the principle of the first invention. The vector processing device of the first invention is also basically the same as the conventional vector processing device, and a vector register for storing a plurality of element data in units of a plurality of interleaved banks, and each of the vector registers. Comprised of a plurality of operation pipelines for accessing element data and one or more memory access pipelines, and a bank management unit for managing bank slots indicating timings at which these pipelines can access each bank unit And the arithmetic and memory access pipelines
Each bank of registers is sequentially accessed to process each element data.

In the first invention, when at least one operation pipeline having a lower operation throughput than other operation pipelines is provided in the plurality of operation pipelines, as shown in FIG. The timing (DR1, DR2, DW3) at which the management unit accesses the vector register by the operation pipeline having a low operation throughput among the plurality of operation pipelines is the timing assigned as the memory access pipeline, especially the memory. The store pipeline of the access pipelines is assigned to the bank slot of the read timing (SR) at which the store operation is performed from the vector register to the main memory (claims 1 and 2).
Note that each reference numeral in FIG. 1 is the same as that described above with reference to FIG. 19, but D indicates the distinction of bank slots in which the operation pipeline with low operation throughput operates.

FIG. 2 is a block diagram of the principle of the second invention. In FIG. 2, 21 is a vector register for storing a plurality of element data in a plurality of interleaved banks, and 22 is a vector register. One or a plurality of operation pipelines that use the data on 21 as an input operand or write an operation result to the vector register 21, and 23 is one or more that transfers data from the main memory 24 to the vector register 21. It is a load pipeline.

Further, reference numeral 25 denotes an overtaking prevention control unit, and the overtaking prevention control unit 25 is used by the load pipeline 23 during execution of an instruction for transferring data from the load pipeline 23 to the vector register 21. When the operation pipeline 22 executes a subsequent operation instruction that uses the data written in the register 21 as an input operand, the load pipeline 2 is used to guarantee the execution order of the instructions.
When the condition of the processing of the subsequent arithmetic pipeline 22 overtaking the execution of No. 3 is detected, the execution of all the arithmetic pipelines 22 is suspended.

In the second aspect of the invention, the changing unit 26 is newly provided. This changing unit 26 is a vector
For a vector instruction that requires a read processing period in which data is supplied from the register 21 and a convergence period in which the results are collected after the read processing period, overtaking prevention for the operation pipeline 22 that is executing the convergence processing of the corresponding vector instruction The overtaking prevention control signal output from the overtaking prevention control unit 25 is changed so as not to perform control (claim 3).

The changing unit 26 may be provided in the arithmetic pipeline 22 (claim 4). In addition, the operation pipeline 22 that is executing the convergence processing of the corresponding vector instruction
Is a configuration having a basic arithmetic unit and an additional arithmetic unit for processing convergence, and the convergence processing is executed by the additional arithmetic unit,
During the convergence process, if it is possible to execute another subsequent arithmetic instruction by the basic arithmetic unit, the changing unit 26 during the convergence process.
However, the overtaking prevention control signal may be changed so that the overtaking prevention control is not performed only on the additional arithmetic unit (claim 5).

[0023]

In the vector processing device according to the first aspect of the present invention (claims 1 and 2), even in a fixed length pipeline such as an arithmetic pipeline, a pipeline with a particularly low throughput is used as a memory access pipeline. By sharing with a pipeline that uses only one bank slot, the arithmetic pipelines are overlapped and executed.

In the vector processing device of the second aspect of the present invention (claim 3), when the overtaking prevention control signal is output from the overtaking prevention control section 25, the arithmetic pipeline 2
2 is executing the sequence of the convergence process and while the condition of the convergence period is satisfied, the changing unit 26 changes the overtaking prevention control signal from the overtaking prevention control unit 25, and the operation pipeline 22 in the convergence process is changed. Overtaking prevention control is prohibited.

When the changing unit 26 is provided in the arithmetic pipeline 22, the arithmetic pipeline executing the convergence process ignores the signal for the overtaking prevention control from the overtaking prevention control unit 25. Then, the arithmetic pipeline 22
The overtaking prevention control by the overtaking prevention control unit 25 is prohibited (claim 4). If the arithmetic pipeline 22 in the convergence process has a basic arithmetic unit and an additional arithmetic unit for the convergence process, the changing unit 26 changes the overtaking prevention control signal from the overtaking prevention control unit 25. As a result, the overtaking prevention control is prohibited only for the additional arithmetic unit (claim 5).

[0026]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment FIG. 3 is a block diagram showing a vector processing apparatus as a first embodiment of the present invention. In FIG. 3, 1-0, 1-
1, ..., 1-n are vector registers, and the vector registers 1-0, 1-1, ..., 1-n are interleaved bank units B0, B1, respectively.
, B7 (in this embodiment, a case of 8 banks is shown) stores a plurality of element data.

2 is a main memory 20 and a vector register 1
-0, 1-1, ..., 1-n is a memory access pipeline configured to load or store each element data at high speed, and a load pipeline 2A and a store pipe. Line 2B
have. Here, the load pipeline 2A is
The element data from the main memory 20 is loaded into the vector registers 1-0, 1-1, ..., 1-n, and the store pipeline 2B is a vector register.
This is for storing the element data stored in the registers 1-0, 1-1, ..., 1-n in the main storage unit 20.

3A is a memory access pipeline 2
Write register 3B-0, 3B-1 for writing the element data from the load pipeline 2A in the vector registers 1-0, 1-1, ..., 1-n in each bank unit B0-B7. , 3B-m respectively receives element data (operation result) from operation pipelines 5-0, 5-1, ..., 5-m, which will be described later, in vector registers 1-0, 1-1 ,. It is a write register for writing in each bank unit B0 to B7 in -n.

4A is a vector register 1-0, 1-
A read register for reading the element data stored in 1, ..., 1-n to the store pipeline 2B of the memory access pipeline 2. Also, 4B
-0,4C-0; 4B-1, 4C-1; ...; 4B-m,
4C-m is an operation pipeline 5-0, which will be described later,
A pair of read registers provided for every 5-1, ..., 5-m. Each pair of read registers 4B-0, 4C-0; 4B-
, 4C-1; 4B-m and 4C-m are respectively
In order to input a pair of element data to be operated to the operation pipelines 5-0, 5-1, ..., 5-m, the pair of element data is input to the vector register 1-.
Bank units B0 to B in 0, 1-1, ..., 1-n
It is for reading from 7.

5-0, 5-1, ..., 5-m are operation pipelines, and these operation pipelines 5-0, 5-1,
, -M are a pair of read registers 4B-, respectively.
0,4C-0; 4B-1, 4C-1; ...; 4B-m, 4
The element data input via C-m is subjected to arithmetic processing such as four arithmetic operations, and the arithmetic result (element data) is output.

Further, 6 is an instruction control section for outputting various vector operation instructions, 7 is a bank management section which operates in response to an instruction from the instruction control section 6, and the bank management section 7 is a memory access pipe. Line 2 and operation pipelines 5-0, 5-1, ..., 5-m are vector registers 1
Bank units B0 to 0, 1-1, ..., 1-n
A bank slot counter 7 that manages a bank slot that indicates the timing at which B7 can be accessed, and that regulates the access timing to each bank unit B0 to B7
a.

Next, the general operation of the above vector processing device will be described. In the vector processing device of the present embodiment shown in FIG. 3, each vector register 1-0, 1
-1, ..., 1-n are associated so as to be dispersed in the bank units B0 to B7, respectively. As for the element data stored in each of the vector registers 1-0, 1-1, ..., 1-n, the 0th data is stored in the bank unit B0 and the 1st data is stored in the bank unit B1.
The 7th data is sequentially stored in each bank unit such that the 7th data is stored in the bank unit B7 and stored in the so-called interleaved form, and the data of the same number is stored in the same bank unit. To be done.

For example, the elements belonging to the vector B
The data b ₀ , b ₁ , ... Are assumed to be loaded from the main memory 20 and stored in the vector register 1-1, and the element data c ₀ , c ₁ , ... It is assumed to be stored in the vector register 1-2. In this state, for example, from the instruction control unit 6 to the bank management unit 7, the vector addition instruction “OP1 [# 1V
R (i)] + OP2 [# 2VR (i)] ⇒OP3 [# 0
VR (i)] "is given, the bank management unit 7
As a result, the following processes (see FIG. 4) are executed. In this embodiment, the operation pipeline (addition pipeline) 5-0 has three step stages (see FIG. 4).

Here, # 0VR (i), # 1VR
(I) and # 2VR (i) mean the data stored in each bank unit Bi of the vector registers 1-0, 1-1, 1-2, and the vector addition instruction is the vector register 1- An instruction for adding each element data stored in 1 and each element data stored in the vector register 1-2 and storing the addition result (element data) in the vector register 1-0; Has become.

Timing cycle (bank slot
.Corresponding to the count value counted by the counter 7a
In T0, T1, ..., bank units B0,
Read access to B1, ..., B7 ,.
Is performed, and as a result, the read registers 4B-0 and 4C-
Element data b through 0₀, b₁, ... and c ₀,
c₁, ... are the vector registers 1-1 and 1-2 in sequence
Read from.

In timing cycle T2, data b ₀ and c ₀ are input to step I of arithmetic pipeline 5-0. In timing cycle T3, data b ₀ and c
₀ is input to step II of the operation pipeline 5-0, and at the same time, the data b ₁ and c ₁ are input to the operation pipeline 5
Input to step I of -0.

In the timing cycle T4, the data b ₀ and c ₀ are the steps of the operation pipeline 5-0.
The data b ₁ and c ₁ are input to step III of the operation pipeline 5-0, and at the same time,
₂ and c ₂ are input to step I of the operation pipeline 5-0. In timing cycle T5, data b ₀ and c
_The data a ₀ which is the addition result with ₀ is written in the write register 3B-
It is set to 0.

At timing cycle T6, this data a ₀ is written to the bank unit B0 of the vector register 1-0. Hereinafter, the data a ₁ ,
a _2, ... it is set in the write register 3B-0, the write register 3B-0 to the set data a _1, a _2, ..., respectively, per bank of vector registers 1-0 B1, B
2, ..., B7, B0 ,.

Here, in the operation pipeline 5-0, the timing is adjusted to the input side of the element data belonging to the vectors B and C so that the element data having the same number (subscript number) is input to the step I. There is provided one stage of buffer register for. With this configuration, addition is made for the vectors B and C,
The resulting vector A is assigned to bank units B0, B1,
It becomes possible to access in order.

Next, in order to simplify the access control to each of the bank units B0 to B7, the bank management unit 7 that performs the access control will be described with reference to FIGS. In FIG. 5, 11-1, 11-2, 11
-3 is a memory access pipeline 2 or an operation pipeline 5-0, 5-1, ..., 5-m is a vector
A management register for storing timing cycles (hereinafter referred to as bank slots) for accessing the registers 1-0, 1-1, ..., 1-n, 12 is a bank slot allocation circuit, and 13 is memory access for storing bank slots.・
A notification register 14 for notifying the pipeline 2 is a start signal controller.

In the bank management unit 7, each bank unit B0 to B0
Pipeline device for accessing B7 (memory access pipeline 2 or operation pipeline 5-0,
5-1, ..., 5-m) does not access the same bank unit at the same time, and further, in order to realize access control that enables efficient access with no wasted idle time, By constantly counting the slot counter 7a (one provided),
Timing cycle T0 called bank slot
T7 is specified and the counter output signal is notified to each pipeline device.

At this time, since the timing of accessing the bank B1 is delayed by one cycle from the bank B0, when the count value of the main counter 7a is "1", the bank B0 is accessed one cycle before. The pipeline that was being accessed accesses bank B1. Therefore, the count value of the bank slot counter 7a indicates the order of pipelines that access the bank B0.

Each management register 11-1, 11-2, 11
-3 is, for example, a 3-bit storage element (for example, a 3-bit storage element that stores a bank slot number (B1) assigned at the time of activation for a channel (access request) for data transfer in each bank unit of each pipeline device. Actually 1 more for valid / invalid display of stored contents
(Bits are required), and the pipeline device has vector registers 1-0, 1-1, ..., 1-n.
The bank slot number assigned to the channel (access request) is stored during the access to the.

The bank slot allocation circuit 12 uses the outputs of the management registers 11-1, 11-2, 11-3 and the output of the bank slot counter 7a to determine the bank slot number in use and the current bank slot number. Know
It is a selection circuit that assigns a bank slot number that minimizes the idle time to a pipeline device that is activated.

Here, the instruction control unit 6 causes the bank management unit 7 to operate.
Suppose that the memory access pipeline 2 requests the main memory 20 to transfer the read data to the vector register 1-0. At this time, the bank slot allocation circuit 12
At the time of starting the memory access pipeline 2, the selected bank slot number is transmitted and stored as a set number in the management registers 11-1, 11-2, 11-3 corresponding to the channel (access request). .

FIG. 6 is for explaining the above-mentioned operation in detail. As shown in FIG. 6, when the memory access pipeline 2 is activated by the activation signal, the element data a ₀ , a ₁ , ..., A _n (assumed to be stored in the main storage unit 20) is started, and after the access time t _A , the memory access is started.
The read contents are loaded into the buffer register (not shown in FIG. 5) of pipeline 2.

Since a predetermined bank slot (see FIGS. 1, 7, and 19) is assigned to each pipeline device, the output of the bank slot counter 7a is referred to in each pipeline device, when it becomes the desired timing, buffer register for temporary storage to have the element data _{a 0, a 1, ...,} a n vector registers 1-0, sequentially transferred to .... When the last data is transferred, a reset signal is sent to the bank management unit 7 by the pipeline end signal, and the contents of the management register 11-1 or 11-2, 11-3 corresponding to the transfer channel are reset and invalidated. .

The buffer / register is the main storage unit 2.
A plurality of registers for adjusting the timing for strobing the read output of 0 and the period until writing to the vector registers 1-0, ... Also,
In the above-mentioned example, considering that the main storage unit 20 is in a busy state or the like due to a request from another access device,
The time from starting up to using the vector register 1-0 is not constant. That is, in the above example, the pipeline length can be an indefinite device, and the operation pipelines 5-0, 5-1, ..., 5-m have a fixed number of steps (that is, pipeline length). The time from activation to use of the vector register 1-0 is constant regardless of the status of the main storage unit 20. In this case, as described in FIG. 4, the operation pipelines 5-0, 5-1 and
, 5-m have a fixed timing relationship for accessing the vector register 1-0.

Therefore, by recognizing a shift in access timing between channels (access requests) in a device having a fixed pipeline length, as shown in FIG. 5, the activation signal controller 14 is in use. Based on the bank slot number, the contents of the bank slot counter 7a and the activation signal, the timing of the activation slot can be used to determine the timing of the bank slot.

Now, in the present embodiment, in the vector processing device which performs the general operation as described above, other arithmetic operations are performed in a plurality of arithmetic pipelines 5-0, 5-1, ..., 5-m. When a division pipeline 15 (a pipeline including six dividers 5a to 5f) is provided as an operation pipeline having a lower operation throughput than the pipeline, the bank management unit 7 operates as shown in FIG. As shown in, the bank slot is managed.

That is, in the bank management unit 7, each of the division pipelines 5a to 5f is a vector register 1-0, 1-.
1, ..., 1-n access timing (DR1, D
R2, DW3) to the memory access pipeline 2
Of the vector registers 1-0, 1-1, ..., 1-n are assigned to the bank slot of the read timing (SR) for the store operation to the main memory 20.

In FIG. 7, the reference numerals are the same as those described above with reference to FIG. 19, but DR1 and DR2 indicate the timing of the read operand in the division pipeline 15, and DW3 indicates the timing in the division pipeline 15. The timing of the write operand is shown. Timing is used in a time division manner while the division pipeline 15 is operating. Further, the division pipeline 15 and the store pipeline 2B are controlled so that only one of them operates. Further, E and F are arithmetic pipelines 5-0 and 5-
The allocation timing of the bank slot in which the addition pipeline or the multiplication pipeline of 1, ..., 5-m operates is shown.

In this embodiment, as shown in FIG. 7, when two types of operation pipelines are operating, each divider 5a-5 of the division pipeline 15 is divided by bank units B0-B7.
f arrives every 16 timing cycles, store
Pipeline 2B is a vector register 1-0, 1-
The calculation processing by the division pipeline 15 is executed by sharing the bank slot of the read timing SR for performing the store operation from 1, ..., 1-n to the main storage unit 20.

For example, in the divider 5a in the division pipeline 15, the first store read timing SR (timing cycle T4) of the bank unit B0 and the bank unit B0.
1 first store read timing SR (timing cycle T5) and vector registers 1-0, 1-1,
.., 1-n is read (DR1, DR2). Then, at the store read timing SR (timing cycle T5) of the second cycle of the bank unit B1 after 16 timing cycles, the division result is transferred to the vector registers 1-0, 1-1, ..., 1-n. After the writing (DW3) is performed, the second cycle store read timing SR of the bank unit B2 (timing cycle T6) and the second cycle store read timing SR of the bank unit B3 are again performed.
(Timing cycle T7), read data from the vector registers 1-0, 1-1, ..., 1-n (D
R1, DR2) is performed, and the same processing is repeated thereafter.

Also, the divider 5 in the division pipeline 15
Also in b, similarly, the vector store 1-0, 1 with the first store read timing SR (timing cycle T7) of the bank unit B3 and the first store read timing SR (timing cycle T0) of the bank unit B4.
Reading data from -1, ..., 1-n (DR1, DR
2), and at the second cycle of the store read timing SR (timing cycle T0) of the bank unit B4 after 16 timing cycles, the division result vector registers 1-0, 1-1, ..., 1- Writing to n (DW3) is performed, and the same processing is repeated thereafter. Other divider 5
Similarly, for c, 5d, 5e, and 5f, timing allocation is performed and division processing is performed.

As described above, according to the vector processing device of the first embodiment of the present invention, even in a fixed length pipeline such as an arithmetic pipeline, a pipeline with a particularly low throughput, for example, the division pipeline 15 is used. , The memory access pipeline 2 and the pipeline that uses only one bank slot, the arithmetic pipelines can be overlapped and executed, and the arithmetic processing can be performed without lowering the overall arithmetic efficiency. The calculation throughput will be greatly improved.

In particular, among the memory access pipelines 2, the load pipeline 2A for reading from the main memory 20 serves as the source of the operation, and therefore the store pipeline 2B for storing the result operand. It is possible to improve the throughput of the entire vector processing device by using the same bank slot.

In the above embodiment, the case where the pipeline with low throughput is the division pipeline has been described, but the present invention is not limited to this, and the pipeline with low throughput is a square pipeline.
It is similarly applied to the case of a root (square root) operation pipeline or the like, and the same effect as the above-described embodiment can be obtained.

(B) Description of Second Embodiment FIG. 8 is a block diagram showing a vector processing device as a second embodiment of the present invention. In FIG. 8, 21 is a plurality of interleaved banks. Vector register (VR) for storing element data, 22-1, 22-2
, 22-n are operation pipelines that use the data in the vector register 21 as an input operand or write the operation result to the vector register 21.

23-1, 23-2, ..., 23-m
Is a memory access pipeline constituted by a pipeline for loading or storing each element data at high speed between the vector register 21 and the main memory unit 24. Each memory access pipeline 23-
, 23-m have a function as a load pipeline 23A and a store pipeline 23B. Where the load pipeline 23A
Is for transferring (loading) data from the main memory unit 24 to the vector register 21, and the store pipeline 23B transfers (stores) the data stored in the vector register 21 to the main memory unit 24. ) To do so.

It should be noted that each memory access shown in FIG.
In the pipelines 23-1, 23-2, ..., 23-m,
Load pipeline 23A and store pipeline 2
3B and 3B are provided as a pair, but a configuration having only one of them may be adopted. Also, the memory access pipelines 23-1, 23-2, ..., 23-m
Either of the above may have only one of the load pipeline 23A and the store pipeline 23B.

Reference numeral 25 denotes an outpacing prevention control unit, which is a memory access pipeline 23.
Input the data written to the vector register 21 by the load pipeline 23A during the execution of the instruction to transfer the data from the load pipeline 23A to the vector register 21 at -1, 23-2, ..., 23-m. Subsequent operation instructions that are used as operands are processed by the operation pipeline 22.
When any of -1, 22-2, ..., 22-n is executed, a condition is detected that the processing of the subsequent operation pipeline overtakes the execution of the load pipeline 23A in order to guarantee the execution order of the instructions. At this time, in order to temporarily suspend the execution of all the arithmetic pipelines 22-1, 22-2, ..., 22-n, for example, while requesting the temporary suspension of the processing, it rises to “1” to execute the processing. When it is possible to continue, the overtaking prevention control signal which becomes "0" is output.

27 is each operation pipeline 22-1, 22
-2, ..., 22-n and the memory access pipelines 23-1, 23-2 ,. When issuing an instruction, the management unit 27 checks whether or not there is a link of an operand register with an instruction that has started execution before the instruction is issued and has not yet completed execution, and If there is, it has a function of notifying the overtaking prevention control unit 25 as link information that the link condition is satisfied.

Then, in the second embodiment, the overtaking prevention control signal changing unit 26A and the convergence period notifying unit 26B as shown in FIG. 9 are provided in the respective operation pipelines 22-1, 22-2.
..., provided every 22-n. The overtaking prevention control signal changing unit 26A converges the corresponding vector instruction for a vector instruction that requires a read processing period in which data is supplied from the vector register 21 and a convergence period in which results are collected after the read processing period. Operation pipelines 22-1, 22-2, ..., 22- executing processing
The overtaking prevention control signal output from the overtaking prevention control unit 25 is changed so that the overtaking prevention control for n is not performed.

The convergence period notifying section 26B has a start final sequence (start final sequence; for example, a pulse signal which rises at the start of the convergence period) of each operation pipeline 22-1, 22-2, ..., 22-n. And whether each of the operation pipelines 22-1, 22-2, ..., 22-n is in the above-mentioned convergence period, based on the end signal of the convergence period (terminal final sequence; for example, a pulse signal rising at the end of the convergence period). Whether or not to output as a convergence period notification signal to the corresponding overtaking prevention control signal changing unit 26A,
For example, it is configured as shown in FIG.

In FIG. 9, 26a is an OR gate and 26a.
b is an AND gate, 26c is a flip-flop, 26e
Is an inverter (NOT gate), and the OR gate 26
a is the logical sum of the start signal and the data output from the flip-flop 26c, and the AND gate 26b
Is a logical product of the logical sum output from the OR gate 26a and the inverted signal of the end signal from the inverter 26e.

The flip-flop 26c is ANDed.
The data output is raised to "1" according to the logical product output from the gate 26b. When the start signal is input to the OR gate 26a, the data output of the flip-flop 26c is raised and set to "1". On the other hand, when the end signal is input to the AND gate 26b, the data output of the flip-flop 26c is reset from "1" to "0". That is, the flip-flop 26
The data output of c (convergence period notifying means) rises to "1" while each of the operation pipelines 22-1, 22-2, ..., 22-n is executing the convergence process (during the convergence period).

Then, the overtaking prevention control signal changing unit 26A
The AND gate 26d that forms the logical AND of the overtaking prevention control signal generated by the overtaking prevention control unit 25 and the inverted signal by the inverter (NOT gate) 26f of the data output (convergence period notifying means) of the flip-flop 26c. However, since the data output of the flip-flop 26c is "1" during the convergence period, the overtaking prevention control signal is forcibly changed to "0" by the AND gate 26d, while the data of the flip-flop 26c is changed. Output is "0"
At this time, the overtaking prevention control signal is output as it is.

Next, the operation of the vector processing device configured as described above will be described with reference to FIGS. [Description of Operation of Corresponding Instruction] First, the operation of the corresponding instruction will be described. However, depending on the actual implementation, the operation may be slightly different from the operation described here. A sum operation instruction for calculating the sum of the data in the vector register 21,
In the search operation instruction for obtaining the maximum value or the minimum value of the data in the vector register 21, the original data is supplied from the vector register 21.

In the sum operation instruction, the cumulative sum is sequentially obtained, but in order to improve the processing speed, the partial cumulative sums for the stages of the pipeline are generated only for the multiple arithmetic units. Next, these partial sums are all added to obtain the result of the summation operation. In the total sum calculation, the period during which the process of adding the partial sums is executed is the convergence period. In the search operation instruction, comparison and selection are sequentially performed, but in this case as well, after the partial selection results for the number of stages are generated for the arithmetic units having multiple, these partial selection results Finally, one result is sought. In the search operation,
The convergence period is a period for executing an operation for obtaining one final result from the partial selection results.

Since the processing in these convergence periods is the processing in which the data supply from the vector register 21 is not received, the overtaking prevention control by the link of the vector register 21 is unnecessary. [Description of General Overtaking Prevention Control] An example of the portion of the vector processing device that controls the overtaking prevention control is as follows. When the command transmission / management unit 27, which manages the command transmission and the progress status, transmits a command, it executes an operand between the command that has been executed before the command is transmitted and has not yet been executed. It is checked whether there is a register link, and if there is a link, the overtaking prevention control unit 25 is notified that the link condition is satisfied.

This link condition is canceled when the register link is canceled by completing the execution of the preceding instruction for writing the data to the vector register 21 in which the link is established. When there are a plurality of register links, the link condition is released when all the register links are released. When it is detected that the data writing of the preceding instruction is interrupted while the link condition is satisfied, the overtaking prevention control unit 25 is activated. The overtaking prevention control unit 25 notifies all the operation pipelines 22-1, 22-2, ..., 22-n and the store pipeline 23B to suspend the processing. However, regarding the pipeline that is the starting point (parent) of the link, the interruption of processing is not notified. When the data writing of the preceding instruction is restarted or the preceding instruction is completed, the overtaking prevention control unit 25 causes all the operation pipelines 22-1, 22-2, ..., 22-n and the store pipeline 23B. Notify and to restart processing.

Actually, each operation pipeline 22-1,
The throughputs of data read from the vector registers 21 of 22-2, ..., 22-n are made equal in any of the operation pipelines 22-1, 22-2 ,. It does not require dynamic overtaking prevention control. Therefore, the pipeline that is the parent of the link whose throughput changes is limited to the load pipeline 23B. Arithmetic pipelines 22-1 and 22
The prevention of overtaking between −2, ..., 22-n is avoided by instructing all arithmetic pipelines 22-1, 22-2 ,. ing.

Note that due to the implementation, a low-throughput arithmetic pipeline actually exists on the vector processing device. In such a case, this low-throughput pipeline is usually controlled at the stage of issuing an instruction so as to prohibit the link operation with other pipelines. However, in the control for pursuing higher performance, even if the pipeline has low throughput, the link operation may be limited.

As an example, if the throughput of the pipeline processing the preceding instruction is high or equal, it is possible to perform the link operation of reading the write result of the pipeline. What is prohibited is that the high throughput pipeline operates by linking to the low throughput pipeline by using the write result of the low throughput arithmetic pipeline.

[Explanation of Read Processing Period] In the read processing period, the data processed first by the command from the command transmission / management unit 27 is processed by the operation pipelines 22-1 and 22-2.
2-2, ..., 22-n starts when the data is received from the vector register 21, and the data to be processed last by the instruction is calculated by the operation pipelines 22-1, 22-2 ,.
Complete when -n is received from vector register 21.

[Overtaking prevention control signal changing unit 26A (A
Description of a case in which the ND gate 26d) is provided for the overtaking prevention control unit 25 side and the convergence period notification unit 26B is provided for the command transmission / management unit 27 side] Then, each operation pipeline 22-1, 22
A function of notifying that the processing of 2, ..., 22-n has entered the convergence period together with the operation pipeline information and a function of notifying that the processing of the convergence period has been completed together with the operation pipeline information are added. That is, the function as the convergence period notification unit 26B described above with reference to FIG. 9 is provided in the command transmission / management unit 27.

Further, the overtaking prevention control unit 25 has a function of notifying a temporary interruption of processing (overtaking prevention control signal) to each of the arithmetic pipelines 22-1, 22-2, ..., 22-n. 22-1, 22-2, ..., 22
Although it is provided for each −n, the overtaking prevention control unit 25
In each of the operation pipelines 22-1, 22-2, ..., 22-n, an operation pipeline in the convergence period is provided with an overtaking prevention control signal changing unit 26A for each signal line for outputting the overtaking prevention control signal in FIG. Is not notified of a temporary interruption of processing (overtaking prevention control signal).

Specifically, the command issuing / management unit 27
When the instruction is decoded and it is detected that the instruction has a convergence period, the operation pipeline 22- that issues the instruction
A flag indicating that the instruction has a convergence period is set in a management unit (not shown) of 1, 22-2, ..., 22-n. The calculation pipeline side management unit calculates the time required for the read period from the vector length, and uses the information by the function of notifying the temporary interruption of the process from the overtaking prevention control unit 25 to accurately grasp the read processing period. .

Since the convergence period is started with the completion of the read processing period, at this time, the convergence period notification unit 26B notifies the overtaking prevention control unit 25 of the operation pipelines 22-1 and 22-2. , ..., 22-n is notified that it has entered the convergence period. The convergence period notification signal notified at this time is, as described above, the operation pipelines 22-1, 22-2, ..., 2 during the convergence period.
The signal line corresponding to 2-n rises to "1", and otherwise becomes "0".

Then, as described above, the overtaking prevention control signal changing section 26A is provided on the signal line for outputting the overtaking prevention control signal.
By providing the AND gate 26d that forms the AND gate 26d, when the convergence period notification signal (data output of the flip-flop 26c) from the corresponding operation pipeline 22-1, 22-2, ... The prevention control signal directly passes through the AND gate 26d and is notified to the corresponding operation pipelines 22-1, 22-2, ..., 22-n, while the corresponding operation pipelines 22-1, 22-
When the convergence period notification signal from 2, ..., 22-n is "1", the overtaking prevention control signal is changed to "0" by the AND gate 26d, and then the corresponding operation pipelines 22-1, 22-2 , ..., 22-n are notified.

As a result, as shown in FIG.
Although the processing that was completely interrupted even during the convergence period at the time of outputting the overtaking prevention control signal, in the present embodiment, the operation pipeline in the convergence period receives the changed overtaking prevention control signal, As shown in 11,
It will be executed without interruption. [Explanation of Operation when Providing Overtaking Prevention Control Signal Changing Unit 26A and Convergence Period Notifying Unit 26B on Each Operation Pipeline Side] Here, each operation pipeline 22-1, 22-2
, 22-n is provided with an overtaking prevention control signal changing unit 26A and a convergence period notifying unit 26B, and based on the sequencer (start signal, end signal) of each operation pipeline itself,
The convergence period notification unit 26B detects that the user is in the convergence period, and during the convergence period, the overtaking prevention control signal changing unit 2
6A is used to change the overtaking prevention control signal from the overtaking prevention control unit 25 to each of the operation pipelines 22-1, 22-2, ..., 22-n from “1” to “0”.

The arithmetic pipelines 22-1 and 22
An internal sequencer (not shown) for controlling the data flow so that the instruction, the vector length, and the activation signal can be received and the processing can be executed is provided in each of -2, ..., 22-n. This internal sequencer is capable of smoothly executing the sequence chain procedure associated with the instructions so that it can execute various sequences of instructions for controlling the data flow.

The convergence period notifying unit 26B receives information on the end of the read processing period and the start of the convergence period from the internal sequencer, and when it is outside the convergence period, the overtaking prevention control signal changing unit 26A (AND gate 26d) Although the overtaking prevention control signal is passed as it is, the overtaking prevention control signal is changed to “0” during the convergence period for the corresponding arithmetic pipeline.

As a result, even when the overtaking prevention control signal changing unit 26A and the convergence period notifying unit 26B are provided on the respective operation pipeline sides as described above, conventionally, as shown in FIG. At the time of output, the processing that was completely interrupted even in the convergence period is
By receiving the changed overtaking prevention control signal, the arithmetic pipeline in the convergence period can be executed without interruption as shown in FIG.

[Example of Arrangement of Arithmetic Pipeline and Description of Its Operation] Here, as an example of an arithmetic pipeline, as shown in FIG. 13, the pipeline type adders 22a to 22d each including four stages are As shown in FIG. 12, a total operation pipeline 22A having four pieces is shown. In FIG. 13, 28a is a first stage register, 28b is a second stage register, 28c is a third stage register,
28d is a fourth stage register, 28e is a transfer relay register, 29 is a selector, 30 is an exponent difference calculation means, 3
1 is a digit alignment means, 32 is an addition / subtraction means, and 33 is a normalization means. Further, with respect to the number of stages of the adders 22a to 22d and the number of adders, an optimal number of stages is prepared for each processing device, and the adder is used as a comparison / selection means depending on an instruction to be processed (search operation instruction etc.). You can also

The first stage of each of the adders 22a to 22d executes the exponent comparison process prior to the digit alignment, and the second stage executes the digit alignment process. The third stage executes addition / subtraction processing. The fourth stage is a normalization process. Adder 22
a processes an element whose remainder is 0 due to the data element number 4 in the vector register, and the adder 22b
Of the element number 4 processes the element whose remainder is 1, the adder 22c processes the element whose remainder by 2 of the element number 4 is 2, and the adder 22d processes the element whose remainder by the element number of 4 is 3. Is configured.

Further, in order to combine the adders 22a to 22d into one, the adders 22b to 22d are added to the adder 22a.
The result can be transferred to. In the summing operation, during the read processing period in which the data is supplied from the vector register 21, the data of the fourth stage is returned to the first stage, and the adders 22a to 22d are added.
Operates as a cumulative sum adder. Also, four adders 22
a to 22d operate in parallel. During the final read processing period, four partial sums are generated in each of the adders 22a to 22d.

In the adder 22a, Σ (E_16i), Σ (E
_{16i + 4}), Σ (E_{16i + 8}), Σ (E _{16i + 12}) 4 types
Partial sums are generated. Where E_iIs the element number i
Is the value of the data element of. In the convergence period, each part
There can be many ways to organize the disintegration, but here
Then, an example thereof is shown in FIG.

First, in each of the adders 22a to 22d, four partial sums are added up to generate one partial result. The four partial results are then added together to compute the final result. Here again, the manner in which the partial result is generated will be described taking the adder 22a as an example. At the moment of entering the convergence period, which partial sum is in which stage depends on the VL length, and therefore emptying is performed until the partial sum of Σ (E _16i ) is set in the first stage register 28a. Guarantee the calculation order. The partial sum Σ (E _16i ) is held for 2τ by the first stage register 28a.

In the meantime, the other cash register of the first stage
The partial sum Σ (E_{16i + 4}) Is set. part
Sum Σ (E_16i) And partial sum Σ (E_{16i + 4}) The first stage
From the second stage to start the addition process
And the partial sum Σ (E_{16i + 8}) Is the first stage register 2
Set to 8a and hold for 2τ. Partial sum Σ
(E_{16i + 8}) Hold another stage
The partial sum Σ (E_{16i + 12})
It Then, the partial sum Σ (E_{16i + 8}) And partial sum Σ (E
_{16i + 12}) And are added.

Then, the partial sum {Σ (E _16i ) + Σ (E
_{16i + 4} )} is set in the first stage register 28a and held for 3τ. Meanwhile, the partial sum {Σ (E
_{16i + 8} ) + Σ (E _{16i + 12} )} is set in the other first stage register 28a and addition processing is executed to obtain the intermediate result of the adder 22a. The operation of obtaining the intermediate sum during the convergence period is performed in parallel by each of the adders 22a to 22d.

The operation for obtaining the final result is executed by the adder 22a. In the adder 22a, the intermediate sum of the adder 22a is held in the first stage register 28a, and the intermediate sum of the adder 22b is stored in the other first stage register.
Wait for the register 28a to be set. Then, the intermediate sums of the adder 22a and the adder 22b are added to obtain the intermediate sum A. This intermediate sum A is held on the first stage register 28a and waits until the intermediate sum of the adder 22c is set on the other first stage register 28a. Then, the intermediate sum A and the intermediate sum of the adder 22c are added to generate the intermediate sum B. This intermediate sum B
Is held by the first stage register 28a and waits for the intermediate sum of the adder 22d to be set in the other first stage register 28a. Then, the intermediate sum B and the intermediate sum of the adder 22d are added to generate a final result.

[Explanation of an embodiment in which the present invention is applied to an operation pipeline with an additional operation unit] Next, each operation pipeline 22-1, 22-2, ..., 2
2-n has a configuration including a basic computing unit and an additional computing unit that processes convergence (see, for example, FIG. 17), the convergence process is executed by the additional computing unit, and during the convergence process, A case will be described in which another operation instruction can be executed.

Even in such a case, during the convergence period from the disconnection from the basic arithmetic unit to the convergence period until the completion of the instruction, the additional arithmetic unit has the overtaking prevention control unit 25.
To arithmetic pipelines 22-1, 22-2, ..., 22
The overtaking prevention control signal changing unit 26A does not accept the information (overtaking prevention control signal) by the means for notifying the temporary interruption of the processing for -n.

When the additional arithmetic unit is used, the internal sequencer is also divided into a basic arithmetic unit and an additional arithmetic unit. The internal sequencer of the additional arithmetic unit is activated from the internal sequencer of the basic arithmetic unit, and receives a notification that the internal sequencer of the additional arithmetic unit will be disconnected from the basic arithmetic unit when the convergence period starts. The internal sequencer of the additional computing unit is
When separated from the basic computing unit, the sequence for convergence is activated.

The convergence period notifying section 26B receives the information about the end of the read period and the start of the convergence period from the internal sequencer of the additional arithmetic unit, and the overtaking prevention control signal changing section 26.
According to A, the passing control signal is passed as it is during the period other than the convergence period.
During the convergence period for the additional arithmetic units 2-1, 22-2, ..., 22-n, the overtaking prevention control signal is changed to "0".

Regarding the basic arithmetic unit, after the additional arithmetic unit is separated, the instruction transmitting / managing unit can execute the arithmetic that does not require the additional arithmetic unit until the additional arithmetic unit completes the arithmetic operation. Waiting for activation from 27. The additional computing unit completes the instruction and the basic computing unit completes the read processing period of the instruction that does not use the additional computing unit, or both the additional computing unit and the basic computing unit complete the execution of the instruction. If so, the operation pipeline 2
22-1, 22-2, ..., 22-n can execute an instruction using an additional arithmetic unit.

As a result, as for the operation pipeline with the additional operation unit for performing the convergence processing, as shown in FIG. 15, conventionally, the processing which was completely interrupted even during the convergence period at the time of outputting the overtaking prevention control signal. However, in this embodiment,
By receiving the changed overtaking prevention control signal, the additional arithmetic unit of the arithmetic pipeline in the convergence period can be executed without interruption as shown in FIG.

[Structural Example of Arithmetic Pipeline with Additional Arithmetic Unit and Description of Its Operation] Here, as an example of the arithmetic pipeline with an additional arithmetic unit, as shown in FIG. 17, a pipeline including four stages is shown. Expression-based arithmetic unit (having the same configuration as the adder shown in FIG. 13) 34a to 34d and a pipeline-type additional arithmetic unit (having the same configuration as the adder shown in FIG. 13) consisting of four stages ) 35a to 35d are combined with each other, and a total operation pipeline 22B having four complex operation units 36a to 36d is shown.

With respect to the number of stages and the number of adders, an optimal number of stages is prepared for each processing device, and the adder can be used as the comparison / selection means depending on the instruction to be processed (search operation instruction, etc.). Further, similarly to the above-mentioned one, the first stage of each of the arithmetic units (adders) 34a to 34d and 35a to 35d executes the exponent comparison process prior to the digit alignment, and the second stage executes the digit alignment process. The third stage executes addition / subtraction processing. The fourth stage is a normalization process.

The complex computing unit 36a is the vector register 2
The remainder due to the data element number 8 in 1 is 0 and 1
, The composite arithmetic unit 36b processes the elements having the remainders 2 and 3 due to the element number 8, and the composite arithmetic unit 36c processes the elements having the remainders 4 and 5 due to the element number 8 to perform the composite arithmetic operation. The device 36d is configured to process the elements whose remainders by the element number 8 are 6 and 7.

In order to combine the results of the additional adders 35a to 35d into one, the results can be transferred from the additional adder 35b, the additional adder 35c, and the additional adder 35d to the additional adder 35a. Has become. Then, during the read processing period, the basic arithmetic unit 34 including the basic arithmetic units 34a to 34d calculates the sum of two consecutive elements, and the additional arithmetic unit 3 including the additional arithmetic units 35a to 35d.
Transfer to 5. The additional calculation unit 35 adds the intermediate sum received from the basic calculation unit 34. At the end of the read period, four partial sums have been generated in the additional calculation unit.
Taking the complex computing unit 36a as an example, these four partial sums are
Σ (E _32i + E _{32i + 1} ), Σ (E _{32i + 8} + E _{32i + 9} ),
Σ (E _{32i + 16} + E _{32 i + 17} ), Σ (E _{32i + 24} + E _{32i + 25} )
Becomes Here, E _i is the value of the data element of the element number i.

When the convergence period starts, the additional arithmetic unit 35 stops accepting data from the data bus of the basic arithmetic unit 34. Subsequently, the intermediate result is calculated from the four partial sums, and finally the final result is calculated from the four intermediate results. The procedure for obtaining the intermediate result will be described with reference to FIG.

First, in order to guarantee the operation order, the partial sum
Σ (E_32i+ E_{32i + 1}) Is the first stage register 28
Do emptying until you come to the top. The partial sum is the first step
It is held for 2τ on the charge register 28a. That
Partial sum Σ (E_{32i + 8}+ E _{32i + 9}) Another first
It is set in the stage register 28a. And part
The calculation of the sum A is started.

Next, the partial sum Σ (E _{32i + 16} + E _{32i + 17} ) is set in the first stage register 28a and held for 2τ. Meanwhile, the partial sum Σ (E _{32i + 24} + E _{32i + 25} ) is set in the other first stage register 28a. Then, another partial sum B is calculated. Partial sum A
Is held in the first stage register 28a for 2τ, while the partial sum B is set in the other first stage register 28a and the intermediate result is calculated.

The operation for obtaining the intermediate result during the convergence period is performed in parallel by each of the additional arithmetic units 35a to 35d. The calculation for obtaining the final result is executed by the additional calculator 35a. The additional arithmetic unit 35a holds the intermediate result of the additional arithmetic unit 35a in the first stage register 28a and waits for the intermediate result of the additional arithmetic unit 35b to be set in the other first stage register 28a.
Then, the intermediate results of the additional arithmetic unit 35a and the additional arithmetic unit 35b are added together to obtain an intermediate result A. The intermediate result A is held on the first stage register 28a and waits for the intermediate result of the additional arithmetic unit 35c to be set on the other first stage register 28a.

Then, the intermediate result A and the intermediate result of the additional operator 35c are added to generate the intermediate result B. This intermediate result B is held by the first stage register 28a, and the intermediate result of the additional arithmetic unit 35d is the other first result.
Wait for the stage register 28a to be set. Then, the intermediate result B and the intermediate result of the additional operator 35d are added to generate a final result.

As described above, according to the vector processing device of the second embodiment of the present invention, when the overtaking prevention control signal is output from the overtaking prevention control unit 25, the arithmetic pipeline 22
-1, 22-2, ..., 22-n, 22A, 22B are executing the sequence of the convergence process, and while the convergence period condition is satisfied, the overtaking prevention control signal changing unit 26A causes the overtaking prevention control unit 25. The overtaking prevention control signal is changed, and the overtaking prevention control for the operation pipeline 22 during the convergence process is prohibited. In the convergence period,
It is possible to avoid the overhead of the overtaking control by the link and improve the performance.

[0110]

As described above in detail, according to the vector processing device of the present invention (claims 1 and 2), a memory access pipeline using only one bank slot is used as an arithmetic pipeline having a low throughput. By sharing with (Store Pipeline) and executing the operation pipelines in an overlapping manner, there is an effect that a significant improvement in the operation throughput can be realized.

Further, according to the vector processing device of the present invention (claims 3 to 5), when the overtaking prevention control signal is output from the overtaking prevention control unit 25, the arithmetic pipeline is executing the sequence of the convergence processing. Therefore, while the convergence period condition is satisfied, the change unit overtaking prevention control signal is changed and the overtaking prevention control for the operation pipeline during the convergence process is prohibited, so that a significant improvement in processing speed can be realized. There is.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention.

FIG. 2 is a principle block diagram of a second invention.

FIG. 3 is a block diagram showing a vector processing device as a first embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a block diagram showing a configuration example of a bank management unit of the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the first embodiment.

FIG. 7 is a timing chart for explaining the operation of the first embodiment.

FIG. 8 is a block diagram showing a vector processing device as a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of an overtaking prevention control signal changing unit in the second embodiment.

FIG. 10 is a diagram for explaining the operation of the second embodiment.

FIG. 11 is a diagram for explaining the operation of the second embodiment.

FIG. 12 is a block diagram showing a configuration example of an arithmetic pipeline of the second embodiment.

FIG. 13 is a block diagram showing a configuration example of an adder of a second embodiment.

FIG. 14 is a timing chart for explaining an operation example of the arithmetic pipeline according to the second embodiment.

FIG. 15 is a diagram for explaining the operation of the second embodiment.

FIG. 16 is a diagram for explaining the operation of the second embodiment.

FIG. 17 is a block diagram showing a configuration example of an arithmetic pipeline with an additional arithmetic unit according to the second embodiment.

FIG. 18 is a timing chart for explaining an operation example of the arithmetic pipeline with additional arithmetic unit according to the second embodiment.

FIG. 19 is a timing chart showing an example of general bank slot timing setting.

[Explanation of symbols]

1-0, 1-1, ..., 1-n Vector register 2 Memory access pipeline 2A Load pipeline 2B Store pipeline 3A, 3B-0, 3B-1, ..., 3B-m Write Registers 4A, 4B-0, 4C-0, 4B-1, 4C-1, ...,
4B-m, 4C-m read register 5-0, 5-1, ..., 5-m operation pipeline 6 instruction control unit 7 bank management unit 7a bank slot counter 11-1, 11-2, 11-3 management Register 12 Bank slot allocation circuit 13 Notification register 14 Activation signal control unit 15 Division pipeline 15a to 15f Divider 20 Main storage unit 21 Vector register 22, 22-1, 22-2, ..., 22-n Operation pipe Lines 22A and 22B Summation operation pipelines 22a to 22d Adders 23-1, 23-2, ..., 23-m Memory access pipeline 23, 23A Load pipeline 23B Store pipeline 24 Main memory 25 Overtaking Prevention control unit 26 Change unit 26A Overtaking prevention control signal change unit 26B Convergence period notification unit 26a OR gate 26b AND gate 26c Flip-flop 26d AND gate 26e, 26f Inverter (NOT gate) 27 Command issuing / management unit 28a First stage register 28b Second stage register 28c Third stage register 28d Fourth stage register 28e Transfer Relay register 29 Selector 30 Exponent difference calculation means 31 Digit matching means 32 Addition / subtraction means 33 Normalization means 34 Basic operation unit 34a to 34d Basic operation unit 35 Additional operation unit 35a to 35d Additional operation device 36a to 36d Complex operation device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuhiko Konno 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Hiroaki Atsumi 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture Fujitsu Limited

Claims (5)

[Claims] 1. A vector register (1-0, ..., 1-n) for storing a plurality of element data in units of a plurality of interleaved banks, and the vector register (1-0, ..., 1-). n) a plurality of operation pipelines (5-0, ..., 5-m) for accessing each element data and one or more memory access pipelines (2), and the operation pipeline (5 -0, ..., 5-m) and a memory access pipeline (2), and a bank management unit (7) that manages a bank slot indicating a timing at which each bank unit can be accessed. (5-0, ..., 5-m) and the memory access pipeline (2)
In the vector processing device for sequentially accessing each bank unit of the registers (1-0, ..., 1-n) to process each element data, the plurality of operation pipelines (5-0, ..., 5-m) Has at least one operation pipeline (15) having a lower operation throughput than other operation pipelines, and the bank management unit (7) allows the operation pipelines (5-0, ..., 5-m) and the memory access pipeline (2) are connected to the vector registers (1-0, ...,
1-n), the plurality of arithmetic pipelines (5-
Of the 0, ..., 5-m), the operation pipeline (15) having a low operation throughput is the vector register (1-
0, ..., 1-n) is accessed by using the timing assigned as the memory access pipeline (2). 2. The plurality of arithmetic pipelines (5-0,
, 5-m), the operation pipeline (15) with a low operation throughput is the vector register (1-0,
, 1-n) is accessed by the store pipeline (2B) of the memory access pipeline (2) at the vector register (1-0,
, 1-n) is assigned to a bank slot at a read timing for performing a store operation from the main storage unit (20). 3. A vector register (21) for storing a plurality of element data in a plurality of interleaved banks, and data on the vector register (21) as an input operand, or an operation result. One or more operation pipelines (22) for writing data to the vector register (21) and one or more load pipes for transferring data from the main memory (24) to the vector register (21) A line (23), the load pipeline (23) is configured to transfer the data from the load pipeline (23) to the vector register (21) during execution of an instruction. Execution order of instructions when the operation pipeline (22) executes the subsequent operation instruction whose input operand is the data written in 21) In order to guarantee the order, the execution of the load pipeline (23) is executed by the subsequent operation pipeline (2
In the vector processing device having the overtaking prevention control unit (25) for temporarily suspending the execution of all the operation pipelines (22) when the condition of the process of 2) overtaking is detected, the vector register (21) For a vector instruction that requires a read processing period for receiving the data supply and a convergence period for collecting the results after the read processing period, overtaking prevention control for the operation pipeline (22) that is executing the convergence processing of the vector instruction is performed. A vector processing device comprising a changing unit (26) for changing an overtaking prevention control signal output from the overtaking prevention control unit (25) so as not to perform. 4. The vector processing apparatus according to claim 3, wherein the changing unit (26) is provided in the arithmetic pipeline (25). 5. An arithmetic pipeline (22) executing a convergence process of a corresponding vector instruction has a basic arithmetic unit and an additional arithmetic unit for processing convergence, and the convergence process is performed by the additional arithmetic unit. If the basic operation unit can execute another subsequent operation instruction during the convergence process, the changing unit (26) prevents overtaking only for the additional operation unit during the convergence process. 4. The overtaking prevention control signal is changed so as not to perform control.
Alternatively, the vector processing device according to item 4.