JPH0715301A - Delay circuit - Google Patents

Abstract

PURPOSE:To delay a rectangular wave whose pulse width is accurately equal to that of a received rectangular wave with a long delay time by using a capacitor whose capacitance is small and to provide an output of the delayed rectangular wave. CONSTITUTION:An output switching element Q5 of a comparator 1 and a constant current source 3 are connected in series in an integrated circuit or the like, a capacitor C1 is rapidly charged via a diode D1 and a discharge current flows trough a base of a transistor (TR) Q6 and then a long delay time TF1 is obtained thereby. The TRQ6 and a constant current source 4 are connected and a capacitor C2 is rapidly charged via a diode D2, the discharge current of the capacitor C2 is discharged via a base of a TRQ7 and a long delay time TR1 is obtained thereby. NPN TRs are employed for the TRs Q6, Q7, the current amplification factor of them is selected equal to each other, the capacitance of the capacitor C1, C2 is selected equal to make currents 11, 12 equal to each other and the time of the delay times TF1, TR1 is made equal to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying a rectangular wave.

[0002]

2. Description of the Related Art A typical prior art is shown in FIG. Transistor Q called differential pair in integrated circuit
A constant current source 11 is connected to the circuit composed of 11 to Q14, and the rectangular wave signal shown in FIG. The discrimination level V is applied to the transistor Q12.
A voltage is set which sets TH. This transistor Q
A capacitor C is connected in association with 12, and a rectangular wave shown in FIG. 5B is derived from the output terminal 13 via the transistors Q15 and Q16. When the capacitor C is formed in the integrated circuit, it is at most about 10 pF, and therefore the rise time TR and the fall time TF shown in FIG. 5 are about 1 μsec, which is a very short time.

[0003]

In the prior art shown in FIGS. 4 and 5, the input terminal 12 is provided with the configuration shown in FIG.
In addition to the rectangular wave 15 shown in (1), high frequency noise 16
When is mixed, the time TR and TF are short,
The waveform 1 corresponding to the rectangular wave 15 is output from the output terminal 13.
7, there is a problem that the waveform 18 corresponding to the noise 16 is derived. It is necessary to prevent the waveform 18 from being output.

Further, in the above-mentioned prior art, the capacitor C is charged from the constant current source 11 by the relatively large current I passing through the transistor Q12, and is discharged through the transistor Q14, whereby each time TR, Since TF is defined, the time TR and TF cannot be lengthened as described above in the configuration using the capacitor C having an extremely small capacity in the integrated circuit.

Furthermore, in this prior art, a charging current flows through the transistor Q12 for charging the capacitor C corresponding to the rising time TR, and a transistor Q14 for discharging the capacitor C corresponding to the falling time TF.
Transistor Q12 is of PNP conductivity type, and transistor Q14 is of NPN conductivity type.
Therefore, the times TR and TF are different depending on the characteristics of the transistors Q12 and Q14. Therefore, it becomes difficult to derive a signal having the same pulse width as that of the input signal VIN from the output terminal 13, and therefore, the circuit shown in FIG. 4 cannot be used in the circuit for calculating the pulse width.

An object of the present invention is to provide a delay circuit capable of accurately achieving a long delay time, for example, 1 msec even with a small capacity capacitor.

[0007]

According to the present invention, a constant current source 3 is connected in series to an output switching element Q5, and the output switching element Q5 is turned on or off when the level of an input signal VIN is less than a predetermined discrimination level VTH. A connection point between the output switching element Q5 and the constant current source 3, and a comparator 1 in which one of the switching states is set and the level of the input signal VIN is equal to or higher than the discrimination level VTH, and the output switching element Q5 is turned on or off. A diode D1 having an anode connected to the capacitor, a capacitor C1 connected to the cathode of the diode D1 and rapidly charged by a current from the constant current source 3 through the diode D1, and a base to which the capacitor C1 is connected, And a discharging transistor Q6 for slowly discharging the capacitor C1. A delay circuit, wherein the door.

The present invention also provides the discharging transistor Q.
6 is connected to another constant current source 4 in series, a discharging transistor Q6, and another diode D2 whose anode is connected to the connection point of the other constant current source 4.
And another capacitor C2 connected to the cathode of the other diode D2 and rapidly charged by the current through the other diode D2 from the other constant current source 4, and the other capacitor C2. Another discharge transistor Q7 having a base to which the capacitor C2 is connected and slowly discharging the other capacitor C2 is characterized.

[0009]

According to the present invention, the level of the input signal VIN is
When the discrimination level becomes less than VTH, the constant current source 3
The output switching element Q5, which is connected in series with, shuts off, so that the capacitor C1 is charged rapidly by the current I from the constant current source 3 through the diode D1 and thus in a very short time.

After that, when the level of the input signal VIN exceeds the discrimination level VTH, the output switching element Q
5 conducts, so that the charge on capacitor C1 is slowly discharged through the base of transistor Q6. At this time, the discharge current Ib1 discharged from the capacitor C1 is
The current flowing between the collector and emitter of the transistor Q6 is I1, and the current amplification factor of the transistor Q6 is β6.
Is I1 / β6, which is a small value. In this way, a long delay time TF1 can be obtained even if the capacitor C1 has a small capacity.

In addition to the transistor Q6,
By providing one more constant current source 4, one diode D2 and one capacitor C2, the input signal VI
When the level of N becomes less than the predetermined discrimination level VTH, the output switching element Q5 is cut off, and the transistor Q6
By conducting the other capacitor C
The charge of 2 is slowly discharged through the base of the other transistor Q7, which causes the capacitor C2
Even if is small, a long delay time TR1 can be obtained.

The transistor Q6 and the other transistor Q7 have the same conductivity type, for example, NPN.
It may be of a conductive type, whereby the characteristics of these transistors Q6 and Q7 are made the same, the capacitances of the capacitors C1 and C2 are made the same, and the currents at the time of discharge are made the same, thus making two delay times TR1. , TF1
Can be made equal, and a delayed rectangular wave having the same pulse width as the input rectangular wave can be accurately derived.

[0013]

FIG. 1 is an electric circuit diagram of an embodiment of the present invention. The electric circuit shown in FIG. 1 is realized by an integrated circuit, and in the comparator 1, a differential pair is constituted by the transistors Q1 to Q4, and the constant current source 2 is connected to this differential pair. The base of the transistor Q1 is connected to the input terminal 6, and the base of the transistor Q2 is supplied with a voltage having a predetermined discrimination level VTH from the reference voltage source 7. The connection point 8 of the transistors Q2 and Q4 is connected to the base of the transistor Q5. The transistor Q5 is an output switching element, and the constant current source 3 is connected in series to the transistor Q5 to supply the current I. The anode of the diode D1 is connected to the connection point 9 between the collector of the transistor Q5 and the constant current source 3. The cathode of the diode D1 is a capacitor C
1 and is further connected to the base of the transistor Q6.

Another constant current source 4 is connected in series to the transistor Q6. Transistor Q6 and constant current source 4
The anode of the diode D2 is connected to the connection point 10 with. The cathode of the diode D2 is connected to the capacitor C2 and the base of the transistor Q7. The transistor Q7 is further connected to the constant current source 5, and their connection point 21 is connected to the base of the transistor Q8. The collector of the transistor Q8 is connected in series to the voltage source via the resistor R1, and the collector serves as the output terminal 22. Transistors Q1 and Q2 are P
NP conductivity type, and the remaining transistors Q3 to Q8 are NPN conductivity type. The capacitors C1 and C2 have a small capacity, for example, about 10 pF, and are formed in the integrated circuit.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. FIG. 2A shows the input terminal 6
It is a wave form diagram of the input signal VIN input from. Time t
1, the input signal VIN of the input terminal 6 changes from the high level to the low level and becomes less than the discrimination level VTH,
Transistor Q1 conducts as shown in FIG. 2 (2), which causes transistor Q5 to shut off as shown in FIG. 2 (3). The transistor Q6 is shown in FIG.
As shown in (4), the transistor Q7 conducts at time t1 and the collector-emitter impedance of the transistor Q7 is as shown in FIG.
As shown in (5), the transistor Q8 operates as shown in FIG. 2 (6). Before time t1, the transistor Q7 is conducting, and after time t1, the charge of the capacitor C2 flows through the base of the transistor Q7, and its discharge current Ib2 is constant current Ib of the constant current source 5.
Corresponds to 2. When the transistor Q7 cuts off at time t2, the transistor Q8 rises and becomes conductive as shown in FIG. 2 (6). When the current amplification factor of the transistor Q7 is β7, the discharge current Ib2 is I2 / β7.
Is a small value.

After that, at time t3, the input signal VIN
Rises above the discrimination level VTH, the transistor Q1 cuts off as shown in FIG. 2 (2), and in response thereto, the transistor Q5 conducts as shown in FIG. 2 (3). This causes the base of transistor Q6 to
The discharge current Ib1 from the capacitor C1 flows. When the constant current of the constant current source 4 is I1 and the current amplification factor of the transistor Q6 is β6, the discharge current Ib1 is I1 / β6, which is a small value. As a result of the discharging of the capacitor C1, when the transistor Q6 is cut off at time t4, the capacitor C2 is rapidly charged by the current I1 from the constant current source 4 through the diode D2.

At time t1 described above, the capacitor C1 causes the current I1 of the constant current source 3 to flow due to the interruption of the transistor Q5.
Flows through the diode D1 and is rapidly charged.

The delay time TF1 between times t3 and t4 is thus achieved by discharging the capacitor C1. The diodes D1 and D2 prevent the discharge currents of the capacitors C1 and C2 from flowing, and the discharge currents Ib1 and Ib2 can flow only through the bases of the transistors Q6 and Q7. In this way, a long delay time TF1 can be obtained.

The capacitors C1 and C2 have the same capacitance,
The currents I1 and I2 of the constant current sources 4 and 5 are made equal, and the characteristics of the transistors Q6 and Q7, particularly the current amplification factors β6 and β
By setting 7 equally, the delay times TR1, T
F1 can be equalized, and a signal having a pulse width exactly equal to the pulse width of the signal from the input terminal 6 thus input can be derived from the output terminal 22. Therefore, the duty ratios of the input and output signals are equalized. can do.

Further, according to the present invention, when the high frequency noise 24 is mixed and input from the input terminal 6 in addition to the rectangular wave pulse 23 shown in FIG.
From FIG. 3, the delayed rectangular wave pulse 2 shown in FIG.
5 is derived, and the waveform corresponding to the noise 24 at this time is
It is not derived from the output terminal 22. Noise 2
By setting a delay time that is longer than the time that 4 is maintained, it is possible to prevent the undesired pulse corresponding to the high frequency noise from being derived.

[0021]

As described above, according to the present invention, a long delay time can be obtained even if the capacitors C1 and C2 have small capacitances.

Further, since such a long delay time can be obtained, it is possible to prevent undesired rectangular wave pulses from being derived from being adversely affected by the input high frequency noise and being mixed with the noise.

Also preferably, the conductivity type of the transistor Q6 and the other transistor Q7 are the same,
Further, it is possible to derive the rectangular wave having the same pulse width as the pulse width of the rectangular wave input by making the capacitors C1 and C2 have the same capacitance. Therefore, the delay circuit of the present invention can be used to generate a pulse wave. The present invention can be implemented in connection with a processing circuit that calculates the width.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a waveform diagram for explaining another operation of the embodiment shown in FIG.

FIG. 4 is a prior art electrical circuit diagram.

5 is a waveform diagram for explaining the operation of the prior art shown in FIG.

FIG. 6 is a waveform diagram for explaining another operation of the prior art shown in FIG.

[Explanation of symbols]

 1 Comparator 2, 3, 4, 5 Constant current source 6 Input terminal 7 Reference voltage source 8, 9, 10, 21 Connection point 22 Output terminal Q5 Output switching transistor Q6, Q7 Discharge transistor C1, C2 Capacitor D1, D2 Diode

Claims (2)

[Claims] 1. A constant current source 3 is connected in series to an output switching element Q5, and when the level of an input signal VIN is less than a predetermined discrimination level VTH, the output switching element Q5 is switched to one of an on state and an off state, and an input signal Comparator 1 for switching the output switching element Q5 to the other switching state of ON or OFF when the level of VIN is equal to or higher than the discrimination level VTH, and the diode D1 whose anode is connected to the connection point between the output switching element Q5 and the constant current source 3. A capacitor C1 that is connected to the cathode of the diode D1 and that is rapidly charged by the current from the constant current source 3 through the diode D1; and a base that the capacitor C1 is connected to for discharging the capacitor C1 slowly A delay circuit including a transistor Q6 . 2. Another constant current source 4 connected in series to the discharging transistor Q6, a discharging transistor Q6, and the other constant current source 4
Another diode D2 whose anode is connected to a connection point with, and which is connected to the cathode of the other diode D2,
Another that is rapidly charged by the current from the other constant current source 4 through the other diode D2
The capacitor according to claim 1, further comprising one capacitor C2 and another discharging transistor Q7 having a base to which the other capacitor C2 is connected and slowly discharging the other capacitor C2. Delay circuit.