JPH0697973A - Radio receiver - Google Patents

Abstract

PURPOSE:To provide excellent transmission characteristics and to reduce power consumption even when the delay distribution of a propagation path is small and fluctuation is large by selectively using an equalizer for signal discrimination and a delay detection circuit corresponding to propagation conditions when propagation environment fluctuates. CONSTITUTION:The reception signals of an intermediate frequency band from an input terminal 1 are amplified by an AGC amplifier 2 and quasi-synchronous detected by a quasi-synchronous detection circuit 3 and common-mode components and orthogonal components are outputted. A/D converters 4 and 5 sample the output signals and convert them into digital signals and sample values are inputted to the equalizer 6, the delay detection circuit 7 and a control circuit 8. The signal discrimination is respectively performed at the equalizer 6 by equalization and at the circuit 7 by delay detection and the circuit 8 selects the circuit for which the sum of squares of a signal discrimination error in a training section is small to be operated. Thus, even when the delay distribution of the propagation path is small and the fluctuation is large, the excellent transmission characteristics can be obtained and the power consumption is reduced by the operation stoppage of the equalizer 6.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used in digitally modulated wireless communications. In particular, it relates to a technique for suppressing deterioration of transmission characteristics due to intersymbol interference. The present invention is suitable for use as a receiver for mobile radio communication.

[0002]

2. Description of the Related Art In digital communication, it is known to use an equalizer as a technique for suppressing deterioration of transmission characteristics due to intersymbol interference, and one of effective equalizers is maximum likelihood sequence estimation (Maximum Likelihood Sequence). Estimatio
n: MLSE) is known. In this maximum likelihood sequence estimation, the likelihood corresponding to a possible signal sequence is calculated, and in the signal determination, the signal sequence having the largest value is selected. Therefore, in order to reduce the number of sequences and suppress the amount of calculation, a Viterbi equalizer that performs state estimation using a Viterbi algorithm is known.

An example of the configuration of a conventional receiver using an equalizer is shown in FIG. 3, and the format of the received signal is shown in FIG.

A received signal in the intermediate frequency band is input to the input terminal 1. This received signal is the automatic gain control amplifier 2
Is amplified to a level suitable for detection and input to the quasi-synchronous detection circuit 3. The quasi-synchronous detection circuit 3 performs quadrature synchronous detection with a local oscillation frequency that matches the carrier frequency of the input signal, and outputs the in-phase component and the quadrature component of the baseband signal. The in-phase component and the quadrature component are A / D
It is sampled by the converters 4 and 5 and converted into a digital signal. This digital signal, that is, the quasi-synchronized detection signal sample value includes a modulation wave having a symbol period T, and the sampling period is T. The equalizer 6 receives this quasi-synchronized detection signal sample value as an input, performs signal determination by equalization, and outputs a determination signal to the output terminals 10 and 11.

This receiver receives a signal having a burst structure. Each burst is provided with a known signal called the training signal, followed by the data signal. The equalizer 6 performs initialization using this training signal,
The signal determination is performed by equalizing the quasi-synchronized detection signal sample value in the data signal section.

[0006]

However, when the delay dispersion of the propagation path is smaller than the symbol period T of the modulated wave and the fluctuation of the propagation path is severe, the equalization characteristic of the equalizer is greatly deteriorated.

An object of the present invention is to solve the above problems and to provide a radio receiver capable of obtaining excellent reception characteristics even when the delay dispersion of the propagation path is small and the fluctuation is large.

[0008]

The radio receiver of the present invention comprises:
In a radio receiver provided with a detection means for detecting a signal modulated by a digital signal and outputting a sample value thereof, and an equalizer for equalizing the waveform distortion included in the output of the detection means to make a signal determination. , A differential detection circuit that performs signal determination on the output of the detection means by differential detection, and a signal determination error of the equalizer and the signal determination error of the differential detection circuit for a predetermined signal section are compared and one of the outputs is output. And a selecting unit for selecting.

It is desirable to include means for stopping the operation of the unselected one of the equalizer and the differential detection circuit after the lapse of a predetermined signal section.

When the received signal is a burst signal, the training signal is used as the predetermined signal section.

When the transmitting side is performing quasi-synchronous transmission in which a plurality of radio waves modulated with the same information are transmitted while maintaining the carrier frequency difference, the receiving means modulated by the digital signal is sent to the detecting means. It is preferable to include a quasi-coherent detection circuit that performs coherent detection at a frequency matched with the carrier frequency of.

The selecting means may be configured to compare the sum of squares of signal determination errors and select either the equalizer or the differential detection circuit.

[0013]

As described above, when the delay dispersion of the propagation path is smaller than the symbol period T of the modulated wave and the fluctuation of the propagation path is large, the equalizer deteriorates the transmission characteristics as compared with the differential detection circuit. In addition, the circuit scale becomes larger than that of the differential detection circuit, and power consumption increases. On the other hand, in the delay detection circuit, the transmission characteristics deteriorate significantly when the delay dispersion increases. Therefore, both an equalizer and a differential detection circuit are provided, and a circuit with a small signal judgment error is selected and controlled to operate.

[0014]

1 is a block diagram showing a radio receiver according to an embodiment of the present invention.

In this embodiment, a quasi-synchronous detection circuit 3 is used as detection means for detecting a signal modulated by a digital signal input via an input terminal 1 and an automatic gain control amplifier 2 and outputting a sample value thereof. The A / D converters 4 and 5 are provided, and the equalizer 6 that equalizes the waveform distortion included in the outputs of the A / D converters 4 and 5 and makes a signal determination is provided.

The characteristic feature of this embodiment is that A
A delay detection circuit 7 which performs signal detection on the outputs of the D / D converters 4 and 5 by delay detection, a signal determination error of the equalizer 6 with respect to a predetermined signal section, and the delay detection circuit 7.
This is because the control circuit 8 and the selection circuit 9 are provided as selection means for comparing the signal determination error of No. 1 and the output of one of the two.

A received signal in the intermediate frequency band is input to the input terminal 1. The automatic gain control amplifier 2 amplifies the received signal to a level suitable for detection. The quasi-coherent detection circuit 3 quasi-coherently detects the received signal that has passed through the automatic gain control amplifier 2 and outputs its in-phase component and quadrature component. The A / D converters 4 and 5 sample the quasi-coherent detection signal,
Convert to digital signal. The quasi-synchronous detection signal sample value is input to the equalizer 6, the differential detection circuit 7 and the control circuit 8. The equalizer 6 performs signal determination by equalization,
The first determination signal is output. In addition, the differential detection circuit 7
The signal determination is performed by the differential detection, and the second determination signal is output. The control circuit 8 selects and operates one of the equalizer 6 and the delay detection circuit 7, whichever has better transmission characteristics. The selection circuit 9 selects the first or second determination signal, and outputs it to the output terminal 1
Output from 0 and 11.

This radio receiver receives a burst-structured signal as in the conventional example. The training signal of the burst signal initializes the equalizer 6 and selects one of the equalizer 6 and the differential detection circuit 7. In the data signal section following the training signal, only one of the equalizer 6 and the differential detection circuit 7 is operated.

Here, the operation of the control circuit 8 will be described by taking as an example the case where a Viterbi equalizer is used as the equalizer 6.

The control circuit 8 has a BER (bit error ratio)
Based on the determination formula obtained from the theoretical formula of, the one having the better BER characteristic is selected from the equalizer 6 and the differential detection circuit 7. This determination formula is D = γ in the case of differential encoding QPSK modulation.
_E −2.0 γ _D , and when D is negative, differential detection circuit 7
Is selected, and the equalizer 6 is selected when the value is non-negative. Here, γ _E and γ _D are equalizer 6 and differential detection circuit 7, respectively.
_Eb / N ₀ of [1], that is, [signal energy per bit] / [noise power per 1 Hz], and is obtained by considering a tracking error for inter-symbol interference and channel fluctuation that cannot be eliminated as a noise component.

Here, a method of approximating γ _E and γ _D in the training signal section of the signal length N _T symbols will be described. Assuming that the power of the noise component is very small,
The judgment formula D can be replaced with the following judgment formula D ′.

[0022]

[Equation 1] Here, the sampling period is the symbol period T of the modulated wave. e _E (k) is a signal determination error of the equalizer 6 and is a difference between the quasi-synchronized detection signal sample value and its estimated value. e
_D (k) is a signal determination error of the differential detection circuit 7, which is an error signal when the signal determination is performed with reference to the carrier phase shift of the 1T past quasi-synchronous detection signal sample value. In this case, the intersymbol interference, the tracking error with respect to the channel fluctuation, and the noise are doubly estimated, and the power is twice the value to be obtained.

In summary, the control circuit 8 makes a selection based on the judgment formula D '. That is, the control circuit 8
The sum of squares of the signal judgment error in the training signal section is obtained for both the equalizer 6 and the delay detection circuit 7, and the circuit having the smaller sum of the squares of the signal judgment errors is selected and operated.
Although the sum of squares of the signal determination error in the training signal section is obtained here, the same can be done in the data signal section.

FIG. 2 shows the result of computer simulation of the average error rate with respect to the delay time.

In this simulation, the transmission rate was set to 4
0 kb / s, and the modulation method was differentially encoded QPSK with roll-off of 0.5. The transmission line was a two-wave Rayleigh model with a delay time τ, E _b / N ₀ = 30 dB, and the maximum Doppler frequency f _D was 80 Hz. The structure of the burst signal was such that a training signal of 10 symbols was followed by a data signal of 64 symbols. The equalizer is a Viterbi equalizer and uses the RLS algorithm for channel estimation. In addition, RLS
The forgetting factor of the algorithm was 0.8, and the number of states of the Viterbi algorithm was 4.

As shown in FIG. 2, the delay time is 0.2T.
In the following, the differential detection has a better error rate characteristic than the equalizer, and the error rate characteristic is improved by selecting and using the differential detection circuit and the equalizer. Moreover, power consumption can be reduced by appropriately selecting the delay detection circuit and stopping the operation of the equalizer.

[0027]

As described above, the radio receiver of the present invention selects and uses the equalizer for signal judgment and the differential detection circuit depending on the propagation condition when the propagation environment changes. To do. As a result, excellent transmission characteristics can be obtained even when the delay dispersion of the propagation path is small and the fluctuation is severe. Furthermore, in that case, by stopping the operation of the equalizer,
Power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a wireless reception device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a computer simulation result of an average error rate with respect to a delay time.

FIG. 3 is a block configuration diagram showing a conventional wireless receiving device.

FIG. 4 is a diagram showing a format of a received signal.

[Explanation of symbols]

 1 Input Terminal 2 Automatic Gain Control Amplifier 3 Quasi-Synchronous Detection Circuit 4, 5 A / D Converter 6 Equalizer 7 Delay Detection Circuit 8 Control Circuit 9 Selection Circuit 10, 11 Output Terminal

Claims (3)

[Claims] 1. A detection means for detecting a signal modulated by a digital signal and outputting a sample value thereof, and an equalizer for equalizing the waveform distortion included in the output of the detection means to make a signal determination. In the radio receiver, a delay detection circuit for performing signal detection by delay detection on the output of the detection means, a signal determination error of the equalizer and a signal determination error of the delay detection circuit for a predetermined signal section are provided. A radio receiver, comprising: a selection means for comparing and selecting one of the outputs. 2. The selecting means includes means for stopping the operation of the non-selected one of the equalizer and the differential detection circuit after the lapse of the predetermined signal section. Wireless receiver. 3. The radio receiver according to claim 1, wherein the predetermined signal section is a section of a training signal transmitted from the transmission side.