JPH0658963A - Method and apparatus for measuring frequency - Google Patents

Method and apparatus for measuring frequency

Info

Publication number
JPH0658963A
JPH0658963A JP4214336A JP21433692A JPH0658963A JP H0658963 A JPH0658963 A JP H0658963A JP 4214336 A JP4214336 A JP 4214336A JP 21433692 A JP21433692 A JP 21433692A JP H0658963 A JPH0658963 A JP H0658963A
Authority
JP
Japan
Prior art keywords
frequency
oscillator
signal
pll
control data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4214336A
Other languages
Japanese (ja)
Inventor
Takeo Ooishi
丈於 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4214336A priority Critical patent/JPH0658963A/en
Publication of JPH0658963A publication Critical patent/JPH0658963A/en
Pending legal-status Critical Current

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  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a frequency measuring apparatus in which a PLL circuit itself can be taken into advantage by providing means for capturing an oscillator control signal in a PLL circuit, means for measuring the frequency of output signal from PLL based on the control signal, and means for estimating the frequency of input signal. CONSTITUTION:A phase comparator 1 compares the phases of input and output signals and delivers an error signal to a loop filter. The loop filter comprises a multiplier 2 and an integrator 3 and determines data for controlling a numeric control oscillator 4 based on the error signal from the comparator 1. The oscillator 4 can control the oscillation frequency based on the control data. An I/O unit 8 delivers control data from the oscillator 4 to a CPU 7. A ROM 5 stores a program and a RAM is a working memory for the CPU. An output unit 9 displays the results. The oscillator 4 oscillates at a frequency determined for the control data. This constitution determines an oscillation frequency through calculation based on a control data being input to the oscillator 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電気信号の周波数を測
定する装置及びその方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for measuring the frequency of electric signals.

【0002】[0002]

【従来の技術】通常、PLLは入力信号と同周波数、同
位相の信号を発生させることを目的として使用される。
そのため、入力信号、及びPLLの出力信号の周波数を
知るためには、外部に測定回路または測定機器(周波数
カウンターなど)を接続し、測定する必要がある。
2. Description of the Related Art Generally, a PLL is used for the purpose of generating a signal having the same frequency and the same phase as an input signal.
Therefore, in order to know the frequencies of the input signal and the output signal of the PLL, it is necessary to connect a measurement circuit or a measurement device (frequency counter or the like) to the outside and measure.

【0003】[0003]

【発明が解決しようとする課題】ところで、上述した従
来の測定手法においては、以下のような問題点があっ
た。 1.PLL回路とは別に、周波数測定用の回路または装
置を付加する必要があり、装置が複雑になる。 2.入力信号の周波数が高い場合または広い場合は複雑
な測定回路や、測定能力が高くまた測定範囲の広い装置
が必要となる。
However, the above-mentioned conventional measuring method has the following problems. 1. In addition to the PLL circuit, it is necessary to add a circuit or device for frequency measurement, which complicates the device. 2. When the frequency of the input signal is high or wide, a complicated measurement circuit and a device with high measurement capability and a wide measurement range are required.

【0004】本発明の目的は、上記の問題点を解消する
ことができる、PLL回路自体を利用した周波数測定装
置を提供することにある。
An object of the present invention is to provide a frequency measuring device using the PLL circuit itself, which can solve the above problems.

【0005】[0005]

【課題を解決するための手段】本発明は、上述した課題
を解決するために、PLL回路内の発振器の制御信号
(データ)を取得する手段と、制御信号(データ)から
PLLの出力信号の周波数を測定する手段と、その周波
数を基に入力信号の周波数を推定する手段とを設けてい
る。
In order to solve the above-mentioned problems, the present invention provides a means for acquiring a control signal (data) of an oscillator in a PLL circuit and a PLL output signal from the control signal (data). Means for measuring the frequency and means for estimating the frequency of the input signal based on the frequency are provided.

【0006】[0006]

【作用】上記の構成によれば、検出した制御信号と発振
周波数の関係から周波数を決定することができ、また、
PLLの出力信号は入力信号に同期するという性質を利
用して、入力信号の周波数をPLLの出力信号から推定
することが可能となる。
According to the above construction, the frequency can be determined from the relationship between the detected control signal and the oscillation frequency, and
It is possible to estimate the frequency of the input signal from the output signal of the PLL by utilizing the property that the output signal of the PLL is synchronized with the input signal.

【0007】[0007]

【実施例】以下、図面を参照し、本発明の実施例につい
て説明する。図1は本発明の一実施例の構成を示す図で
ある。図1において、1〜4はディジタルPLLの構成
要素で、5〜9はマイクロプロセッサーとその周辺装置
である。 位相比較器1は入力信号と出力信号の位相を
比較し、その結果出力される誤差信号をループフィルタ
ーに送る。該ループフィルタは乗算器2と積分器3で構
成され,位相比較器1からの誤差信号を基に数値制御発
振器4を制御するための制御データを決定する。数値制
御発振器4は該制御データにより、発振する周波数を制
御することができる。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 1 to 4 are components of a digital PLL, and 5 to 9 are a microprocessor and its peripheral devices. The phase comparator 1 compares the phases of the input signal and the output signal and sends the resulting error signal to the loop filter. The loop filter is composed of a multiplier 2 and an integrator 3, and determines control data for controlling the numerically controlled oscillator 4 based on the error signal from the phase comparator 1. The numerically controlled oscillator 4 can control the oscillating frequency according to the control data.

【0008】I/O装置8は数値制御発振器4の制御デ
ータをCPU7に送る。ROM5はプログラムを保持
し、RAM6はCPUの作業用のメモリーである。出力
装置9は結果を表示する。数値制御発振器4は、制御デ
ータに対して一意に定まる周波数で発振する。したがっ
て、数値制御発振器4に入力される制御データから、発
振周波数を計算によって求めることが可能である。本実
施例では、上記制御データの取得と周波数の計算のため
に、I/O装置8とCPU7を用いている。制御データ
は、I/O装置8を通してCPU7に取り込まれ、そこ
で関係式に当てはめて、発振周波数が求められる。制御
データと発振周波数の関係式はあらかじめプログラムに
組み込まれている。
The I / O device 8 sends the control data of the numerically controlled oscillator 4 to the CPU 7. The ROM 5 holds a program, and the RAM 6 is a working memory of the CPU. The output device 9 displays the result. The numerically controlled oscillator 4 oscillates at a frequency that is uniquely determined for the control data. Therefore, the oscillation frequency can be calculated from the control data input to the numerically controlled oscillator 4. In this embodiment, the I / O device 8 and the CPU 7 are used to obtain the control data and calculate the frequency. The control data is taken into the CPU 7 through the I / O device 8 and applied to the relational expression there to obtain the oscillation frequency. The relational expression between control data and oscillation frequency is built in the program in advance.

【0009】以上の手順でPLLの出力信号周波数の瞬
時値は測定可能である。次に、上記構成によるPLLの
入力信号の周波数測定法の動作を述べる。PLLでは、
入力信号と出力信号の位相を比較し、その誤差をループ
フィルターを通して発振器にフィードバックすることに
より、出力信号の周波数、位相を入力信号のそれにそろ
えている。いま、適当な周波数で発振しているPLL回
路に、周波数変動の無視できる入力信号を加えた場合を
考える。入力信号を加えた直後では、位相比較器1から
の誤差信号は大きく、数値制御発振器4の制御データは
フィードバックがかかる度に大きく変動する。しかし、
フィードバックを繰り返すうちに、誤差信号がが小さく
なり、制御データの変動も小さくなっていく。最終的に
は、入出力信号の周波数、位相ともほぼ一致する。この
定常状態に達すると、誤差信号はほぼ0となり、数値制
御発振器4の制御データもほぼ一定値となる。
The instantaneous value of the output signal frequency of the PLL can be measured by the above procedure. Next, the operation of the frequency measuring method for the input signal of the PLL configured as described above will be described. In the PLL,
By comparing the phases of the input signal and the output signal and feeding back the error to the oscillator through a loop filter, the frequency and phase of the output signal are aligned with that of the input signal. Now, consider a case where an input signal whose frequency fluctuation can be ignored is added to a PLL circuit oscillating at an appropriate frequency. Immediately after adding the input signal, the error signal from the phase comparator 1 is large, and the control data of the numerically controlled oscillator 4 greatly fluctuates every time feedback is applied. But,
As the feedback is repeated, the error signal becomes smaller and the fluctuation of the control data also becomes smaller. Finally, the frequencies and phases of the input and output signals are almost the same. When this steady state is reached, the error signal becomes almost 0, and the control data of the numerically controlled oscillator 4 also becomes almost constant.

【0010】したがって、CPU7で適当な時間、数値
制御発振器4の制御データをサンプルし、サンプルの変
動が定常状態に達したときに、入出力信号の周波数が一
致したと推定できる。このときの制御データを前記手順
で周波数に変換したものが、入力の周波数と考えてよ
い。本実施例では、定常状態に達したかどうかの指標と
して、分散を用いた。サンプルの分散がプログラムで定
めた一定値より小さくなったときに、その平均値を変換
した周波数がPLLの入力信号のそれであるとみなして
いる。
Therefore, the CPU 7 samples the control data of the numerically controlled oscillator 4 for an appropriate time, and when the variation of the sample reaches the steady state, it can be estimated that the frequencies of the input and output signals match. The control data at this time converted into the frequency by the above procedure may be considered as the input frequency. In this example, the variance was used as an index of whether or not the steady state was reached. When the variance of the sample becomes smaller than a fixed value defined by the program, the frequency converted from the average value is regarded as that of the input signal of the PLL.

【0011】なお、本発明はこの実施例にのみ限定され
るものではなく、例えば、数値制御発振器4の制御デー
タを周波数に変換する機能を論理回路で実現し、PLL
回路と一体化することも可能である。また,図2に示す
アナログPLLでは、電圧制御発振器12に入力される
制御電圧を 電圧計に加え、目盛に周波数をふれば、簡
易周波数計となる。更にアナログPLLで、CPUを使
うのであれば、制御電圧をA/D変換して、電圧と周波
数の関係式を用いて計算することができる。
The present invention is not limited to this embodiment. For example, a function of converting the control data of the numerically controlled oscillator 4 into a frequency is realized by a logic circuit, and a PLL is used.
It is also possible to integrate it with the circuit. The analog PLL shown in FIG. 2 becomes a simple frequency meter if the control voltage input to the voltage controlled oscillator 12 is added to the voltmeter and the frequency is scaled. Further, if a CPU is used in an analog PLL, the control voltage can be A / D converted and calculated using a relational expression of voltage and frequency.

【0012】[0012]

【発明の効果】以上説明したように、本発明により、以
下のような効果が得られる。 1.PLL回路を使用している装置の場合、簡単に入力
信号の周波数測定ができ、他に周波数測定回路を付加す
る必要がなくなる。特にCPUを搭載している場合は、
非常に簡単に実現できる。これにより、装置の規模、コ
ストとも縮小できる。 2.入力信号の周波数に関係なく、従来より簡単に周波
数の測定が可能となる。 3.周波数測定の機能を付加したPLL−ICを作れ
ば、部品点数を削減できる。
As described above, according to the present invention, the following effects can be obtained. 1. In the case of the device using the PLL circuit, the frequency of the input signal can be easily measured, and it is not necessary to add another frequency measuring circuit. Especially when equipped with a CPU,
Very easy to achieve. As a result, the scale and cost of the device can be reduced. 2. The frequency can be measured more easily than before regardless of the frequency of the input signal. 3. If a PLL-IC with a frequency measurement function is created, the number of parts can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による周波数測定装置の構成
を示すブロック図である。
FIG. 1 is a block diagram showing a configuration of a frequency measuring device according to an embodiment of the present invention.

【図2】本発明の要部の他の実施例での構成を示すブロ
ック図である。
FIG. 2 is a block diagram showing the configuration of another embodiment of the main part of the present invention.

【符号の説明】[Explanation of symbols]

1 位相比較器 2 乗算器 3 積分器 4 数値制御発振器 5 ROM 6 RAM 7 CPU 8 I/O装置 9 表示装置 10 位相比較器 11 ループフィルター 12 電圧制御発振器 1 Phase Comparator 2 Multiplier 3 Integrator 4 Numerically Controlled Oscillator 5 ROM 6 RAM 7 CPU 8 I / O Device 9 Display Device 10 Phase Comparator 11 Loop Filter 12 Voltage Controlled Oscillator

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 PLL回路内の発振器を制御するための
制御信号を取得する手段と,該制御信号から上記PLL
回路の出力信号の周波数を測定する測定手段と,該周波
数に基づいて上記入力信号の周波数を推定する推定手段
とを有することを特徴とする周波数測定装置。
1. A means for acquiring a control signal for controlling an oscillator in a PLL circuit, and the PLL based on the control signal.
A frequency measuring device comprising: a measuring means for measuring the frequency of an output signal of the circuit; and an estimating means for estimating the frequency of the input signal based on the frequency.
【請求項2】 上記PLL回路は上記発振器及び位相比
較器,ループフィルタで構成されることを特徴とする特
許請求の範囲第1項記載の周波数測定装置。
2. The frequency measuring device according to claim 1, wherein the PLL circuit includes the oscillator, a phase comparator, and a loop filter.
【請求項3】 上記ループフィルタは乗算器と積分器で
構成されることを特徴とする特許請求の範囲第2項記載
の周波数測定装置。
3. The frequency measuring device according to claim 2, wherein the loop filter is composed of a multiplier and an integrator.
【請求項4】 上記測定手段と上記推定手段はCPUと
上記PLL回路内の位相比較器を含み,上記制御信号が
上記PLL回路のフィードバック動作により定常状態に
達した際,該制御信号に基づいて上記入力信号の周波数
を推定するようになすことを特徴とする特許請求の範囲
第2項記載の周波数測定装置。
4. The measuring means and the estimating means include a CPU and a phase comparator in the PLL circuit, and based on the control signal when the control signal reaches a steady state by a feedback operation of the PLL circuit. The frequency measuring device according to claim 2, wherein the frequency of the input signal is estimated.
【請求項5】 周波数変動の無視できる入力信号をPL
L回路に入力して上記PLL回路内の発振器を制御する
ための制御信号を生成し,上記PLL回路内のループに
より上記制御信号が略定常状態に達したことを検知した
ら,該制御信号を予め定められた関係に基づいて周波数
に変換して上記入力信号の周波数を推定するようになす
ことを特徴とする周波数測定方法。
5. An input signal whose frequency fluctuation can be ignored is PL
When a control signal for controlling the oscillator in the PLL circuit is input to the L circuit and it is detected that the control signal has reached a substantially steady state by a loop in the PLL circuit, the control signal is set in advance. A frequency measuring method, characterized in that the frequency of the input signal is estimated by converting it into a frequency based on a defined relationship.
JP4214336A 1992-08-11 1992-08-11 Method and apparatus for measuring frequency Pending JPH0658963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4214336A JPH0658963A (en) 1992-08-11 1992-08-11 Method and apparatus for measuring frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4214336A JPH0658963A (en) 1992-08-11 1992-08-11 Method and apparatus for measuring frequency

Publications (1)

Publication Number Publication Date
JPH0658963A true JPH0658963A (en) 1994-03-04

Family

ID=16654078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4214336A Pending JPH0658963A (en) 1992-08-11 1992-08-11 Method and apparatus for measuring frequency

Country Status (1)

Country Link
JP (1) JPH0658963A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480387B1 (en) * 2002-10-09 2005-04-07 엘지산전 주식회사 Measurement of frequency apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480387B1 (en) * 2002-10-09 2005-04-07 엘지산전 주식회사 Measurement of frequency apparatus

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