JPH0628299B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to an improvement of a semiconductor integrated circuit device. Below, Integrated Injection Logic circuit device (hereinafter "II
L ・ IC ”. ) As an example.

FIGS. 1 (a) to 1 (e) are sectional views taken along the line N--N in FIG. 2 which is a plan view showing the states in the main manufacturing steps thereof in order to better understand the structure of the conventional IIL / IC. However, what is shown here is the case of two outputs (fan-out).

That is, this IIL IC is generally a bipolar IC.
The n-type high impurity on the p-type silicon substrate (1)
Concentration (n⁺Form, the following applies to this. ) Embedded layer
After forming (2), n-type low impurity concentration (n⁻Shape and word
Yes, the same applies below. ) Growing the epitaxial layer (3)
Then, the oxide film (101) and the nitride film (2
01) and are sequentially formed and patterned into a predetermined shape.
N as a mask⁻Shape epitaxial layer (3) to a specified depth
After only etching, the ion implantation method
Form a p-type ion implantation layer (5) for the Yanerukat prevention layer,
Separation by selective oxidation using the nitride film (201) as a mask
An oxide film (102) is formed [Fig. 1 (a)]. Next, nitride film
After removing (201) and oxide film (101),
After forming a thin oxide film (103), pass it through
Resist mask (The resist mask at this stage is shown
Without. ) Via implantation of boron ions, n⁻Shape epi
Selective p for taxi layer (3)⁻After forming the shaping layer (6)
Again, a resist mask with the required pattern (301)
To form boron through the oxide film (103).
Implanting ions, n⁻P on the epitaxial layer (3)⁺form
Layers (7), (8) and (9) are formed [Fig. 1 (b)]. Next Regis
After removing the mask (301), the entire top surface is
After growing a glass film (401), this phosphorus glass film
(401), p⁻Shape layer (6) and p⁺Shape layer (7), (8) Annie
Ring simultaneously p⁻Shaped layer (6a) and P⁺Shape layer
(7a) and (8a) are formed [Fig. 1 (c)]. Then p⁻
A phosphorous glass film (401) and an acid are formed on a part of the shaping layer (6a).
A window is opened in the chemical film (103), and n-type impurities are introduced from here.
And by annealing + Form layer (10a)
And p⁻Shape layer (6a) p⁻In the shaping layer (6b), p⁺form
Layers (7a) and (8a) are grown to (7b) and (8b), respectively [First
Figure (d)]. Then p⁺Open a window on the shaping layer (7b)
Note n⁺Each of the metal together with the part of the window above the shaping layer (10a)
Electrode wiring is performed through the silicide layer (501), and pnp
P, which is the emitter of the transistor⁺Inge on the shaping layer (7b)
The collector electrode (11) is the collector of the pnp transistor,
And p which is the base of the reverse operation npn transistor⁻form
P for electrode extraction connected to layer (6b)⁺Impinged on the molding layer (8b)
The reverse electrode npn transistor
The collector of n⁺The patterned electrode (1
3) again⁺Form the output electrode (14) on the shaping layer (11a).
The IIL gate is completed by making connections to each [First
Figure (e)]. Next, FIG. 11 is a sectional view taken along the line MM of FIG.
Indicates.

The basic two-output IIL gate is shown above, and FIG. 2 is a plan view of this conventional three-output IIL gate, in which (13), (14), and (15) are the first, respectively. Collector C ₁ ,
Three output electrodes (21) and (22) connected to the second collector C ₂ and the third collector C ₃ are inter-gate wirings. The three collectors C ₁ , C ₂ and C ₃ are arranged in the order close to the input (base) electrode (12). wiring
The signal input from 12 is input to 8b, is transmitted from this point to the right in the base 6b region of the first transistor, and is input at each collector position of the first transistor. Therefore, the travel distance in the base is between 8b and 10a. , 8b and 11a, and between 8b and 12a, there is a problem that the signal delays occur. Now,
As shown in FIG. 3, the current amplification factor β _u of the reverse operation npn transistor is greatly reduced in the high current region of the collector current Ic as the collector is farther from the base electrode (11). It is considered that this is because the base resistance becomes farther as the collector is farther from the base electrode. Also, the IIL gate propagation delay time t
It is known that there is a power delay characteristic as shown in FIG. 4 between _pd and power consumption P _d . (For example, Semiconductor Transistor Research Group, IEICE Technical Report SSD76-89, p37: High S
peed IIL with Self − Aligned Double Diffusion Inj
ector [S ² L]).

If the same base area and the same pnp transistor characteristic are used, an inverse proportional relationship such as tpd min ∝ βu ^-0.15 is established as shown in FIG. 5, so as shown in FIG. (as the distance D _CB of the collector and base electrodes is large) minimum delay time t _Pdmin increases. Therefore, in this way II
As shown in Table 1 as an example, the performance of the L gate is different in characteristics between the output electrodes, and is limited by the large delay time of the output electrode farthest from the base electrode. Further, even with the same manufacturing method, the current amplification factor β _u is proportional to the ratio S _C / S _B of the collector area S _{c to} the booth area S _B as shown in FIG. In the conventional structure, as shown in FIG. 2, the base region consisting of the p ⁻ region (6b) and the p ⁺ regions (8b) and (9b) connected to it is the inter-gate wiring.
It exists under (21) and (22), and has a large base area S _B as shown in Table 1, and accordingly a collector area S _C.
And the ratio S _C / S _B becomes very small, the current amplification factor β _u becomes small, the minimum delay time t _pdmin becomes large even in the collector C ₁ closest to the base electrode, and the power supply current I _inj
Of about 200 μA / gate, the delay time t _pd also becomes large.

The present invention has been made in view of the above points, and a low-low resistance conductor layer made of polysilicon or metal silicide is provided in the vicinity of a plurality of collector regions at a fixed distance from the regions, and the low-resistance conductor is formed. By connecting each base region corresponding to each collector to the input terminal by a layer, even if there are a plurality of collectors, it is possible to suppress the characteristic variation due to the difference in the distance between each collector region and the input terminal. The purpose is to obtain an integrated circuit device.

8 (a) to 8 (f) are cross-sectional views showing the states in the main steps of the manufacturing process for better understanding of the basic structure of the IIL / IC according to the embodiment of the present invention. In the Y-Y sectional view of the plan view of the device, the same parts as those in FIGS. Also in this embodiment, the processes up to FIGS. 1 (a) and 1 (b) in the conventional example are processed in exactly the same manner. Then, after forming a window in the oxide film (103) on the p ^{+ -type} layer (9) to be the base extraction layer, a polysilicon film (601) is deposited on the entire upper surface and boron ions are implanted. Anneal process. At this time, the p ^{− type} layer (6a) and the p ^{+ type} layer (9a) are formed [FIG. 8 (a)]. Next, the polysilicon film (601) is patterned to leave only a portion extending from above the p ^{+ -type} layer (9a) to above the isolation oxide film (102) adjacent thereto, and the oxide film removed at this time. (103)
Instead of the above, a thin oxide film (105) is formed including on the remaining polysilicon film (601), and a nitride film (202) is further formed on the thin oxide film (105) [eighth Figure
(b)]. After opening a window on the nitride film (202) and the oxide film (105) on the p ^{+ -type} layer (9a) and on the p ⁻ -type layer (6a), a window on the p ⁻ -type layer (6a). The n ^{+ -type} layer (10) to be the collector layer is p-typed by masking it with a resist film (302) so as to cover other window openings while leaving the open areas.
^- formed in a portion of the surface of the form layer (6a) Eighth FIG
(c)]. Next, the resist film (302) is removed and annealing is performed to complete the n ^{+ -type} collector layer (10a) of the npn transistor, and the p ⁻ -type layer (6b) and the p ^{+ -type} layer (9).
Complete a). After that, P _t , P _d , W, M
A silicide forming metal film (500) such as _o is formed and sintering is performed to form a metal silicide film (501) only on the surfaces of silicon and polysilicon [FIG. 8 (d)]. Next, remove only the metal film (500) with aqua regia,
After depositing a passivation film (401) (for example, a phosphorus glass film) thereon, a required resist mask (303) is used to open a window for forming each electrode. At this time, an etching liquid that does not attack the nitride film is used, and a window larger than the contact hole of the nitride film (202) is opened, and the contact hole is made of the nitride film (202) [Fig. 8 (e)]. . And thereafter removing the resist mask (303), Al, and connect wiring Autoputsuto electrode (13) with a low resistance metal such as A _u, this embodiment is completed [FIG. 3 (f)].

FIG. 10 shows a U-U sectional view of the plan view of FIG. 9, and FIG. 12 shows a RR sectional view of FIG.

The signal input is input from wiring 12, which is the two-layer wiring 501/6.
It is transmitted to 01. (Figs. 9 and 10), on the other hand, the injector input is input from the wiring 11 to the emitter 7b of the second transistor and output from the collector 8b, and this output is the two-layer wiring.
501/601 (FIG. 12) inputs to the base layer 6b through the base lead terminals 9b corresponding to the collectors of the first transistor. (Figs. 9 and 8) The outputs of the first transistor are collectors 10a, 11a, 12a.
Are taken to the wiring 13, 14 and 15 from (Figure 9) Now, in this configuration, the distance D _CB from the signal input position of the wiring 12 to the input position 6b corresponding to the collector of the first transistor can be shortened. That is, in FIG. 2 of the plan view of the conventional example, since the signal input is transmitted from 8b under the wiring 12 through the base 6b of the first transistor from right to left, 8b, 10a, and 8b are transmitted.
11a, there was a problem that D _CB would gradually increase according to the distance between them.

On the other hand, in this embodiment, since the signal input position of the wiring 12 and the base extraction layer 9b corresponding to each collector of the first transistor are connected by the two-layer wiring 501/601 of the low resistance conductive layer, This has the remarkable effect that a simultaneous signal can be supplied to the base 6b corresponding to 10a, 11a and 12a.

FIG. 9 is a plan view showing an IIL gate having three outputs and two inter-gate wirings according to an embodiment of the present invention. First
FIG. 10 is a sectional view taken along line XX of FIG. As can be seen from the figure, beside each collector of the first npn transistor, a metal silicide film (5
A low resistance silicon film (601) is provided in (01), and the polysilicon film (601) allows the base regions corresponding to the collectors of the npn transistor and the pnp transistor as a current source. Is connected with the collector.

In the device having such a configuration, the distances between the collectors of the npn transistors and the collectors (input terminals) of the pnp transistors are substantially the same electrically, and the characteristics are the same as shown in Table 2. Further, since the base electrode wiring corresponding to each of the collectors is composed of the polysilicon film (601) on the inactive region and the metal silicide film (501) on the polysilicon film (gate), which is essential in the conventional structure. The base diffusion layers (6b) and (9b) immediately below the inter-wirings (21) and (22) are unnecessary, the base area S _B itself is small, and the ratio S _C / S _B to the collector area S _C is large, Therefore, the current amplification factor β
_u also becomes large.

Although the gate separation method using selective oxidation is described in the above-mentioned embodiments, the present invention can be applied to other general gate separation methods and color separation methods using a high impurity concentration region, and the base layer has a graft structure. Although the case has been described, the present invention can be applied to an embedded base structure.

As described above in detail, according to the present invention, a low resistance conductor layer made of polysilicon or metal silicide is disposed in the vicinity of a plurality of collector regions at a certain distance from the collector region, and the low resistance conductor layers are provided to the collectors. Since the corresponding base regions and the input terminals are connected to each other, even if there is a difference in the distance between the position of each collector of the npn transistor and its base terminal (input terminal), variations in characteristics due to this are suppressed. It is possible to obtain a semiconductor integrated circuit device that can be manufactured.

[Brief description of drawings]

1 (a) to 1 (e) are cross-sectional views showing a state in a main manufacturing process of a conventional IIL-IC, FIG. 2 is a plan view of the conventional IIL-IC, and FIGS. Relationship between collector current Ic and current amplification factor β _u and power consumption Pd and gate propagation delay time t of a conventional IIL gate having _two collectors C ₁ , C ₂ and C _3.
FIG. 5 shows the relationship with _pd, and FIG. 5 shows the current amplification factor β _u.
Shows a minimum delay time relationship between t _Pdmin and, Figure 6 shows the relationship between the distance D _CB and the minimum delay time t _pd of the collector and base electrodes figure 7 Figure collector-base area ratio S _C / S _B
Diagram showing the relationship between the current amplification factor beta _u and, Figure 8 (a) ~ (f) is a sectional view showing a state in main steps of manufacturing an embodiment of the present invention, FIG. 9 is in this embodiment It is a top view. 10th
The figure is a cross-sectional view taken along the line U-U of FIG. Figure 11 shows
FIG. 3 is a sectional view taken along the line MM in FIG. FIG. 12 is a sectional view taken along line RR of FIG. 9 in plan view. In the figure, (6b) is a base layer, (8b) and (9b) are base extraction layers, (10a) is a collector layer, (11) is an injector terminal,
(12) is a base terminal (electrode wiring), (13), (14) and (15) are collector terminals (electrode wiring), (21) and (22) are wirings between logic gate circuit devices, and (501) is The metal silicite film, (601) is a polysilicon film. The same reference numerals in the drawings indicate the same or corresponding parts.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 7514-4M H01L 21/88 Q (56) References JP-A-54-66784 (JP, A) JP-A-53 -146576 (JP, A) JP-A-53-53254 (JP, A) JP-A-53-53271 (JP, A) JP-A-54-155778 (JP, A) JP-A-52-61476 (JP-A) )

Claims (1)

[Claims] 1. A second conductivity type high impurity concentration diffusion layer formed on a first conductivity type semiconductor substrate, and an emitter formed of a second conductivity type low impurity concentration diffusion layer formed on this layer.
A first transistor including a base formed on the emitter and a plurality of collectors formed on the base, and a low impurity concentration diffusion layer of the second conductivity type as a base, on which a first transistor is formed. A second transistor in which an emitter and a collector are formed, the base of the first transistor is an input, the collector of the first transistor is an output, and the collector of the second transistor is the first transistor. A gate circuit connected to the base of a transistor and having an emitter terminal of the emitter of the second transistor, wherein the first circuit is formed at an equal distance from the respective positions of the plurality of collectors of the first transistor. A low resistance conductive layer is formed on the extraction region of the base of the transistor and connected to the collector of the second transistor. Semiconductor integrated circuit device.