JPH06267992A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device free from damages to an epitaxial layer due to ion impact and a semiconductor device of an element structure which is advantageous in integration. CONSTITUTION:An active region 5 and a semiconductor layer 9 for connecting this active region 5 to electrode metals 10, 11 are formed by a semiconductor material selective growing method. In the embodiment of a field-effect transistor, a gate layer 8 is constructed so as to extend onto an insulation film 3 in the gate width direction. In the case of a bipolar transistor, a base layer is constructed so as to extend onto the insulation film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a semiconductor device used for high-speed signal processing in the fields of communication and information processing, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A field effect transistor (FET) using a compound semiconductor GaAs can perform signal processing at a higher speed than a transistor using Si in a frequency band of a microwave region, and has been used so far for satellite broadcasting reception. Is beginning to become popular as a low-noise amplifier device. In the field of optical communication, Ga is used as a direct modulation element for semiconductor lasers.
AsFET is used.

One example of a conventional FET is the Technical Digest International Electron Device Meeting San Francisco, USA, November 11
Sun-14, 1988, p.692 (Technica
l digest international el
electron devices meeting Sa
n Francisco, USA, December
11-14, 1988 p. 692 ") (hereinafter referred to as" first conventional technology "). FIG. 8 shows a manufacturing process drawing based on the element drawing and the explanatory text described therein.

FIG. 8A: Semi-insulating GaAs substrate 100
Undoped GaAs buffer 101, n-type GaAs
The channel 102, non-doped AlGaAs 103, and non-doped GaAs 104 are epitaxially grown in this order by the MBE method. A metal 105 having a high melting point such as tungsten or tungsten silicide is deposited on the non-doped GaAs 104 by using a sputtering method or the like. Further, a photoresist pattern 106 is formed.

FIG. 8B: The above photoresist pattern 1
The metal 105 is processed using 06 as a mask to form the gate electrode 107. Using this gate electrode as a mask, Mg and Si are sequentially implanted by ion implantation to form a p-type conductive layer 108 and an n′-type conductive layer 109.

FIG. 8 (c): A part of the undoped GaAs 104 is formed by a process using a photoresist pattern.
A part of the undoped AlGaAs 103 and a part of the n-type GaAs channel 102 are removed by etching.
The type GaAs selective growth portion 110 is formed by the MOCVD method. Finally, the source electrode 113 and the drain electrode 1
12 is formed on the n-type GaAs selective growth portion 111.

Another example of a conventional FET is the Institute of Physics Conference Series No. 120, Chapter 4, p. -12th, 1991 (Institute of Physics Con
ference series number 12
0: Chapter 4 p. 207; Procee
ings of the Eightenth I
international Symposium on
Gallium Arsenide and Rel
arated Compounds, Seattle, U
SA, 9-12 September 1991 p.
207) (hereinafter referred to as the second related art). FIG. 3 shows a manufacturing process diagram based on the element diagram and the explanatory text described therein.

FIG. 3 (a): InAlAs buffer 22, InGaAs channel 23, InAlAs 24, InGaAs cap 2 on a substrate 21 made of semi-insulating InP.
Each layer of 5 is epitaxially grown by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method. Next, a photoresist pattern 26 is formed.

FIG. 3B: Using the photoresist pattern as a mask, the epitaxial film grown on the substrate is etched to form a mesa etching portion 27.

FIG. 3C: The photoresist pattern 26 is removed, and the source electrode 2 is placed on the InGaAs cap 25.
9 and the drain electrode 28 are produced by combining photolithography and vapor deposition of metal.

FIG. 3D: Finally, the gate electrode 31 is formed by vapor deposition and etching of metal.

A bipolar transistor is used as a compound semiconductor device. An example of a conventional bipolar transistor is No. 419, pages 25 to 30 (July 17, 1987) (hereinafter referred to as the third prior art). This will be described with reference to FIG.

FIG. 7A: n-type GaAs 72, n-type GaAs collector layer 73, p-type GaAs base layer 74, and n-type AlG are formed on the semi-insulating GaAs substrate 71 by the MBE method.
Epitaxial growth of aAs75 and n-type GaAs76 is performed in this order. Next, the insulating film mask 77 is formed on the n-type GaAs 76.

FIG. 7B: The n-type GaAs 76 is etched leaving the lower part of the insulating film mask 77. Next, Mg ions are uniformly ion-implanted on the substrate surface. After the ion implantation, the substrate is annealed at 800 ° C. to activate Mg ions and form the p-type base portion 78.

FIG. 7C: An insulating film mask 81 is attached to the entire surface of the substrate, and B ions are implanted by ion implantation.
Thereby, the high resistance part 80 is formed.

FIG. 7D: A part of the insulating film mask 81 is removed, and an AuZn electrode 82 is formed on the p-type base portion 78.
Use as a base electrode. Further, part of the insulating film mask 81 remains as the insulating film sidewall 83.

FIG. 7 (e): The insulating film mask 77 and the insulating film side wall 83 are removed, then the insulating film mask 85 is formed, and the AuGeNi electrode 84 is formed on the n-type GaAs emitter portion 79 to serve as an emitter electrode. .

FIG. 12 shows a schematic sectional view of the bipolar transistor thus manufactured.

Another example of a conventional bipolar transistor is Applied Physics Letters, Vol. 61 (19).
1992, pp. 592-594 (Applied P)
hysics Letters 61 (1992) p
p592-594) (hereinafter referred to as the fourth prior art).

In this conventional technique, a SiO ₂ pattern is formed on a compound semiconductor InP substrate, InP in an opening of the SiO ₂ pattern is etched, and an active region of a heterojunction bipolar transistor (HBT) is selectively formed therein. The technique for forming the same is described. The active area is the gas source M
By BE, an n-type InP buffer layer, an n-type InGaAs collector layer, and a p-type InG are formed in the SiO ₂ pattern opening.
The aAs base layer, n-type InGaAs, n-type InP, and n-type InGaAs emitter layer are selectively grown in this order. After that, electrodes are formed by a usual method to form an HBT element structure.

[0021]

First prior art FE
At T, in the process of processing the gate electrode metal 105 to form the gate electrode 107, the gate electrode metal 10 is formed.
The epitaxial film under 5 may be damaged. In particular, WSi, which is a heat-resistant gate electrode material
When W or W or a silicide is deposited on the epitaxial film by a sputtering method and the deposited electrode material is processed by dry etching, the degree of damage is large. This damage remains under the gate electrode 107 even after the device is manufactured, and acts to reduce the current driving capability of the device and the mutual conductance indicating good gain. Therefore, desired device characteristics cannot be obtained. As described above, the first prior art FET has a manufacturing method problem that the epitaxial layer is damaged by ion bombardment.

In the second prior art FET, the planar shape of the element is determined by mesa etching (FIG. 3 (e)).
Therefore, the second prior art FET has a structural problem that it is not suitable for high integration. In addition, the gate electrode 31
Is partially adjacent to the InGaAs channel 23 at the mesa portion 27 (FIG. 3E). FIG. 4 shows a sectional view in the gate width direction of FIG. Gate electrode 31 and I
It is close to the nGaAs channel 23 at the reference numeral 32, and when they contact each other, there is a problem that a leak current flows in the contact portion and normal device characteristics cannot be obtained. There is also a problem that the probability of disconnection of the gate electrode 31 itself at the step portion of the slope of the mesa portion is extremely high. Further, since the gate electrode 31 is in contact with the substrate 21, when the integrated circuit is formed by using the FET of the conventional technique, the voltage applied to the gate electrode 31 is also applied to the substrate 21 and other elements are formed. There is a problem of affecting. The problem of high integration and influence on other elements in the above integration is not limited to the first and second prior art heterojunction FETs,
It also exists in FET.

The third prior art bipolar transistor uses an ion implantation method (see FIG. 7).
(B)) Impurity diffusion in the epitaxial film occurs with the annealing treatment after ion implantation. That is, the doping profile of the epitaxial film becomes different from the device design structure, and desired device characteristics cannot be obtained.
As described above, the third prior art FET has a manufacturing method problem that the epitaxial layer is damaged by ion bombardment. Further, between the p-type base portion 78 and the n-type GaAs collector layer 73 immediately below the p-type base portion 78 shown in FIG.
There is a parasitic capacitance due to a depletion layer formed at the n-junction interface, that is, a base-collector parasitic capacitance portion 89. Since the parasitic capacitance of this portion greatly hinders the high frequency characteristics of the device, it is preferable that the area of the interface of the pn junction is small, but it is difficult to further reduce it by the method of the prior art. Therefore, the bipolar transistor of the third prior art has a structural problem that it is unsuitable for high integration, and thus is not suitable for high integration.

The electrode forming method of the fourth prior art bipolar transistor is a usual method. The usual method is n-type InGaAs emitter layer, n-type InP
It is appropriate to consider a method in which the p-type InGaAs base layer is exposed by removing the layer and the n-type InGaAs layer and the base electrode is formed there. Because of this removal step,
The conventional technique of is disadvantageous in terms of miniaturization. Therefore, the fourth conventional bipolar transistor has a structural problem that it is not suitable for high integration.

A first object of the present invention is to provide a method of manufacturing a semiconductor device which does not have a problem in the manufacturing method that an epitaxial layer is damaged by ion bombardment.

A second object is to provide a semiconductor device having an element structure advantageous for high integration.

[0027]

A first object of the present invention is to form an active region by a selective growth method of a semiconductor material using a mask having a pattern of the active region, and a semiconductor for connecting the active region and an electrode metal. This can be achieved by a method for manufacturing a semiconductor device, which has a step of forming a semiconductor layer by a selective growth method of a semiconductor material using a mask having a layer pattern.

A second object is to arrange a first field effect transistor and an insulating film side by side on a high resistance substrate, and extend a gate electrode of the first field effect transistor in the gate width direction onto the insulating film. This can be achieved by the semiconductor device having the above structure.

Further, the second object is to arrange the first bipolar transistor and the insulating film side by side on the high resistance substrate,
This can be achieved by a semiconductor device having a structure in which the base layer of the bipolar transistor is extended to above the insulating film.

Here, the active region refers to a place where the semiconductor element originally operates. The field effect transistor corresponds to the channel portion, and the bipolar transistor corresponds to the emitter, base and collector regions. In addition, the source and drain contact layers and the emitter,
The base and collector extraction layers correspond to the semiconductor layer connecting the active region and the electrode metal.

[0031]

The operation of the present invention will be described with reference to specific examples.

F using selective growth by MOCVD method
The manufacturing process of ET is shown in FIG.

FIG. 2A: Si that is an insulating film on the substrate 1.
O ₂ and SiN are laminated in order, and then the SiO ₂ and SiN are patterned into mask patterns 2 and 3 by photolithography.

FIG. 2B: SiO is formed by MOCVD.
_{2 In} the openings 12 of the mask 2 and the SiN mask 3, a GaAs buffer layer 4, a GaAs channel 5, AlGaAs 6, G
It grows selectively in the order of the aAs cap 7.

FIG. 2C: A metal is deposited on the uppermost portion, and the deposited metal is processed by photolithography and etching to form the gate electrode 8. At this time, the gate electrode 8
Completely covers the selectively grown layers 4, 5, 6, 7 grown by the MOCVD method and also covers the end of the SiN mask 3.

FIG. 2D: Using the gate electrode 8 as a mask, the SiO ₂ mask 2 and the SiN mask 3 are processed.

FIG. 2E: By wet etching,
The SiO ₂ mask 2 remaining under the gate electrode 8 is removed. The SiN mask 3 is left.

FIG. 2 (f): GaAs by MOCVD method
9 is selectively grown to form a drain contact layer and a source contact layer. Next, the drain electrode 10 and the source electrode 11 are formed on these layers, respectively, to complete the desired FET. A perspective view of the FET of this embodiment is shown in FIG.

According to the present invention, the selective growth of the active region and the semiconductor layer connecting the active region and the electrode metal is carried out by using the masks having the respective patterns. Therefore, as is apparent from this embodiment, the gate electrode 8 is formed. When processing metal materials for
The processed portion can be placed on the mask material 3 for selective growth (FIG. 2C), and damage to the epitaxial layer immediately below the gate electrode due to ion bombardment can be prevented.

Further, a perspective view showing the shape of the gate electrode 8 of this embodiment in detail is shown in FIG. 9 (a) in the gate width direction (AB).
FIG. 9B shows a cross-sectional view of the (direction). 9 (a) (b)
As is apparent from the above, the field effect transistor of the present invention has no mesa portion, and the gate electrode 8 is on the insulating film having substantially the same height as the active region in the gate width direction and is planarized. Is advantageous for high integration. When the field effect transistor is entirely surrounded by the insulating film, the insulating film can be used as isolation between FETs in an integrated circuit. Furthermore, as is clear from the sectional view shown in FIG. 9B, the gate electrode 8 and the GaAs
There is no electrical contact with the channel 5. Therefore, no leak current is generated between the gate electrode 8 and the GaAs channel.

Next, FIG. 5 shows a manufacturing process of a bipolar transistor using selective growth by MOCVD.

FIG. 5A: SiN pattern 42 is formed on a semi-insulating GaAs substrate 41, and MOCVD is performed on the pattern opening.
The n-type GaAs collector contact layer 43 is selectively grown by the method. Next, the SiN pattern 44 is formed again, and the n-type GaAs collector layer 45 and the p-type AlGaA are formed in the pattern opening.
The s base layer 46 is selectively grown by MOCVD in this order. The upper half of the p-type AlGaAs base layer 46 is SiN.
Ride on the edge of the pattern 44 to grow laterally.

FIG. 5B: A SiO ₂ pattern 47 is further formed, and the n-type AlGaAs emitter layer 4 is formed in the pattern opening.
8, n-type GaAs layer 49 and n-type InGaAs contact layer 50 are selectively grown by MOCVD. Also in this case, the n-type InGaAs contact layer 50 rides on the edge of the opening of the SiO ₂ pattern 47 and grows laterally.

FIG. 5C: The SiO ₂ pattern 47 is removed by etching, and then the SiN pattern 51 is formed. S
A p-type GaAs base lead-out portion 52 is selectively grown in the opening of the iN pattern 51 by MOCVD. Next, Au /
The base electrode 57 is formed by vacuum-depositing Zn.

FIG. 5D: SiO ₂ pattern 53, SiN
An n-type GaAs collector lead-out portion 54 is selectively grown in the openings of the patterns 51 and 47 by MOCVD.

FIG. 5 (e): SiO ₂ pattern 53, SiN
An opening is formed by a photoresist pattern on the n-type InGaAs contact layer 50 in the pattern 51, and SiO 2 is formed.
₂ pattern 58. Semiconductor part n-type In exposed on the surface
A metal of Au / Ge is vapor-deposited on the GaAs emitter contact layer 50 and the n-type GaAs collector lead portion 54 to form an emitter electrode 55 and a collector electrode 56.

The present invention, as is clear from this embodiment,
An active region and a semiconductor layer connecting the active region and the electrode metal are formed by selective growth. As described above, since the ion implantation method is not used, the annealing process after the ion implantation is unnecessary. Therefore, it is possible to eliminate the impurity diffusion in the epitaxial film due to the annealing treatment, and prevent the epitaxial layer in the active region from being damaged by ion bombardment.

By using the selective growth method,
The area of the base layer 46 can be reduced, which is advantageous for high integration.

Further, since the base layer 46 is extended to above the insulating film 44 and this portion is used as a part of the base extraction layer, the base extraction layer is formed without removing the upper portion of the active region of the base layer. Can be achieved, which is advantageous for high integration. Furthermore, the base layer 46 and the collector contact layer 4
The insulating film 44 exists between the base layer 46 and the collector contact layer 43, and there is no parasitic capacitance due to the depletion layer formed at the interface of the pn junction between the base layer 46 and the collector contact layer 43. Therefore, the base-collector parasitic capacitance portion, which is a problem of the conventional bipolar transistor described in FIG. 12, can be significantly reduced.

[0050]

EXAMPLE The characteristics of selective growth by the MOCVD method which is the basis of the present invention will be described with reference to FIG. Figure 13 shows GaAs /
It is a schematic diagram which looked at the cross-sectional structure near the AlGaAs selective growth part from the direction from which a crystal plane orientation differs. FIG. 13A is a cross-sectional view in which the crystal plane orientation is viewed from the [1,1,0] direction,
FIG. 13B is a cross-sectional view when the crystal plane orientation is viewed from the [1, -1,0] direction. In the figure, 160 is a substrate, for example G
aAs is used. The SiO ₂ pattern 161 is formed on the substrate 160.
After the formation of the
161, GaAs 163, AlGaAs 164, GaA
Crystals grow in the order of s165. When the source gas used in the process of crystal growth is trimethylgallium (TMG), trimethylaluminum (TMA) as the group III source gas, and arsine (AsH ₃ ) as the group V source gas,
When the supply ratio V / III of the group V source gas and the group III source gas is 30 or more and the crystal growth temperature is in the range of 500 ° C. to 700 ° C., as shown in FIGS. 13 (a) and 13 (b). Crystal growth with different cross-sectional shapes can be realized.

The present invention will be described in detail below with reference to examples.

Example 1 A GaAs / AlGaAs heterojunction FET of Example 1 of the present invention will be described with reference to FIG.

FIG. 2A: A SiO ₂ film and a SiN film are sequentially deposited on the semi-insulating GaAs substrate 1 by the CVD method at 200 nm and 100 nm, respectively. Next, by photolithography and etching, SiO ₂ , SiN
Forming a pattern on the film.

FIG. 2B: SiO ₂ and SiN patterns 2 and 3 have openings (width 300 nm, length 10 μm) 12 formed by GaAs buffer layer (150 n) by MOCVD method.
m) 4, GaAs channel (15 nm) 5, AlGaA
s (15 nm) 6, GaAs cap layer (10 nm) 7
Select to grow. During the selective growth, trimethylgallium ((CH ₃ ) ₃ Ga: TMG) and arsine (AsH ₃ ) were used as source gases for the growth of GaAs, and TMG, AsH ₃ , and trimethylaluminum ((( CH _{3) 3} Al: TMA) was used as the raw material gas. In addition, as a doping raw material for the GaAs channel,
Disilane (Si ₂ H ₆ ) was used. These source gases are
Hydrogen was used as a carrier gas from the raw material container to the growth chamber for flow rate control. The selective growth was performed in the range of 600 to 700 ° C. AlGaAs126 has an elemental composition of A
l: 0.3, Ga: 0.7, As: 1.0 are shown in a simplified manner. Further, the doping concentration of Si in the GaAs channel 5 is about 3 × 10 ¹⁸ / cm ³ .

FIG. 2C: Next, Al is deposited on the substrate by a vacuum evaporation method and an Al gate electrode 8 is formed by photolithography and dry etching. Here, the Al gate electrode 8 has a width of 400 nm, and the width thereof is 50 nm wider at the end portion than the opening portion 12 for selective growth.

FIG. 2D: Using the Al gate electrode 8 as a mask, the insulating films SiO ₂ 2 and SiN 3 are partially removed by dry etching.

FIG. 2E: Of the insulating films SiO ₂ 2 and SiN ₃ remaining under the gate electrode 8, only SiO ₂ 2 is removed by wet etching. For wet etching, S
A hydrofluoric acid-based etching solution having an etching rate about 6 times that of SiO ₂ than that of iN was used.

FIG. 2F: Again, the MOCVD method is used to selectively grow the n-type GaAs 9 serving as the source and drain regions. The selective growth is performed in the temperature range of 500 to 600 ° C., Si ₂ H ₆ is added to n-type GaAs as a doping material, and the carrier concentration is about 3 × 10 ¹⁸ / cm ³ .

Thereafter, as shown in FIG. 1, n-type GaAs
A metal electrode portion of Au / Ge / Ni is formed on 9 by vacuum vapor deposition and superheat alloying treatment, and the drain electrode 10 and the source electrode 1 are formed.
Set to 1. In addition, as the selective growth layer to be the source and drain regions, Ge doped with As to be n-type may be used. By adopting the selective growth portion having such a structure for the source and drain regions, the electric resistance of the source portion can be significantly reduced and the driving capability of the device can be enhanced.

A gate length of 0.3 μm and a gate width of 1 made by the GaAs channel FET according to this embodiment and the GaAs channel FET of the conventional structure described with reference to FIGS. 3 and 4.
The following is a comparison of the number of leak current generating elements in the gate electrode portion of 10,000 product elements of 0 μm.

[0061] That is, according to this embodiment, the number of defective products can be significantly reduced.

Next, the GaAs channel FET of this embodiment
The gate breakdown voltage and the transconductance of 10,000 product elements were compared between the conventional GaAs FET shown in FIG. 8 (an element that has undergone a process in which the epitaxial film is likely to be damaged during processing of the gate electrode).

Gate breakdown voltage Transconductance (unit: Volt) (Unit: millisiemens / mm) FET of the present embodiment: 5 to 7 600 to 800 Conventional FET: 3 to 5 300 to 450 FET of the present invention as described above According to the method, an FET having a high breakdown voltage and a large current driving capability can be manufactured.

A further feature of this embodiment is that high integration is possible by making the device structure planar. This resulted in a significant reduction in the disconnection failure of the inter-element wiring as compared with the conventional IC which employed mesa etching for electrical isolation between elements. The following results are obtained by comparing the defective parts of the inter-element wiring with respect to 1000 products of 20,000-gate logic integrated circuits having 100,000 FET devices.

Defects of Step Defects in Inter-Element Wiring ICs of this Example: 2 places Conventional IC: 76 places Example 2 An InGaAs channel FET of Example 2 of the present invention is shown in FIG.
The description will be made using 0.

FIG. 10A: Semi-insulating GaAs substrate 12
A SiO ₂ mask (200 nm) 121 and a SiN mask (100 nm) 122 are formed on the substrate 0. The mask opening 123 formed at this time has a width of 300 nm and a length of 10 μm.

FIG. 10B: The GaAs buffer layer (15) is formed in the mask opening 123 by selective growth by MOCVD.
0 nm) 124, InGaAs channel (5 nm) 12
5, AlGaAs (20 nm) 126, and GaAs cap (10 nm) 127 are sequentially grown. Where InG
The elemental composition of the aAs channel 125 is In: 0.2, G
a: 0.8 and As: 1.0 are shown in a simplified manner. The channel is doped with Si and its concentration is about 1 × 10 ¹⁹ / cm ³ . Selective growth temperature is 650 ℃
Then, trimethyl indium ((CH ₃ ) ₃ In: TMI) was used as a raw material of In.

The steps from FIG. 10C to FIG. 10E are the same as those in the first embodiment.

FIG. 10 (f): By MOCVD again, n
Type GaAs 131 is selectively grown. Selective growth is 500 ℃
I went there. a source electrode 132 on the n-type GaAs 131,
By forming the drain electrode 133, a desired FET can be formed.

Example 3 InGaAs lattice-matched to InP of Example 3 of the present invention
The channel FET will be described with reference to FIG.

FIG. 11A: Using an InP substrate, SiO ₂ mask (200 nm) 141, S as in the second embodiment.
An iN mask (100 nm) 142 is formed.

FIG. 11B: In the mask opening 143
P buffer layer (150 nm) 144, InGaAs channel (15 nm) 145, InAlAs (30 nm)
146, GaAs cap (10 nm) 147 in this order M
Selective growth is performed by the OCVD method. Here, PH ₃ was used as the P raw material of InP. The selective growth temperature is 600 ° C.

11 (c) to 11 (e) are the same as those in the first and second embodiments.

FIG. 11F: The InP selective growth portion 151 is grown by the second MOCVD. Further, the source electrode 15
2. The drain electrode 153 is formed to complete the FET.

Example 4 GaAs / AlGaAs HEMT of Example 4 of the present invention
Will be described with reference to FIG.

FIG. 15 shows a sectional structural view after the element is completed. The process of crystal growth by selective growth is almost the same as that shown in Examples 1 to 3. here,
Two-dimensional electron gas is used for the channel of the transistor.

A GaAs / AlGaAs multi-layer 261 is formed on the semi-insulating GaAs substrate 260 using an insulating film pattern.
Is 300 nm and undoped GaAs262 is 200 n
m, non-doped AlGaAs 265 to 10 nm, n-type A
lGaAs266 to 100 nm, undoped GaAs2
67 is selectively grown in the order of 10 nm.

Next, the gate electrode 273 is formed, and the n-type GaAs 27 of the source and drain portions is formed by the second crystal growth.
0 grows selectively.

After that, the source electrode 271 and the drain electrode 272 are formed to complete the HEMT.

Here, the sheet concentration of the two-dimensional electron gas 263 is 1 × 10 ¹² / cm ² , and the channel length is 100 n.
m. Operate the device with a drain voltage of 1 volt, and
A noise figure of 0.5 dB at 1 GHz was obtained.

In the above-described first, second, third, and fourth embodiments, the manufacturing process of the InGaAs channel and GaAs channel FETs has been described. As the crystal material to be used, the following materials can be selected in addition to the materials shown in the above embodiment.

(1) When a GaAs substrate is used, a GaAs buffer and Ga are formed in the upper and lower selective growth layers including the channel.
An As channel, InGaP or InAlGaP cap is used, and GaA is used for the selective growth layers of the source and drain portions.
s or InGaAs is used. (2) When a GaAs substrate is used, GaA is formed in the upper and lower selective growth layers including the channel.
s buffer, InAs channel, and GaAs cap are used.
Alternatively, a sequentially laminated structure of InGaAs and GaAs is used. In this case, if the thickness of the InAs channel is about 10 nm or less, the crystal strain due to the difference in the lattice constant between GaAs and InAs and the deterioration of the device characteristics caused by the crystal dislocation can be suppressed to a negligible level. Note that an InSb channel may be used instead of the InAs channel.

Example 5 A bipolar transistor of Example 5 of the present invention will be described with reference to FIG.

FIG. 5A: SiN pattern 42 is formed on semi-insulating GaAs substrate 41, and MOCVD is performed on the pattern opening.
N-type GaAs 43 is selectively grown by the method. At this time, S
The thickness of iO ₂ is 0.5 μm, and the thickness of the n-type GaAs 43 is 0.5 μm, which is almost the same. Then again Si
An N pattern 44 is formed, and an n-type GaAs collector layer 45 and a p-type AlGaAs base layer 46 are sequentially formed in the opening of the pattern MO.
Selective growth is performed by the CVD method. The SiN pattern 44 has a thickness of 0.3 μm, and the n-type GaAs collector layer 45 has a thickness of 0.3 μm.
Is 0.25 μm, and the p-type AlGaAs base layer 46 is 0.
It is 1 μm. Therefore, the p-type AlGaAs base layer 46
The upper half grows on the edge of the SiN pattern 44.

FIG. 5B: Further SiO ₂ pattern (thickness 2
50 nm) 47 is formed, and n-type AlGa is formed in the pattern opening.
The As emitter layer 48 has a thickness of 50 nm and the n-type GaAs layer 4 is formed.
9 and 100 nm in thickness, and an n-type InGaAs emitter contact layer 50 is selectively grown by MOCVD to a thickness of 200 nm. Also in this case, the n-type InGaAs emitter contact layer 50 grows on the edge of the opening of the SiO ₂ pattern 47.

FIG. 5C: The SiO ₂ pattern 47 is removed by etching, and then the SiN pattern 51 is formed. S
A p-type GaAs base extraction layer 52 is selectively grown in the opening of the iN pattern 51 by MOCVD. Next, Au / Z
The base electrode 57 is formed by vacuum-depositing n.

FIG. 5D: SiO ₂ pattern 53, SiN
An n-type GaAs collector extraction layer 54 is selectively grown in the openings of the patterns 51 and 47 by MOCVD.

FIG. 5E: SiO ₂ pattern 53, SiN
An opening is formed by a photoresist pattern above the n-type InGaAs emitter contact layer 50 in the pattern 51 to form a SiO ₂ pattern 58. Next, a metal of Au / Ge is vapor-deposited on the n-type InGaAs emitter contact layer 50 and the n-type GaAs collector extraction layer 54 exposed on the surface to form an emitter electrode 55 and a collector electrode 56, respectively.

FIG. 6 is a plan view of the bipolar transistor manufactured in this step. In FIG. 6, the collector electrode is 6
1, the base electrode is 57, and the emitter electrode is 63.

Further, according to this embodiment, in the bipolar transistor, an element structure having a small parasitic capacitance and therefore suitable for high speed operation can be realized. Below, the maximum oscillation frequency (fma
The value of x) is shown in comparison between the structure according to the present embodiment shown in FIG. 5 and the conventional structure shown in FIG.

Maximum oscillation frequency (fmax) (unit: gigahertz) Element of this example: 150 to 180 Conventional element: 70 to 100 In addition to the crystal materials shown in this example, the following combinations of crystals are available. Basically, the device can be manufactured.

(1) Substrate; GaAs, collector layer; Ga
As, base layer; GaAs, emitter layer; InGaP,
Contact layer; InGaAs. (2) Substrate; InP, collector layer; InGaAs or InP, base layer; InGaAs, emitter layer; InA
lAs, contact layer; InGaAs.

(3) Substrate; GaAs, collector layer; Ga
As, base layer; Ge, emitter layer; GaAs.

(4) Substrate; GaAs, collector layer; Ga
As, base layer; InGaAs, emitter layer; GaAs
Or AlGaAs, contact layer; GaAs or I
nGaAs.

Needless to say, the order of stacking the collector layer, the base layer, and the emitter layer on the substrate may be the order of the emitter layer, the base layer, and the collector layer.

Example 6 An FET using selective growth of tungsten for forming a gate metal of Example 6 of the present invention will be described with reference to FIG.

FIG. 14A: Semi-insulating GaAs substrate 12
A SiO ₂ mask 121 and a SiN mask 122 are formed in this order by CVD on the substrate 0, and a mask opening 123 is provided.

FIG. 14B: The GaAs buffer layer 124 is formed in the mask opening 123 by the same procedure as in FIG. 10B.
InGaAs channel 125, AlGaAs 126, G
The aAs cap 127 is selectively grown by MOCVD. Next, Si 170 is selectively grown on the GaAs cap 127. For selective growth of Si170, SiCl
₄ , a Si raw material containing chlorine such as SiCl ₂ H ₂ , or a Si hydride such as Si ₂ H ₆ or SiH ₄ is used. Further, in order to give the grown Si film conductivity,
Phosphorus is added as phosphine (PH _3).

Next, by the CVD method of tungsten, S
Tungsten 171 is selectively grown only on i170. Here, the tungsten grown above the SiN mask 122 also grows laterally.

FIG. 14C: Tungsten selective growth part 1
71 as a mask, the SiO ₂ mask 121 and SiN
A part of the mask 122 is removed by dry etching, and Si
An O ₂ mask 172 and a SiN mask 173 are formed.

FIG. 14D: The SiO ₂ mask 172 is removed by wet etching.

FIG. 14 (e): GaAs by MOCVD
The selective growth portion 174 is formed.

Next, the drain electrode 175 and the source electrode 1
The FET is completed by forming 76 on the GaAs selective growth portion 174.

Seventh Embodiment An integrated circuit (IC) having an inverter circuit according to a seventh embodiment of the present invention will be described with reference to FIG.

A cross-sectional view of the inverter circuit is shown in FIG. 16 (a), and a circuit configuration diagram is shown in FIG. 16 (b). FIG. 16A: Enhancement type FET (EFET) and depletion type FE formed on the substrate 190.
The T (DFET) has basically the same structure as the structure of the FET described in the first embodiment. In this embodiment, the GaAs channels 195 and 196 have different thicknesses, and
Has a thinner channel thickness than DFET. The thickness of the channel portion is controlled by selectively growing the channel portion by MOCVD so that the dimensions La and Lb of the opening are L as shown in FIG.
Let a be larger than Lb. As La, for example, 5
When Lb is 250 nanometers at 00 nanometers, the EFET has a GaAs channel section thickness of 15 nanometers, and the DFET has a GaAs channel section thickness of 30 nanometers. In this case, EFET and D
The epitaxial film of the channel portion of the FET can be grown simultaneously by selective growth.

FIG. 16B: The basic constitutional units of the inverter circuit composed of the EFET and the DFET are shown as the first stage and the second stage. In the first stage, Vdd represents the power supply voltage, Vin represents the input voltage to the EFET, and Vout represents the output voltage from the first stage inverter.

Example 8 A pattern layout of an integrated circuit (IC) having an inverter circuit of Example 8 of the present invention will be described with reference to FIG.

In this embodiment, by arranging the DFETs and EFETs constituting the inverter circuit so that their gates are oriented at right angles to each other, the arrangement of the DFETs and EFETs becomes a square pattern as a whole.

With the arrangement of this embodiment, by utilizing the selective growth of the present invention, the characteristics of the element such as the threshold voltage are different depending on whether the direction of the gate electrode of the FET is parallel to the orientation flat or perpendicular to it. It is based on finding that there is no difference.

Here, assuming that the vertical and horizontal dimensions of the pattern of this embodiment are L3 and L4, respectively, L3 = L4 = 10 μm.
m, and the area is 100 μm ² .

On the other hand, FIG. 17 shows the pattern arrangement of the inverter circuit in the conventional compound semiconductor integrated circuit. The DFET and the EFET forming the inverter circuit are arranged such that the width directions of the gates thereof are parallel to each other and also parallel to the orientation flat on the wafer (substrate). Here, the compound semiconductor GaA
In the case of a substrate made of s, InP or the like, the direction of this orientation flat coincides with the direction parallel to the [-1,1,0] direction (or [1, -1,0] direction) shown in FIG.
Thus, the pattern arrangement of the DFET and EFET of the inverter circuit in the conventional compound semiconductor integrated circuit is
Since the directions of the gates are parallel to each other, the DFET
Since there is no freedom in arranging the EFET and the EFET, it is impossible to intentionally reduce the pattern area of both FETs as a whole.

Vertical and horizontal dimensions L1 and L2 of the conventional pattern
Is L1 = 10 μm, L2 = 15 μm, and the area is 1
It becomes 50 μm ² .

Therefore, according to this embodiment, the area of the pattern becomes about two thirds. As a result, the DFET and EFET of the inverter circuit in the integrated circuit can have their gate electrodes oriented at right angles to each other, and therefore the element area can be reduced.

Example 9 A pattern layout of a memory IC including an FET according to Example 9 of the present invention will be described with reference to FIG. In FIG. 19, the channel layer region 220 is n-type GaAs or n-type InG.
This is a portion where a layer containing aAs is selectively crystal-grown on a substrate, and a gate electrode pattern is formed thereon. The gate electrodes 223, 224, and 225 are not necessarily parallel to the direction of the orientation flat of the substrate, and have a portion bent at an angle or at a right angle. In the conventional memory IC, the gate electrode did not have a bent portion, but by adopting the selective growth of the present invention, it was found that there is no inconvenience in the characteristics of the element even if the gate electrode is bent. The layout area could be reduced by about 20%.

Embodiment 10 As an embodiment of an integrated circuit (IC), the difference between the present invention and the conventional method regarding the distance between elements in the IC or the isolation interval will be described in detail. FIG. 20 shows a conventional F
A part of IC using ET is shown. FIG. 21 shows an embodiment of an IC using the FET of the present invention, and FIG. 22 shows the H of the present invention.
An example of an IC using BT will be shown.

In FIG. 20, (a) shows two FETs 1 and FE.
The top view of T2, (b) is the sectional drawing. Figure 20
In (a), the channel layers 237 of the two FETs are separated from each other by the step shown by the mesa etching portion 230.
Here, this separated distance is called an isolation interval. The gate electrode 232 lies on the step of the mesa etching portion, and its cross section is shown in FIG. The gate electrode is liable to cause defects such as irregular shape and cutting in the metal pattern at the step portion of the mesa etching.
Further, when a bias voltage is applied to the gate electrode of the FET1, the FET2 is passed through the buffer layer 236 and the substrate 235.
However, there is a problem that the desired element characteristics cannot be obtained due to the influence of the voltage-current characteristics of the above. Therefore, it is necessary to secure the isolation interval L1 of the conventional IC of 30 μm or more.

Next, an embodiment of the IC of the present invention using the FET will be described with reference to FIG. FIG. 21 shows a part of the cross-sectional structure of the IC, and the two FET1 and FET2 are separated by an isolation distance L2. The crystal growth portions 242 and 243 including the FET channel layer are selectively formed in the pattern opening of the insulating film 241. In this embodiment, part of the gate electrodes 244 and 245 is formed on the insulating film in a plane so that there is no step with the crystal growth portion. By adopting such a structure, FET1
Even if a bias voltage is applied to the gate electrode 245 of the
It was found that the electrical properties of T2 were not affected. In this embodiment, the isolation interval L2 is 1 μm. As a result, the chip area of the IC including 500 FETs could be reduced by about 30%.

Next, an embodiment of the IC of the present invention using a heterojunction bipolar transistor (HBT) will be described with reference to FIG. FIG. 22 shows HB in a part of such IC
The plane layout of T is shown. In each of the HBT1 to HBT3 elements, an HBT element region 250 formed of a crystal growth portion formed on a substrate is separated by an isolation interval L3. As in the embodiment of FIG. 21, an insulating film is used for isolation. In this embodiment, the isolation distance L3 is 1 μm. On the other hand, IC using conventional HBT
However, isolation was secured by partially removing the epitaxial layer by mesa etching. Therefore, the isolation interval needs to be 5 μm or more. According to this embodiment, the chip area of the IC including 200 HBTs can be reduced from the conventional ² × ² mm ² to 1 × ¹ mm ² . In addition, since the distance between the elements can be shortened to one fifth, the inter-element wiring capacitance can also be reduced to one fifth and the signal transmission speed at high frequencies is improved.

[0119]

As described in the above embodiments, the main features of the present invention are that high integration of elements and high manufacturing yield can be achieved by planarization.

[Brief description of drawings]

FIG. 1 is a perspective view of a GaAs / AlGaAs heterojunction FET according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a GaAs / AlGaAs heterojunction FET of Example 1 of the present invention.

FIG. 3 is a manufacturing process diagram of a conventional FET.

FIG. 4 is a cross-sectional view of a conventional FET.

FIG. 5 is a manufacturing process diagram of a bipolar transistor of Example 5 of the present invention.

FIG. 6 is a plan view of a bipolar transistor of Example 5 of the present invention.

FIG. 7 is a manufacturing process diagram of a conventional bipolar transistor.

FIG. 8 is a manufacturing process diagram of a conventional FET.

FIG. 9 is a perspective view (a) and an AB sectional view (b) of a GaAs / AlGaAs heterojunction FET according to the first embodiment of the present invention.

FIG. 10 is an InGaAs channel F according to a second embodiment of the present invention.
It is a manufacturing-process figure of ET.

FIG. 11: I that is lattice-matched to InP of Example 3 of the present invention
nGaAs channel FET FIG.

FIG. 12 is a cross-sectional view of a conventional bipolar transistor.

FIG. 13 is a diagram showing the crystal orientation dependence of the cross-sectional shape of the selectively grown portion of the present invention. In FIG. 13 (a), the crystal plane orientation is [1,
FIG. 13B is a sectional view seen from the [1,0] direction, and FIG. 13B is a sectional view seen from the [1, -1,0] direction of the crystal plane orientation. .

FIG. 14 is a manufacturing process diagram of an FET in which selective growth of tungsten is used for forming a gate metal in Example 6 of the present invention.

FIG. 15: GaAs / AlGaAs of Example 4 of the present invention
It is sectional drawing of system HEMT.

FIG. 16 is a cross-sectional view (a) and a circuit configuration diagram (b) of an integrated circuit (IC) including an inverter circuit according to a seventh embodiment of the present invention.

FIG. 17 is a plan layout view of an IC including a conventional FET.

FIG. 18 is a plan layout view of an IC having an inverter circuit according to an eighth embodiment of the present invention.

FIG. 19 is a memory I including the FET according to the ninth embodiment of the present invention.
It is a plane layout drawing of C.

FIG. 20 is a view showing an isolation part of an IC using a conventional FET, and FIG. 21 (a) is a plan view.
(B) is a sectional view.

FIG. 21 is a sectional view showing an isolation portion of an IC including an FET according to Example 10 of the present invention.

FIG. 22 is a plan view showing an isolation part of an IC including an HBT of Example 10 of the present invention.

[Explanation of symbols]

1 ... Substrate, 2 ... SiO ₂ , 3 ... SiN, 4 ... GaAs buffer layer, 5 ... GaAs channel, 6 ... AlGaA
s, 7 ... GaAs, 8 ... Gate electrode, 9 ... GaAs, 1
0 ... Drain electrode, 11 ... Source electrode, 12 ... Opening part,
21 ... Substrate, 22 ... InAlAs buffer, 23 ... In
GaAs channel, 24 ... InAlAs, 25 ... InG
aAs cap, 26 ... Photoresist pattern, 27 ...
Mesa etching part, 28 ... Drain electrode, 29 ... Source electrode, 30 ... Groove type etching part, 31 ... Gate electrode, 3
2 ... Proximity portion of gate electrode and channel, 41 ... Substrate, 4
2 ... SiN pattern, 43 ... n-type GaAs, 44 ... SiN
Pattern, 45 ... n-type GaAs collector layer, 46 ... p-type A
1 GaAs base layer, 47 ... SiO ₂ , 48 ... n-type Al
GaAs emitter, 49 ... N-type GaAs, 50 ... N-type I
nGaAs emitter contact layer, 51 ... SiN pattern, 52 ... p-type GaAs base extraction layer, 53 ... SiO
₂ pattern, 54 ... n-type GaAs collector extraction layer, 55
... emitter electrode, 56 ... collector electrode, 57 ... base electrode, 58 ... SiO ₂ pattern, 61 ... collector electrode, 62
... Base electrode lead portion, 63 ... Emitter electrode, 64 ...
Base-collector junction surface, 71 ... Substrate, 72 ... N-type Ga
As, 73 ... n-type GaAs collector layer, 74 ... p-type base layer, 75 ... n-type AlGaAs, 76 ... n-type GaAs,
77 ... Insulating film mask, 78 ... P-type base part, 79 ... N-type GaAs emitter part, 80 ... High resistance part, 81 ... Insulating film mask, 82 ... AuZn electrode, 83 ... Insulating film side wall, 84 ...
AuGeNi electrode, 85 ... Insulating film mask, 86 ... Emitter, 87 ... Base, 88 ... Collector, 89 ... Insulating film, 9
0 ... Base-collector parasitic capacitance generating portion, 100 ... Substrate, 101 ... Non-doped GaAs buffer, 102 ... N
Type GaAs channel, 103 ... Undoped AlGaA
s, 104 ... Non-doped GaAs, 105 ... Metal film, 1
06 ... Photoresist pattern, 107 ... Gate electrode, 1
08 ... p-type conductive layer, 109 ... n′-type conductive layer, 110 ... n
Type GaAs selective growth part, 112 ... Drain electrode, 113
Source electrode, 120 substrate, 121 SiO ₂ mask, 122 SiN mask, 123 mask opening, 1
24 ... GaAs buffer layer, 125 ... InGaAs channel, 126 ... AlGaAs, 127 ... GaAs cap, 128 ... Gate electrode, 129 ... SiO ₂ mask,
130 ... SiN mask, 131 ... GaAs selective growth part,
132 ... Source electrode, 133 ... Drain electrode, 140 ...
Substrate, 141 ... SiO ₂ mask, 142 ... SiN mask, 143 ... Mask opening, 144 ... InP buffer layer, 145 ... InGaAs channel, 146 ... InAl
As: 147 ... GaAs cap, 148 ... Gate electrode, 149 ... SiO ₂ mask, 150 ... SiN mask,
151 ... InP selective growth part, 152 ... Source electrode, 15
3 ... Drain electrode, 160 ... Substrate, 161 ... SiO ₂ pattern, 162 ... AlGaAs, 163 ... GaAs, 16
4 ... AlGaAs, 165 ... GaAs, 170 ... Si,
171 ... Tungsten selective growth portion, 172 ... SiO ₂ mask, 173 ... SiN mask, 174 ... GaAs selective growth portion, 175 ... Drain electrode, 176 ... Source electrode, 1
90 ... Substrate, 191 ... Source electrode, 192 ... Drain electrode, 193 ... 194 ... Gate electrode, 195 ... GaAs channel, 196 ... GaAs channel, 197 ... GaAs
Selective growth portion, 198 ... Insulating film, 199 ... Insulating film, 200
... wafer, 201 ... integrated circuit chip, 202 ... orientation flat (OF), 203 ... area in integrated circuit chip, 204 ... EFET and DFE in integrated circuit
T plane arrangement frame, 205 ... Drain D1, 206 ... Gate G1, 207 ... Source S1 / Drain D2, 208 ...
Gate G2, 209 ... Source S2, 210 ... Drain D
1, 211 ... Gate G1, 212 ... Source S1 / Drain D2, 213 ... Gate G2, 214 ... Source S2, 2
15 ... Planar arrangement frame of EFET and DFET, 220 ... Channel layer region, 221 ... Gate electrode 1, 222 ... Gate electrode 2, 223 ... Gate electrode 3, 224 ... Gate electrode 4,
225 ... Gate electrodes 5, 226 ... Gate electrodes 6, 230
... Mesa etching part, 231, ... Gate electrode, 232 ... Gate electrode, 233 ... Source electrode, 234 ... Drain electrode, 235 ... Substrate, 236 ... Buffer layer, 237 ... Channel layer, 238 ... Cap layer, 240 ... Substrate, 241
... Insulating film, 242 ... Crystal growth part, 243 ... Crystal growth part,
244 ... Gate electrode, 245 ... Gate electrode, 246 ... Source electrode, 247 ... Source electrode, 250 ... HBT element region, 251, ... Collector electrode, 252 ... Base electrode, 25
3 ... Emitter electrode, 254 ... Wiring, 260 ... Substrate, 26
1 ... GaAs / AlGaAs multi-layer, 262 ... Undoped GaAs, 263 ... Two-dimensional electron gas, 264 ... Si
N, 265 ... Non-doped AlGaAs, 266 ... N-type A
lGaAs, 267 ... Undoped GaAs, 268 ... S
iO ₂ , 269 ... SiN, 270 ... n-type GaAs, 27
1 ... Source, 272 ... Drain, 273 ... Gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/73 29/784 9054-4M H01L 29/78 301 X (72) Inventor Masaru Miyazaki Tokyo 1-280, Higashi Koigokubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd.

Claims (20)

[Claims] 1. A high-resistance substrate, a first field-effect transistor and an insulating film formed side by side on the high-resistance substrate, wherein a gate electrode of the first field-effect transistor is arranged in a gate width direction. A semiconductor device, which is formed so as to extend onto the insulating film. 2. The high resistance substrate is a single crystal, and the gate width direction of the gate electrode of the first field effect transistor is oriented in the [-1,1,1] axis direction of the high resistance substrate. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the source / drain contact layer is in contact with the side surface of the active region of the first field effect transistor. 4. The semiconductor device according to claim 3, wherein an insulator is interposed between the gate electrode and the source / drain contact layer. 5. The active region is GaAs, AlGaAs,
InGaAs, InAlAs, InP, InGaP, I
It is made of a semiconductor material selected from the group consisting of nAlGaP, InAs and InSb, and the source / drain contact layers are made of GaAs, InGaAs and In.
5. The semiconductor device according to claim 3, which is made of a semiconductor material selected from the group consisting of P, InAs, InSb, and Ge. 6. The high resistance substrate is a single crystal, and the gate electrode of the first field effect transistor and the gate electrode of the second field effect transistor formed on the high resistance substrate have their gates. The width direction is different.
The semiconductor device described. 7. The insulating film is formed so as to planarly surround the periphery of the first field effect transistor, and is formed on the high resistance substrate adjacent to the first field effect transistor. The semiconductor device according to claim 1, wherein the semiconductor device is electrically isolated from the third field effect transistor. 8. The insulating film planarly surrounds, in addition to the first field effect transistor, a fourth field effect transistor formed on the high resistance substrate. 5. The semiconductor device according to claim 3, wherein is an enhancement type, the fourth field effect transistor is a depletion type, and both transistors form an inverter circuit. 9. The insulating film has a portion having a length between the first field effect transistor and the third field effect transistor of 1 μm or more and less than 30 μm.
Or the semiconductor device according to 8. 10. A high-resistance substrate, a first bipolar transistor and an insulating film formed side by side on the high-resistance substrate, wherein a base layer of the first bipolar transistor extends onto the insulating film. A semiconductor device characterized by being formed locally. 11. The first bipolar transistor has an active region composed of an emitter, a base and a collector layer and a semiconductor connecting the active region and a metal electrode, and the active region and the semiconductor are GaAs, AlGaAs and I.
nGaAs, InP, InGaP, InAs and Ge
11. The semiconductor device according to claim 10, which is made of a semiconductor material selected from the group consisting of: 12. The insulating film is formed by planarly surrounding the periphery of the first bipolar transistor, and is formed on the high resistance substrate adjacent to the first bipolar transistor. 11. The semiconductor device according to claim 10, wherein the bipolar transistor is electrically isolated from the bipolar transistor. 13. The first bipolar transistor and the second bipolar transistor are a collector or emitter contact layer formed on the high resistance substrate, and a collector or emitter layer formed on the collector or emitter contact layer. 13. The semiconductor device according to claim 12, further comprising: a base layer formed on the collector or emitter layer. 14. The insulating film has a portion where the length between the first bipolar transistor and the second bipolar transistor is 1 μm or more and less than 5 μm between the collector or emitter contact layers of both transistors. The semiconductor device according to claim 13. 15. A step of forming an active region by a selective growth method of a semiconductor material using a mask having a pattern of an active region, and a semiconductor material using a mask having a pattern of a semiconductor layer connecting the active region and an electrode metal. 2. A method of manufacturing a semiconductor device, which comprises the step of forming the semiconductor layer by the selective growth method. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the selective growth method is a vapor phase growth method using vapor of a gas or a liquid source, or a molecular beam epitaxy method. 17. The semiconductor device is a field effect transistor, the semiconductor layer connecting the active region and the electrode metal is a source / drain contact layer, and an insulating film having an opening is formed on a high resistance semiconductor substrate. A step of forming the active region in the opening of the insulating film, a step of forming a gate electrode on the active region so as to extend over the insulating film, and forming the insulating film on a side surface of the active region. Forming a region for forming the source / drain contact layer so that the source / drain contact layer is exposed, and a portion under the gate electrode on at least one side in the source / drain direction remains. 16. The method of manufacturing a semiconductor device according to claim 15, further comprising the step of forming the source / drain contact layer in a drain contact layer formation region. 18. The step of forming an insulating film having an opening on the high resistance semiconductor substrate includes the step of forming a first insulating film on the high resistance semiconductor substrate and the step of forming a first insulating film on the first insulating film. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising: a step of forming a second insulating film made of a material different from that of the first insulating film; and a step of opening the first and second insulating films. 19. The semiconductor device is a bipolar transistor, the active region is an emitter, a base and a collector layer, and the semiconductor layer connecting the active region and an electrode metal is a base contact layer, a collector or emitter contact layer, a base. Forming a first insulating film having an opening on the high resistance semiconductor substrate, which is an extraction layer and a collector or emitter extraction layer; and forming the collector or emitter contact layer on the opening of the first insulation film And a step of forming a second insulating film having an opening on the collector or emitter contact layer, a step of forming the collector or emitter layer in the opening of the second insulating film, Alternatively, the base layer is formed on the emitter layer so as to extend onto the second insulating film. A step of forming a third insulating film having an opening on the base layer, a step of forming the emitter or collector layer on the opening of the third insulating film, and a step of forming the emitter or collector layer on the emitter or collector layer. A step of forming the emitter or collector contact layer, a step of forming a fourth insulating film having an opening on the base layer, and a step of forming the base lead layer in the opening of the fourth insulating film. A step of forming a fifth insulating film having an opening on the collector or emitter contact layer formed on the high resistance semiconductor substrate, and the collector or the emitter at the opening of the fifth insulating film. The method for manufacturing a semiconductor device according to claim 15, further comprising the step of forming a lead layer. 20. The step of forming the emitter or collector contact layer on the emitter or collector layer, wherein the emitter or collector contact layer is formed to extend onto the third insulating film. Manufacturing method of semiconductor device.