JPH05327688A - Synchronization device - Google Patents

Abstract

PURPOSE:To prevent a synchronization pattern from being hardly detected due to the decrease in a receiving level and increase in a bit error rate. CONSTITUTION:A synchronization pattern detecting means compares a bit string of a signal demodulated by a demodulator 3 after reception by a reception section 2 with a synchronization pattern and when a discordant bit number is less than a correlation threshold level, it is discriminated that the synchronization pattern is detected. The correlation threshold value is set by a decision device 10 based on a level of a received signal by a level measurement device 4 together with a bit error rate of a demodulated signal by a bit error rate computing element 8. When a consecutive detection frequency of a counted synchronization pattern reaches a backward protection stage number or over, a synchronization detecting frequency counter 18 discriminates that the synchronization is established. When the consecutive undetected frequency of the counted synchronization pattern reaches the forward protection stage number or over, the undetected frequency counter means 19 discriminates the synchronization is varnished. The protection stage number is set by forward and backward protection stage number decision devices 16, 17 based on the correlation threshold value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing device used for digital communication.

[0002]

2. Description of the Related Art In time division multiple access digital radio communication, a plurality of radio lines separated by time division are formed between one base station and a plurality of slave stations. In this system, a plurality of slave stations physically located at different positions divide a signal of the same frequency on the time axis for use. That is, a fixed length of time (frame), which is the basic cycle of signal transmission and reception, is determined, and this frame is divided into a plurality of small sections (time slots). Each slave station is assigned to each of these time slots, and a plurality of wireless lines are formed by transmitting or receiving a signal with the base station using the assigned time slot.

For this reason, it is necessary for each slave station to adjust the transmission timing so that the burst signal to be transmitted does not overlap in time with the transmission signals of other stations in space and does not interfere with each other.

As a method of adjusting this timing, one base station sends a synchronization signal serving as a time reference to each slave station, and each slave station detects this synchronization signal to adjust the transmission timing. There is a way to do it. According to this method, the slave station knows the time position of the line allocated to itself by using the detected synchronization signal as a time reference, and acquires the line of its own station.

As an example, FIG. 3 shows a frame structure when N slave stations perform bidirectional communication with one base station using the same carrier. In FIG. 3, Ri (i =
, 1, 2, 3, 3, ..., N) are time slots for transmission from the base station to the slave station i, and Ti (i = 1, 2, 3, ..., N) are time slots for transmission from the slave station i to the base station. is there. Each time slot contains a different pattern of synchronization signal. The synchronization pattern is composed of, for example, a 32-bit bit string.

The slave station i detects the synchronization pattern of its own station from the received signal sequence in order to capture the line (downlink of its own station) that receives the signal sent from the base station.
Establish synchronization. Then, the line that transmits the signal to the base station using the detected synchronization signal as a time reference (local station uplink)
By measuring the time position of, the own station's uplink is captured.

When the slave station i detects the synchronization pattern of its own station from the received signal sequence, it compares the received signal sequence with the predetermined synchronization pattern of its own station bit by bit. As a result, if the number of unmatched bits is equal to or less than a certain number (correlation threshold value), it is considered that the sync signal is detected. By the way, since the sync signal is inserted at every fixed frame time, the next sync signal is ahead of the detected sync signal by a fixed frame, so that when the next sync signal is searched, there is a sync signal. Search only within the predicted time range (aperture). Then, it is considered that the synchronization is established at the time when the detection is continuously performed a predetermined number of times (the number of backward protection stages) over a plurality of frames within the aperture section. Further, if the synchronization pattern is not continuously detected a predetermined number of times (the number of forward protection steps) over a plurality of frames in the state where the synchronization is established, it is considered that the synchronization is lost.

[0008]

In the above synchronization establishing method, it becomes difficult to detect the synchronization pattern when the reception level of the radio signal is low or the bit error rate is large in the slave station. This can make it difficult to establish synchronization or easily lose synchronization.

It is an object of the present invention to provide a synchronization device capable of preventing the synchronization pattern from becoming difficult to detect due to such a decrease in reception level and an increase in bit error rate.

[0010]

According to the present invention, a receiving means for receiving a digital modulated signal, a demodulating means for demodulating the digital modulated signal into a digital signal, and a bit string of the digital signal demodulated by the demodulating means. A synchronization device comprising a synchronization pattern detecting means for determining that a synchronization pattern has been detected when the number of unmatched bits obtained as a result of comparison with a specific synchronization pattern bit by bit is equal to or less than a predetermined correlation threshold, and a correlation threshold. The value is set based on the level of the received signal or the bit error rate of the demodulated digital signal.

Further, according to the present invention, the number of times the synchronization pattern is continuously detected by the synchronization pattern detecting means is counted,
If the number of times of counting is equal to or greater than the number of backward protection steps, the number of times of detection that determines that synchronization has been established and the number of times that the synchronization pattern is not continuously detected by the synchronization pattern detection means are counted, and A non-detection number counter means for determining that the synchronization is lost when the number of protection stages is exceeded, a front protection stage number determination means for determining the front protection stage number based on the set correlation threshold value, and a set correlation threshold value. And a rear protection stage number determining means for determining the rear protection stage number based on the above.

[0012]

According to the present invention, since the correlation threshold value is changed according to the received signal level or the bit error rate of the demodulated digital signal, the correlation does not occur even if the received signal level decreases or the bit error rate increases. By increasing the threshold value, it is possible to facilitate the detection of the synchronization pattern by the synchronization pattern detection means. Further, in the detection of the synchronization pattern, since the reliability of the determination result differs depending on the correlation threshold value that is the reference of the synchronization pattern detection, the number of forward protection steps and the number of backward protection steps are changed according to the correlation threshold value. ..

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the frame synchronization apparatus of the present invention. 1 is an antenna, 2 is an antenna 1
The receiving unit 3 for receiving and processing the received signal from the demodulator is a demodulator for demodulating the digital modulation signal received and processed by the receiving unit 3.

Reference numeral 4 is a level measuring device for measuring the level of the received signal, and outputs a predetermined signal according to the measured received level. This predetermined signal is composed of, for example, a bit pattern of 3 bits, and in this case, the level measuring device 4 can express the intensity of the reception level by dividing it into 8 levels by this output signal.

Reference numeral 5 is a shift register to which the digital signal demodulated by the demodulator 3 is input. Reference numeral 6 is a memory in which a predetermined synchronization pattern of, for example, 32 bits contained in the slot of its own station is stored.

Reference numeral 7 denotes a correlator in which a digital signal having the same number of bits as the synchronization pattern temporarily stored in the shift register 5 is input in parallel for each bit, and the input digital signal and the memory 6 for each bit. The predetermined synchronization patterns input in parallel are compared for each bit, the number of mismatched bits is counted, and the count value is output.

An error rate calculator 8 calculates the bit error rate of the digital signal demodulated by the demodulator, and outputs a predetermined signal according to the calculated bit error rate. This predetermined signal is composed of, for example, a bit pattern of 3 bits, and in this case, the bit error rate measuring device 8 can express the magnitude of the bit error rate in 8 stages by this output signal.

Reference numeral 9 is a delay device which delays the output signal from the error rate calculator 8 by one frame and outputs it.

Reference numeral 10 is a correlation threshold value determiner, which receives a signal indicating the strength of the reception level from the level measuring device 4 and a signal indicating the magnitude of the bit error rate from the delay device 9 and outputs these signals. Determine the correlation threshold according to the input. When making this decision, set the correlation threshold high when the bit error rate is high or the reception level is low, and lower the correlation threshold when the bit error rate is low or the reception level is high. Set.

Reference numeral 11 denotes a mismatch bit number comparator, which receives the number of mismatch bits from the correlator 7 and the correlation threshold value from the correlation threshold value deciding device 10. The unmatched bit number comparator 11 compares the unmatched bit number with the correlation threshold value. As a result, if the unmatched bit number is smaller than the correlation threshold value, a detection signal is output. Output.

Reference numeral 12 is an aperture control section for performing aperture control in response to the detection signal from the comparator 11. The aperture control unit 12 outputs a non-detection signal when a non-detection signal is input from the comparator 11 when synchronization is not established, and outputs a detection signal when the detection signal is input and the aperture control is performed. It becomes a state. In the aperture control state, the aperture control unit 12 provides an aperture of a predetermined time width one frame ahead in which a sync signal is expected to be detected next, and detects that a detection signal is input from the comparator 11 in this aperture. A signal is output, and when only the non-detection signal is input and the detection signal is not input, the non-detection signal is output. Then, when a signal indicating that the synchronization is lost is input in the aperture control state, the aperture control is stopped.

Reference numeral 14 is a holder for holding the value of the correlation threshold value input from the correlation threshold value determiner 10. When the next value is input, the held value is output and also input. Holds a new value.

Reference numeral 15 is a comparator, which receives the correlation threshold value from the correlation threshold value deciding device 10, and its value and the holding device 12.
Compare with the previous correlation threshold input from. As a result, if the previous correlation threshold is greater, that is, the correlation threshold decreases, the comparator 15 outputs the first signal, and if the previous correlation threshold is smaller, That is, when the correlation threshold increases, the second signal is output.

Reference numeral 16 is a front protection stage number determiner that stores a predetermined number of front protection stages and increases or decreases the stored value according to the output signal from the comparator 15. Is input, the number of front protection stages is increased, and when the second signal is input from the comparator 15, the number of front protection stages is decreased.

Reference numeral 17 denotes a rear protection stage number determiner which stores a predetermined number of rear protection stages and increases or decreases the stored value according to the output signal from the comparator 15. Is input, the number of rear protection stages is decreased, and when the second signal is input from the comparator 15, the number of rear protection stages is increased.

Reference numeral 18 denotes a detection counter, which resets the count value when a non-detection signal is input from the aperture controller 12 and increases the count value each time the detection signal is input. That is, this count value is a value indicating how many times the synchronization pattern is continuously detected. Then, when the count value reaches the value of the backward protection stage number input from the backward protection stage number determiner 17, a signal indicating that the synchronization is established is output to the subsequent processing circuit.

Reference numeral 19 denotes a non-detection number counter, which resets the count value when a detection signal is input from the aperture controller 12 and increases the count value each time the non-detection signal is input. That is, this count value is a value indicating how many times the synchronization pattern is not continuously detected. Then, the count value is determined by the front protection stage number determiner 1
When the value of the number of backward protection stages input from 6 is reached, a signal indicating that the synchronization is lost is output to the processing circuit of the subsequent stage.

Next, the operation of this frame synchronizer will be described with reference to FIG.
It will be described according to the flowchart shown in FIG.

First, the operation for establishing synchronization will be described.

When a radio signal is input from the antenna 1 and reception processing is performed by the receiving unit 2 to start communication, the correlation threshold value determining unit 10, the front protection stage number determining unit 16 and the rear protection stage number determining unit 17 respectively correlate. The threshold value, the number of front protection stages and the number of rear protection stages are set to initial values (step 1).

The received signal received by the receiving section 2 is demodulated by the demodulator 3. The demodulated digital signal is sequentially input to the shift register 5 bit by bit and is output in parallel to the correlator 7 bit by bit. In the correlator 7, the parallel bits input from the shift register 5 are transferred to the memory 6
The predetermined synchronization pattern stored in (1) is compared bit by bit, and the number of unmatched bits is output to the unmatched bit number comparator 11 (step 2).

On the other hand, the level of the received signal is measured by the level measuring device 4, and a signal corresponding to the measured level is output to the correlation threshold value deciding device 10 (step 3). The bit error rate calculator 8 calculates the bit error rate of the digital signal demodulated by the demodulator 3, and outputs a signal corresponding to the calculated bit error rate to the delay device 9 (step 4). Correlation threshold value deciding device 10 receives a signal according to the level from level measuring device 4 and a signal according to the bit error rate one frame before from delay device 9 based on these signals. Determine a correlation threshold (step 5). The determined correlation threshold value is input to the mismatch bit number comparator 11, the holder 14, and the comparator 15.

The comparator 15 compares the correlation threshold from the correlation threshold determiner 10 with the previous correlation threshold from the holder 14 (steps 6 and 7).

The comparator 15 outputs the first signal to the front protection stage number determiner 1 when the correlation threshold value is smaller than the previous value.
6 and the rear protection stage number determiner 17, and outputs a second signal when the correlation threshold value exceeds the previous value. When the first signal is input from the comparator 15, the front protection stage number determiner 16 increases the number of front protection stages in accordance with the decrease amount of the correlation threshold (step 8), and the comparator 15 determines the first signal. When the signal No. 2 is input, the number of forward protection stages is decreased according to the increase amount of the correlation threshold value (step 10). When the first signal is input from the comparator 15, the backward protection stage number determiner 17 decreases the backward protection stage number according to the decrease amount of the correlation threshold value (step 9), and the backward protection stage number is determined by the comparator 15. When the signal No. 2 is input, the number of backward protection stages is increased according to the increase amount of the correlation threshold value (step 11).

The unmatched bit number comparator 11 compares the unmatched bit number from the correlator 7 with the correlation threshold value from the correlation threshold value determiner 10 (step 12). As a result, the detection signal is output to the aperture control unit 12 when the number of mismatch bits is less than or equal to the correlation threshold value, and the non-detection signal is output to the aperture control unit 12 when the number of mismatch bits is greater than the correlation threshold value.

At this time, the correlation threshold is the level measuring device 4
The correlation threshold value deciding unit 10 decides from the level of the received signal measured in step 1 and the bit error rate one frame before calculated by the bit error rate calculator 8. This is because when the reception level is low or the bit error rate is high, the correlation threshold is set high, so that the synchronization pattern is easily detected, and the reception level decreases and the bit error rate increases and the synchronization pattern is detected. Prevent it from getting difficult. Further, when the reception level is high or the bit error rate is low, the correlation threshold value is set low so that erroneous detection is prevented.

When the detection signal is input from the comparator 11 when the synchronization is not established, the aperture controller 12 detects the number of detections 18 and the number of non-detections 19.
A detection signal is output to and aperture control is started (step 13). When the detection signal is input, the detection counter 18 increments the count value by one (step 1
4), the count value of the non-detection number counter 19 is reset (step 15).

The detection counter 18 compares the number of backward protection stages from the backward protection stage number determiner 17 with the number of detections (step 16). If the number of detections is smaller than the number of backward protection stages, the process returns to step 2 and the aperture control state is set. The synchronization detection operation of steps 2 to 12 is performed under Then, when the synchronization signal is subsequently detected, the number of detection times of the detection number counter 18 is sequentially incremented, and if the number of detections is equal to or greater than the number of backward protection stages, it is considered that the synchronization is established (step 17) A signal indicating that synchronization is established is output to. Hereinafter, returning to step 2, the synchronization detection operation is repeated under the aperture control state.

At this time, the number of backward protection stages is set by the backward protection stage number determiner 17 according to the variation of the correlation threshold value.
When the correlation threshold is set low, the number of backward protection stages is set low. The low correlation threshold is set when the reception level is high and when the bit error rate is low.The synchronization pattern detected at this time is extremely reliable, so the number of backward protection stages should be set low. Reduce the time required to establish synchronization. Further, when the correlation threshold is set high, there is a high possibility of erroneous detection. Therefore, the number of backward protection stages is set high so that the detection number counter 18 does not erroneously indicate that synchronization has been established. ing.

Next, the operation when the synchronization is lost in the state where the synchronization is established by the above operation will be described.

When the number of unmatched bits from the correlator 7 becomes larger than the correlation threshold value due to a decrease in the reception level or the like,
The non-coincidence bit number comparator 11 outputs a non-detection signal. If the detection signal is not input to the aperture controller 12 in the aperture, the aperture controller 12 outputs a non-detection signal. When a non-detection signal is input to the non-detection number counter 19, the non-detection number, which is a count value, is incremented and the detection number counter 18 is reset (steps 18 and 19).

The non-detection number counter 19 compares the counted number of non-detections with the number of front protection stages from the front protection stage number determiner 16 (step 20). If the number of non-detections is smaller than the number of front protection stages, the process returns to step 2. , Under the aperture control state, the synchronization detection operation of steps 2 to 12 is performed. Then, if the sync signal is not subsequently detected, the count value indicating the non-detection frequency of the non-detection frequency counter 19 is sequentially incremented, and if the non-detection frequency is equal to or more than the number of forward protection steps, it is considered that the synchronization is lost (step 21), a signal indicating that the synchronization has been lost is output to the subsequent processing circuit. This signal is also input to the aperture control unit 12, and the aperture control unit 12 cancels the aperture control state to open the aperture (step 22). Hereinafter, returning to step 2, the synchronization detection operation is repeated under the open aperture.

At this time, the number of front protection stages is set by the front protection stage number determiner 16 according to the variation of the correlation threshold value.
When the correlation threshold is set high, the number of front protection stages is set low. When the correlation threshold value is high, the synchronization pattern is easily detected, but when it is not detected despite this, it is highly possible that the synchronization has been lost, and therefore the number of forward protection stages is reduced.

[0045]

As described above, according to the present invention, with respect to an increase in bit error rate and a decrease in reception level,
It is possible to prevent the establishment of synchronization from becoming difficult and the loss of synchronization from occurring easily.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronizer of the present invention.

FIG. 2 is a flowchart showing an operation of the synchronization device of FIG.

FIG. 3 is a diagram showing a frame structure in time division multiple access digital wireless communication.

[Explanation of symbols]

 2 receiver 3 demodulator 4 level measurer 7 correlator 8 bit error rate calculator 10 correlation threshold determiner 11 mismatch bit number comparator 16 forward protection stage number determiner 17 backward protection stage number determiner 18 detection count counter 19 no Detection counter

Claims (4)

[Claims] 1. A receiving means for receiving a digitally modulated signal, a demodulating means for demodulating the digitally modulated signal into a digital signal, and a bit string of the digital signal demodulated by the demodulating means and a specific synchronization pattern for each bit. Sync pattern detecting means for determining that a sync pattern is detected when the number of mismatch bits obtained as a result of comparison with a predetermined correlation threshold value or less, and level measuring means for measuring the level of the received signal are provided. A synchronization device, wherein the correlation threshold value is set based on a received signal level measured by a measuring means. 2. A receiving means for receiving a digital modulated signal, a demodulating means for demodulating the digital modulated signal into a digital signal, and a bit string of the digital signal demodulated by the demodulating means and a specific synchronization pattern for each bit. A sync pattern detecting means for determining that a sync pattern is detected when the number of unmatched bits obtained as a result of comparison is less than a predetermined correlation threshold; and a bit error rate of the digital signal demodulated by the demodulating means. A synchronizing device comprising: a bit error rate calculating means, wherein the correlation threshold value is set based on at least the bit error rate calculated by the bit error rate calculating means. 3. Receiving means for receiving a digitally modulated signal, demodulating means for demodulating the digitally modulated signal into a digital signal, bit sequence of the digital signal demodulated by the demodulating means and a specific synchronization pattern for each bit. When the number of mismatch bits obtained as a result of the comparison is equal to or less than a predetermined correlation threshold, a synchronization pattern detecting means for determining that a synchronization pattern has been detected, a level measuring means for measuring the level of a received signal, and the demodulating means A bit error rate calculating means for calculating a bit error rate of the demodulated digital signal; a received signal level measured by the level measuring means; and a bit error rate calculated by the bit error rate calculating means. Correlation threshold value determining means for setting a correlation threshold value, and a synchronization device. 4. A detection number counter means for counting how many times a synchronization pattern is continuously detected by the synchronization pattern detection means, and determining that synchronization has been established when the counted number is equal to or greater than the number of backward protection stages. A non-detection number counter unit that counts the number of times that the synchronization pattern is not continuously detected by the synchronization pattern detection unit and determines that the synchronization is lost when the counted number is equal to or greater than the number of forward protection stages is set. And a front protection stage number determining means for determining the front protection stage number based on the correlation threshold value, and a rear protection stage number determining means for determining the rear protection stage number based on the set correlation threshold value. The synchronization device according to claim 1, claim 2, or claim 3.