JPH05315921A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain an output circuit capable of maintaining the potential state of an output terminal at a stable potential even at the time of starting up a power supply. CONSTITUTION:The output circuit includes a level detecting circuit 8 for detecting power supply potential 10, a PMOS transistor(TR) 21 whose gate is connected to the output terminal of the circuit 8 is inserted into the potential side of a power supply terminal in an output buffer driving terminal, a capacitor 4 is inserted between the gate of the PMOS TR 21 and the potential of the terminal 10, and a capacitor 7 is inserted between a driving signal 3 and a ground terminal 9, so that an output buffer 5 is driven and the potential status of an output terminal 6 is determined. Since the PMOS TR 21 is not turned until the power supply arrives at a prescribed level at the time of its rise, the signal 3 is held at a logic 'L' level, and when the power supply arrives at the stable operation voltage of an internal circuit, the signal 3 holds the logic 'L' level since an output signal 1 is a logic 'H' level. Thereby the output terminal 6 is held at the high impedance state even at the start-up of the power supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output circuit that produces a high impedance output when the power supply rises.

[0002]

2. Description of the Related Art A circuit diagram of a conventional output circuit is shown in FIG.
Shows a timing chart for explaining the operation.

According to FIG. 5, a conventional output circuit has drive signals 3 and 15 generated by using an output buffer driving section 2 and an output buffer driving section 12 which are connected to an operating power source of an internal circuit.
Controls the on / off of the output buffer.

The operating state of the conventional output circuit when the power supply voltage rises will be described below with reference to FIGS. 5 and 6.

The conventional output circuit shown in FIG.
Of the output buffer 5 in which the drive signal 3 is input to the gate, the source is connected to the ground terminal 9, and the drain is connected to the output terminal 6. An N-channel type insulated gate field effect transistor (hereinafter referred to as an NMOS transistor) 51 and an output signal 11 are input, and a second output buffer drive unit 12 that generates a drive signal 15 and a drive signal 15 are input to the gate,
Connect the source to the power supply terminal 10 and the drain to the output terminal 6
The output buffer 5 is connected to the P channel type insulated gate field effect transistor (hereinafter referred to as PMOS transistor) 52.

Further, the potential of the power supply terminal 10 rises,
When the stable operation potential of the internal circuit is reached, the output signal 1 becomes the logical value "H" level (hereinafter referred to as "H") and the output signal 1
1 is initially set to a logical value "L" level (hereinafter referred to as "L").

The operation of each part when the voltage is supplied to the power supply terminal 10 and the potential rises will be described below with reference to the timing chart shown in FIG. Output signal 1, drive signal 3, output signal 11 until the potential of power supply terminal 10 rises from the ground potential to the stable internal operation potential
The potential of the drive signal 15 is indefinite (FIG. 6 (a)-
(C)). Therefore, the NMOS transistor 51, PM
The potential of the output terminal 6 connected to the drain of the OS transistor 52 also becomes indefinite (FIG. 6 (d)).

Further, after the potential of the power supply terminal 10 reaches the stable operation potential of the internal circuit, the output signal 1 becomes "H" and the output signal 11 becomes "L", so that the drive signal 3 becomes "L". Next (FIG. 6D), the NMOS transistor 5
1 turns off, the drive signal 15 becomes "H" (FIG. 6 (b)), and the PMOS transistor 52 also turns off. Therefore, the potential state of the output terminal 6 connected to the drains of the NMOS transistor 51 and the PMOS transistor 52 becomes high impedance (FIG. 6 (d)).

[0009]

In this conventional output circuit, the potential state of the output terminal 6 is maintained from the start of power source rise at the time of raising the potential of the power source terminal 10 to the stable operation potential of the internal circuit. It became unstable and indefinite. This has a problem that when a peripheral circuit that operates below the stable operating voltage of the internal circuit is connected to the output terminal 6, the operation of the circuit becomes indefinite.

An object of the present invention is to eliminate the above-mentioned drawbacks and to obtain an output circuit capable of maintaining the potential state of the output terminal at a stable potential even when the power source is rising.

[0011]

A feature of the present invention is that an output buffer driver for receiving an output signal and generating a drive signal for an output buffer, an output end of the output buffer driver and a gate are connected, and a source is provided. And an output buffer formed of an insulated gate field effect transistor for connecting a drain to an output terminal and connecting the drain to the first power terminal or the second power terminal.
A level detection circuit for detecting a predetermined potential of the power supply terminal, and an insulated gate field effect transistor is connected in series between any one of the first or second power supply terminals and the output buffer drive section, The gate of the field effect transistor, the output end of the level detection circuit, and one end of the first capacitor are commonly connected, and the other end is connected to either the first power supply terminal or the second power supply terminal, and the output The output terminal of the buffer driver is connected to one end of the second capacitor, and the other end is connected to either the first power supply terminal or the second power supply terminal.

Each of the first capacitor and the second capacitor can be composed of a resistor.

Another feature of the present invention is to input a first output signal to generate a drive signal for the output buffer, and a second output signal for inputting a second output signal to drive the output buffer. A second output buffer driving unit for generating, an output end of the first output buffer driving unit and an output end of the second output buffer driving unit are respectively connected to gates, and a source is a first power supply terminal. And an output buffer composed of an N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor respectively connected to the second power supply terminal, and the N-channel type insulated gate field effect transistor and P-channel. An output circuit in which the drains of the type insulated gate field effect transistors are commonly connected to the output terminal, wherein a predetermined potential of the second power supply terminal is detected. And a second level detection circuit, and a first insulated gate field effect transistor is provided between either the first power supply terminal or the second power supply terminal and the first output buffer drive section. Connected in series,
The gate of the first insulated gate field effect transistor, the output end of the first level detection circuit, and one end of the first capacitance are commonly connected, and the other end is the first power supply terminal or the second power supply terminal. And connecting the output end of the first output buffer driving section and one end of the second capacitor, and connecting the other end to either the first power supply terminal or the second power supply terminal. Further, a second insulated gate field effect transistor is connected in series between either the first power supply terminal or the second power supply terminal and the second output buffer driving section, and the second insulated gate field effect transistor is connected. The gate of the transistor, the output terminal of the second level detection circuit, and one end of the third capacitor are commonly connected, and the other end is connected to either the first power supply terminal or the second power supply terminal, and Second
The output terminal of the output buffer driving section is connected to one end of the fourth capacitor, and the other end is connected to either the first power supply terminal or the second power supply terminal.

Each of the third capacitor and the fourth capacitor can be composed of a resistor.

[0015]

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit diagram of an output circuit of a first embodiment of the present invention, and FIG. 2 is a timing chart thereof. The MOS transistor of the output buffer, the output buffer driver, and the MOS transistor connected between the first power supply terminal (hereinafter referred to as the ground terminal) or the second power supply terminal (hereinafter simply referred to as the power supply terminal) are respectively Although a P-channel type and an N-channel type can also be used, this embodiment will be described as an N-channel type and a P-channel type, respectively.

In the embodiment shown in FIG. 1, the first output buffer driving section 2 which receives the output signal 1 and generates the driving signal 3 is described.
And the drive signal 3 is input to the gate, the source is connected to the first power supply terminal (hereinafter referred to as the ground terminal) 9, and the drain is connected to the output terminal 6 and the NMOS transistor 51 of the output buffer 5, and the power supply terminal 10 and a level detection circuit 8 for detecting the potential of the level detection circuit 8, and a PMOS transistor in which the output signal of the level detection circuit 8 is input to the gate and the drain is commonly connected to the source of the transistor of the PMOS transistor 21 of the output buffer driver 2 and the power supply terminal 10. 21 and the capacitance 4 inserted between the output terminal of the level detection circuit 8 and the power supply terminal 10.
And a capacitor 7 inserted between the drive signal 3 and the ground terminal 9.

Further, the potential of the power supply terminal 10 rises,
When the stable operation voltage of the internal circuit is reached, the output signal 1 is initialized to "H". In the case of this embodiment,
As shown in FIG. 1, the level detection circuit 8 includes an NMOS transistor 83 in which a gate, a source, and a power supply terminal 10 are commonly connected, and a source is connected to a ground terminal 9 and a gate is an NMOS.
The NMOS transistor 81 connected to the drain of the transistor 83 is used, the drain of the NMOS transistor 81 is used as an output terminal, and the capacitor 82 is inserted between the gate of the NMOS transistor 81 and the ground terminal 9.

The operation of each part when the potential of the power supply terminal 10 rises will be described below with reference to the timing chart shown in FIG.

In the level detection circuit 8, the power supply terminal 10
NM from the ground potential to the threshold voltage of the NMOS transistor 83 (FIG. 2A),
The potential of the node C, which is the drain of the OS transistor 83, is held at the ground potential by the capacitor 82 (FIG. 2C).
Therefore, during this period, the NMOS transistor 81 is turned off, so that the potential of the node B, which is the drain thereof, is held at the potential of the power supply terminal 10 by the capacitor 4 (FIG. 2C). Therefore, the PMOS transistor 21 is also turned off, and the potential of the node A, which is the drain thereof, becomes high impedance (FIG. 2 (d)). On the other hand, the potential of the output signal 1 is indefinite during this period (FIG. 2E), but since the node A has a high impedance, the potential of the drive signal 3 is held at the ground potential by the capacitor 7 (see FIG. 2 ( f)). As a result, the NMOS transistor 5 is turned off and the output terminal 6 becomes high impedance (FIG. 2 (g)).

Further, when the potential of the power supply terminal 10 rises,
The node C rises from the potential of the power supply terminal 10 while maintaining a level lower by the threshold voltage of the NMOS transistor 83 (FIG. 2B). When the potential of the power supply terminal 10 reaches the stable operation voltage of the internal circuit (FIG. 2 (a)), the output signal 1 becomes “H” (FIG. 2 (e)) and the drive signal 3 becomes “L”. Therefore, the NMOS transistor 5 is turned off (FIG. 2 (f)), and the output terminal 6 maintains the high impedance state (FIG. 2 (g)). When the potential of the power supply terminal 10 further rises (FIG. 2A) and the potential of the node C exceeds the threshold voltage of the NMOS transistor 81, the NMOS transistor 81 is turned on and the node B becomes “L” (FIG. 2).
(C)). Therefore, the PMOS transistor 21 is turned on, and the node A becomes "H" (FIG. 2 (d)). However, since the drive signal 1 is "H", the drive signal 3 is kept "L" (FIG. 2 (f)), the NMOS transistor 5 is kept off, and the output terminal 6 is kept in a high impedance state. (FIG. 2 (g)). Therefore, the output terminal 6 maintains the high impedance state from the initial rising of the potential of the power supply terminal 10.

In this embodiment, the capacitors 4 and 7 are used for explanation, but it is obvious that the same operation can be performed by replacing them with resistors. That is, until the node C reaches the threshold voltage of the NMOS transistor 81, the node B is pulled up to “H” by the resistor replaced with the capacitor 4 (FIG. 2C), and the PMOS transistor 2
1 turns off and node A becomes high impedance (Fig. 2
(D)). Therefore, the drive signal 3 is also pulled down by the resistor replaced with the capacitor 7 to be “L” (FIG. 2 (f)),
The NMOS transistor 5 is turned off and the output terminal 6 becomes high impedance (FIG. 2 (g)). The subsequent operation is the same as the case where the capacitors 4 and 7 are used, and the description thereof is omitted.

FIG. 3 is a diagram showing a circuit diagram of an output circuit of the second embodiment of the present invention, and FIG. 4 is a timing chart thereof.

In the embodiment shown in FIG. 3, a first output buffer driving section 2 for inputting a first output signal 1 and generating a driving signal 3 and a driving signal 3 for a gate and a source for a ground terminal. NMO connected to 9 and the drain to output terminal 6
The S-transistor 5, the first level detection circuit 8 that detects the potential of the power supply terminal 10, the output of the first level detection circuit 8 is input to the gate, and the drain is the first output buffer driver 12 of the first output buffer drive unit 12. Of the first MOS transistor (hereinafter simply referred to as “PMOS transistor”) 21 connected to the source of the PMOS transistor and the source connected to the power supply terminal 10, the output terminal of the first level detection circuit 8 and the power supply terminal 10. A second capacitor for inputting the first capacitor 4 inserted between them, the second capacitor 7 inserted between the drive signal 3 and the ground terminal, and the second output signal 11 to generate the second drive signal 15
Of the output buffer driver 12, the drive signal 15 is input to the gate, the source is connected to the power supply terminal 10 and the drain is connected to the output terminal 6, and the potential of the power supply terminal 10 is detected. And a second level detection circuit 14 for inputting the output of the second level detection circuit 14 to the gate, connecting the drain to the source of the NMOS transistor of the second output buffer driving unit 12, and connecting the source to the ground terminal 9. The connected second MOS transistor (hereinafter simply referred to as NMOS transistor) 121, the third capacitor 16 inserted between the output terminal of the second level detection circuit 14 and the ground terminal 9, the drive signal 15, and the power supply. It is composed of a fourth capacitor 13 inserted between the terminal 10 and the terminal 10.

Further, the potential of the power supply terminal 10 rises,
When the stable operation voltage of the internal circuit is reached, the output signal 1 is "H".
In addition, the output signal 11 is initially set to "L". In the case of this embodiment, as shown in FIG. 3, the first level detection circuit 8 has an NMOS transistor 83 whose gate and source are commonly connected to the power supply terminal 10 and a source which is connected to the ground terminal 9.
And an NMOS transistor 81 whose gate is connected to the drain of the NMOS transistor 83.
The drain of the S-transistor 81 is used as the output end, and the NMOS
A capacitor 8 is provided between the gate of the transistor 81 and the ground terminal 9.
2 is inserted. In the second level detection circuit 14, N
Using a MOS transistor 142, the gate and the source are commonly connected to the power supply terminal 10, and the drain is the output terminal.

The operation of each part when the potential of the power supply terminal 10 rises will be described below with reference to the circuit diagram shown in FIG. 3 and the timing chart shown in FIG. First level detection circuit 8, PMOS transistor 21, NMO
The operation of the S transistor 5 is exactly the same as that of the output circuit of the first embodiment, and follows the timing chart of FIG.

In the second level detection circuit 14, the potential of the power supply terminal 10 changes from the ground potential to the NMOS transistor 142.
Until the threshold voltage of
(A)), the potential of the node F, which is the drain of the NMOS transistor 142, is held at the ground potential by the fourth capacitor 16 (FIG. 4 (b)). Therefore, during this period, the NMOS transistor 121 is turned off, and the node E which is its drain becomes high impedance (FIG. 4C). on the other hand,
The potential of the second output signal 11 is indefinite during this period (FIG. 4 (d)), but since the node E has high impedance,
The potential of the driving signal 15 is set to the power supply terminal 1 by the third capacitor 13.
The potential of 0 is held (FIG. 4 (e)). As a result, PM
The OS transistor 17 is turned off and the output terminal 6 becomes high impedance (FIG. 4 (f)).

Further, when the potential of the power supply terminal 10 rises,
The node F rises while maintaining a level lower than the potential of the power supply terminal 10 by the threshold voltage of the NMOS transistor 142 (FIG. 4B). When the potential of the power supply terminal 10 eventually reaches the stable operation voltage of the internal circuit, the output signal 11
Becomes “L” (FIG. 4D), and the drive signal 15 is “H”
Therefore, the PMOS transistor 17 is turned off and the output terminal 6 maintains the high impedance state (FIG. 4 (e)). Further, the potential of the power supply terminal 10 rises, and the potential at the node F becomes the NMOS transistor 121.
When the threshold voltage of is exceeded (Fig. 4 (b)), NM
The OS transistor 121 is turned on, and the node E becomes “L” (FIG. 4C). However, since the output signal 11 is "L" (FIG. 4 (d)), the drive signal 15 maintains "H" (FIG. 4 (e)), the PMOS transistor 15 is kept off, and the output terminal 6 is The high impedance state is maintained (FIG. 4 (f)). Therefore, the output terminal 6 maintains the high impedance state from the initial rising of the potential of the power supply terminal 10.

Also in this embodiment, as in the case of the first embodiment, the first, second, third and fourth capacitors 4, 7, 1 are provided.
Even if the resistors 3 and 16 are replaced with resistors, the same operation can be performed.

[0030]

As described above, in the output circuit of the present invention, the output signal 1 is in an indefinite state until the power supply voltage reaches the stable operation voltage of the internal circuit when the power supply is initially turned on. In the case of the output buffer of the transistor 51, the NMOS transistor 51 is turned off by the capacitor 7 connected to the output terminal of the first output buffer driving unit 2, and the output terminal 6 becomes high impedance. Next, since the capacitance 4 inserted between the gate of the PMOS transistor 21 connected to the power supply terminal 10 side of the first output buffer driving unit 2 and the power supply terminal 10, the PMOS transistor 21 is turned off. The output terminal 6 maintains a high impedance state. When the power supply voltage rises and the NMOS transistor 81 of the level detection circuit 8 turns on, its drain becomes "L" and the PMO
Since the S transistor 21 is turned on and the internal circuit also starts a stable operation, the output signal 1 also becomes "H" and the drive signal 3 also becomes "L", and the high impedance state of the output terminal 6 is maintained.

On the other hand, in the case of the output buffer of the PMOS transistor 52, until the power supply voltage reaches the stable operation voltage of the internal circuit, the NMOS transistor is connected by the capacitor 13 connected to the output terminal of the second output buffer driving section 12. 52 is turned off and the output terminal 6 becomes high impedance. Next, the ground terminal 9 of the second output buffer driving unit 12
Since the NMOS transistor 121 is turned off by the capacitor 16 inserted between the gate of the NMOS transistor 121 connected to the side and the ground terminal 9, the output terminal 6 maintains a high impedance state. As the power supply voltage rises, the drain voltage of the NMOS transistor 142 of the level detection circuit 14 also rises, and the NMOS transistor 121 which receives the potential thereof is turned on.
At the same time, since the internal circuit also starts a stable operation, the output signal 11 becomes "L" and the drive signal 15 also becomes "H", and the output terminal 6 maintains the high impedance state.

Therefore, by stably holding the potential state of the output terminal 6 at the rise of the power supply, the peripheral circuit which operates even at the stable operation voltage of the internal circuit or less is output terminal 6
There is an effect that can be connected to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing an output circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional output circuit.

FIG. 6 is a timing chart for explaining the operation of the conventional output circuit.

[Description of Reference Signs] 1,11 First and second output signals 2 First output buffer driver 21 First insulated gate field effect transistor 12 Second output buffer driver 121 Second insulated gate field effect transistor 4, 7, 13, 16 First, Second, Third, Fourth Capacitance 5 Output buffer 51 N-channel insulated gate field effect transistor of output buffer 52 P-channel insulated gate field effect transistor 6 of output buffer 6 Output terminal 8, 14 First and second level detection circuits 9 First power supply terminal (ground terminal) 10 Second power supply terminal (power supply terminal)

Claims (4)

[Claims] 1. An output buffer driver for receiving an output signal and generating a drive signal for an output buffer, an output terminal and a gate of the output buffer driver are connected to each other, and a source is connected to a first power supply terminal or a second power supply terminal. An output circuit having an output buffer formed of an insulated gate field effect transistor having a drain connected to an output terminal while being connected to any of the power supply terminals, including a level detection circuit for detecting a predetermined potential of the second power supply terminal. An insulated gate field effect transistor is connected in series between any one of the first or second power supply terminals and the output buffer driver, and the gate of the insulated gate field effect transistor, the output end of the level detection circuit, and the 1
One end of the capacitance of is commonly connected and the other end is connected to either the first power supply terminal or the second power supply terminal,
An output circuit, wherein the output end of the output buffer driving unit is connected to one end of a second capacitor, and the other end is connected to either the first power supply terminal or the second power supply terminal. 2. The output circuit according to claim 1, wherein each of the first capacitor and the second capacitor is composed of a resistor. 3. A first output buffer drive section for receiving a first output signal and forming a drive signal for an output buffer, and a second output buffer drive section.
A second output buffer driving section for receiving the output signal from the second output buffer driving section and generating an output buffer driving signal, and an output terminal of the first output buffer driving section and an output terminal of the second output buffer driving section. And an output buffer composed of an N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor whose source is connected to the first power supply terminal and the second power supply terminal, respectively. In an output circuit in which the drains of the N-channel type insulated gate field effect transistor and the P-channel type insulated gate field effect transistor are commonly connected to an output terminal, a first level for detecting a predetermined potential of the second power supply terminal. A first level detection circuit including a detection circuit and a second level detection circuit;
A first insulated gate field effect transistor is connected in series between either the first power supply terminal or the second power supply terminal and the first output buffer driver, and the first insulated gate field effect transistor has a gate and the first insulated gate field effect transistor. An output end of the first level detection circuit is commonly connected to one end of the first capacitance, and the other end is connected to either the first power supply terminal or the second power supply terminal, and the first output buffer is connected. The output end of the drive unit is connected to one end of the second capacitor, and the other end is connected to either the first power supply terminal or the second power supply terminal, and further the first power supply terminal or the second power supply. A second insulated gate field effect transistor is connected in series between any one of the terminals and the second output buffer driving unit, and the gate of the second insulated gate field effect transistor and the output of the second level detection circuit. Edge and number Is commonly connected to one end of the second capacitor and the other end is connected to either the first power supply terminal or the second power supply terminal, and the output end of the second output buffer driving section and one end of the fourth capacitance are connected. And an other end, and the other end is connected to either the first power supply terminal or the second power supply terminal. 4. The output circuit according to claim 3, wherein each of the third capacitor and the fourth capacitor is composed of a resistor.