JPH05304419A - Frequency multiplier - Google Patents

Frequency multiplier

Info

Publication number
JPH05304419A
JPH05304419A JP647392A JP647392A JPH05304419A JP H05304419 A JPH05304419 A JP H05304419A JP 647392 A JP647392 A JP 647392A JP 647392 A JP647392 A JP 647392A JP H05304419 A JPH05304419 A JP H05304419A
Authority
JP
Japan
Prior art keywords
capacitor
line
matching circuit
frequency multiplier
fundamental wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP647392A
Other languages
Japanese (ja)
Inventor
Shuichi Kokubu
秀一 国分
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP647392A priority Critical patent/JPH05304419A/en
Publication of JPH05304419A publication Critical patent/JPH05304419A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the suppression characteristic of a basic wave output by using a 1/4 wavelength coupling line as a capacitor for DC blocking of an output matching circuit. CONSTITUTION:This frequency multiplier is formed by an input matching circuit 1, an FET 2 as a frequency multiplying means, an output matching circuit 3, and a bonding wire 4 connecting the FET 2 and the circuits 1, 3. The basic wave from the FET 2 is shorted by an open stab 10, but the sufficient suppression is not enabled. However, since the gap capacitor 11 has the line of lambda/4 length, the basic wave is shorted in a gap capacitor 1. Since a double wave is strong in a coupling degree, it is outputted through the opposing line of lambda/4 length from the line of lambda/4 length within the capacitor 11. Therefore, even if the basic wave is not sufficiently suppressed, it is suppressed by the gap capacitor 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は周波数逓倍器に関し、特
に基本波の抑圧を改善した周波数逓倍器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier, and more particularly to a frequency multiplier with improved suppression of the fundamental wave.

【0002】[0002]

【従来の技術】従来の逓倍器では、基本波(波長λ)で
短絡状態、2倍波で開放状態となる長さλ/4のオープ
ンスタブを出力整合回路として用いることにより基本波
を抑圧している。また、この出力整合回路の直流阻止用
コンデンサとして単板コンデンサが使用されている。
2. Description of the Related Art In a conventional multiplier, a fundamental wave is suppressed by using an open stub having a length λ / 4, which is short-circuited at the fundamental wave (wavelength λ) and opened at the second harmonic as an output matching circuit. ing. A single plate capacitor is used as a DC blocking capacitor of this output matching circuit.

【0003】[0003]

【発明が解決しようとする課題】このような従来の逓倍
器では入力基本波成分が出力されないよう出力整合回路
に基本波のλ/4長のオープンスタブと単板コンデンサ
とから入力基本波成分を抑圧しているが、充分抑圧する
ことができなかった。
In such a conventional multiplier, the input fundamental wave component is provided to the output matching circuit from the λ / 4 length open stub of the fundamental wave and the single plate capacitor so that the input fundamental wave component is not output. I'm suppressing, but I couldn't suppress it enough.

【0004】[0004]

【課題を解決するための手段】本発明の周波数逓倍器
は、基本波信号を入力して2倍波信号を出力する逓倍手
段と、前記逓倍手段の入力側に設けられた薄膜誘電体基
板上のストリップラインによる入力整合手段と、前記逓
倍手段の出力側に設けられた出力整合手段とからなる周
波数逓倍器において、前記出力整合手段が、基本波に対
して1/4波長のオープンスタブと、直流阻止用コンデ
ンサとしてのλ/4波長結合線路とを備えている。
A frequency multiplier according to the present invention comprises a multiplication means for inputting a fundamental wave signal and outputting a second harmonic wave signal, and a thin film dielectric substrate provided on the input side of the multiplication means. In the frequency multiplier comprising the strip line input matching means and the output matching means provided on the output side of the multiplying means, the output matching means is an open stub having a quarter wavelength with respect to the fundamental wave. It has a λ / 4 wavelength coupling line as a DC blocking capacitor.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の周波数逓倍器の平面図で
ある。同図において周波数逓倍器は、入力整合回路1,
周波数逓倍手段としての電界効果トランジスタ(FE
T)2,出力整合回路3,FET2と入力整合回路1あ
るいは出力整合回路3とを接続するボンディングワイヤ
4で構成されている。
The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a frequency multiplier according to an embodiment of the present invention. In the figure, the frequency multiplier is an input matching circuit 1,
A field effect transistor (FE) as a frequency multiplication means.
T) 2, output matching circuit 3, FET 2 and input matching circuit 1 or output matching circuit 3 are formed by bonding wires 4.

【0006】入力整合回路1は、薄膜誘電体基板5上に
ストリップライン6と直流阻止用コンデンサとしての単
板コンデンサ7とを備えており、入力基本周波数に対し
て整合をとる。出力整合回路3は、薄膜誘電体基板8上
にストリップライン9,基本波のλ/4長のオープンス
タブ10および直流阻止用コンデンサとしてのλ/4長
の線路をもつギャップコンデンサ11を備えており、2
倍波周波数に対して整合をとり、入力基本波を抑圧す
る。オープンスタブ10およびギャップコンデンサ11
の一対の線路は基本波のλ/4の長さLを有している。
The input matching circuit 1 is provided with a strip line 6 and a single plate capacitor 7 as a DC blocking capacitor on a thin film dielectric substrate 5 to match the input fundamental frequency. The output matching circuit 3 includes a stripline 9, a λ / 4 open stub 10 of a fundamental wave, and a gap capacitor 11 having a λ / 4 long line as a DC blocking capacitor on a thin film dielectric substrate 8. Two
Matches to the harmonic frequency and suppresses the input fundamental wave. Open stub 10 and gap capacitor 11
Has a length L of λ / 4 of the fundamental wave.

【0007】FET2からの基本波はオープンスタブ1
0でショートされるが、充分な抑圧ができない。しか
し、キャップコンデンサ11がλ/4長の線路を有して
いるため基本波はギャップコンデンサ11でショートさ
れる。一方、2倍波は結合度が強いため、ギャップコン
デンサ11内のλ/4長の線路から対向するλ/4長の
線路を通り出力される。
The fundamental wave from the FET 2 is an open stub 1.
It is shorted with 0, but cannot be suppressed sufficiently. However, since the cap capacitor 11 has a line of λ / 4 length, the fundamental wave is short-circuited by the gap capacitor 11. On the other hand, since the second harmonic wave has a high degree of coupling, it is output from the λ / 4 length line in the gap capacitor 11 through the opposing λ / 4 length line.

【0008】図2は図1に示した本発明の一実施例(ギ
ャップコンデンサ使用)と、従来技術(単板コンデンサ
使用)との通過周波数特性を示す図である。同図より出
力整合回路3の直流阻止用コンデンサとして従来のよう
に単板コンデンサを用いた時より本発明のようにギャッ
プコンデンサを用いた時の方が抑圧特性が改善されるこ
とがわかる。例えば、基本周波数を9GHzとすると、
単板コンデンサの時は−0.8dBであるが、ギャップ
コンデンサの時は−4.0dBとなる。
FIG. 2 is a diagram showing pass frequency characteristics of one embodiment of the present invention (using a gap capacitor) shown in FIG. 1 and a conventional technique (using a single plate capacitor). From the figure, it can be seen that the suppression characteristic is improved when the gap capacitor is used as in the present invention as compared with the case where the single plate capacitor is used as the DC blocking capacitor of the output matching circuit 3 as in the prior art. For example, if the fundamental frequency is 9 GHz,
It is −0.8 dB for a single plate capacitor, but −4.0 dB for a gap capacitor.

【0009】したがって、オープンスタブで基本波が充
分抑圧されなくても、ギャップコンデンサで抑圧され
る。
Therefore, even if the fundamental wave is not sufficiently suppressed by the open stub, it is suppressed by the gap capacitor.

【0010】なお、本発明の実施例において出力整合回
路の直流阻止用コンデンサとしてギャップコンデンサを
用いた場合について説明したが、本発明はギャップコン
デンサでなくともλ/4波長結合線路であれば良い。
In the embodiment of the present invention, the case where the gap capacitor is used as the DC blocking capacitor of the output matching circuit has been described, but the present invention is not limited to the gap capacitor and may be a λ / 4 wavelength coupled line.

【0011】[0011]

【発明の効果】以上説明したように本発明は、出力整合
回路の直流阻止用コンデンサとしてλ/4波長結合線路
を用いたので、基本波を充分抑圧できる。またオープン
スタブの位置がずれてもあるいはFETの特性にばらつ
きがあっても基本波の抑圧特性を改善することができる
という効果を有する。
As described above, according to the present invention, since the λ / 4 wavelength coupling line is used as the DC blocking capacitor of the output matching circuit, the fundamental wave can be sufficiently suppressed. Further, even if the position of the open stub is displaced or the characteristics of the FET are varied, the suppression characteristic of the fundamental wave can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の平面図FIG. 1 is a plan view of an embodiment of the present invention.

【図2】ギャップコンデンサの通過周波数特性を示す
図。
FIG. 2 is a diagram showing a pass frequency characteristic of a gap capacitor.

【符号の説明】[Explanation of symbols]

1 入力整合回路 2 FET 3 出力整合回路 4 ボンディングワイヤ 5,8 薄膜誘電体基板 6,9 ストリップライン 7 単板コンデンサ 10 オープンスタブ 11 ギャップコンデンサ 1 Input Matching Circuit 2 FET 3 Output Matching Circuit 4 Bonding Wire 5,8 Thin Film Dielectric Substrate 6,9 Stripline 7 Single Plate Capacitor 10 Open Stub 11 Gap Capacitor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基本波信号を入力して2倍波信号を出力
する逓倍手段と、前記逓倍手段の入力側に設けられた薄
膜誘電体基板上のストリップラインによる入力整合手段
と、前記逓倍手段の出力側に設けられた出力整合手段と
からなる周波数逓倍器において、 前記出力整合手段が、基本波に対して1/4波長のオー
プンスタブと、直流阻止用コンデンサとしてのλ/4波
長結合線路とを有することを特徴とする周波数逓倍器。
1. A multiplication means for inputting a fundamental wave signal and outputting a second-harmonic signal, input matching means by a strip line on a thin film dielectric substrate provided on the input side of said multiplication means, and said multiplication means. A frequency multiplier comprising output matching means provided on the output side of the output matching means, wherein the output matching means is an open stub having a quarter wavelength with respect to the fundamental wave and a λ / 4 wavelength coupling line as a DC blocking capacitor. And a frequency multiplier having:
【請求項2】 前記λ/4波長整合線路がギャップコン
デンサであることを特徴とする請求項1記載の周波数逓
倍器。
2. The frequency multiplier according to claim 1, wherein the λ / 4 wavelength matching line is a gap capacitor.
JP647392A 1992-01-17 1992-01-17 Frequency multiplier Pending JPH05304419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP647392A JPH05304419A (en) 1992-01-17 1992-01-17 Frequency multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP647392A JPH05304419A (en) 1992-01-17 1992-01-17 Frequency multiplier

Publications (1)

Publication Number Publication Date
JPH05304419A true JPH05304419A (en) 1993-11-16

Family

ID=11639433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP647392A Pending JPH05304419A (en) 1992-01-17 1992-01-17 Frequency multiplier

Country Status (1)

Country Link
JP (1) JPH05304419A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6041224A (en) * 1996-04-26 2000-03-21 Sharp Kabushiki Kaisha DBS tuner for satellite broadcasting receivers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6041224A (en) * 1996-04-26 2000-03-21 Sharp Kabushiki Kaisha DBS tuner for satellite broadcasting receivers

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