JPH05267317A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To operate an element at high speed by a method wherein a first diffusion region and a second diffusion region are formed in prescribed widths and in prescribed regions. CONSTITUTION:The title semiconductor device is provided with the following: a first conductive region 34 which is formed so as to protrude selectively to a low-doped collector layer 22 from the upper part of a high-doped collector layer 21 so as to correspond to the position of an emitter layer 26 and which is composed of a high-doped layer of one conductivity type; and a second conductive region 31 which is formed near the junction part of an internal base layer 24 to the low-doped collector layer 22 and which is composed of a high-doped layer of one conductivity type. The thickness of the low-doped collector layer 22 is formed to be thick near a part directly under an outer base diffusion layer 25 and to be thin in a part directly under the internal base diffusion layer 24. When the thickness of the low-doped collector layer 22 is made thin only in a region near the part directly under the internal base diffusion layer 24 in this manner, a parasitic capacity is not increased so much, and a collector parasitic resistance can be reduced. Thereby, an element can be operated at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device which is a self-aligned bipolar transistor and can operate at high speed, and a method for manufacturing the same. In the advanced information processing society in recent years, it has been required to process a huge amount of information quickly, and thus a high processing speed is required. Therefore, in order to increase the processing speed of, for example, a computer or the like, it is desired to increase the speed of an integrated circuit element, which is a basic component thereof, especially a bipolar transistor.

However, in increasing the speed of a bipolar transistor, for example, the parasitic capacitance and parasitic resistance inside the element are reduced, or the base pushing effect (Kirk effect) is applied.
Although various improvements have been made in order to suppress such problems, they have not been sufficient. Therefore, there is a demand for a bipolar transistor capable of achieving higher speed.

[0003]

2. Description of the Related Art FIG. 7 is a sectional view showing the structure of a conventional self-aligned bipolar transistor, and FIG. 8 is a sectional view showing the structure of another conventional self-aligned bipolar transistor. In these figures, 1 is an n-type high-concentration collector burying layer (n ⁺ ) and 2 is an n-type low-concentration collector burying layer (n ⁻ ). Connected to. Three
Is a field oxide film formed by the LOCOS method for element isolation, 4 is a high-concentration p-type internal base diffusion layer (p) formed in the upper center of the low-concentration collector layer 2, and 5 is an internal base diffusion layer. A high-concentration p-type external base diffusion layer (p) 6 provided on both sides of the low-concentration collector layer 2 on both sides of the layer 4 is a high-concentration n-type diffusion layer formed near the center of the upper part of the internal base diffusion layer 4. It is an emitter diffusion layer (n). Reference numeral 7 denotes an external base lead electrode made of polysilicon or the like, which is formed on the external base diffusion layer 5 and doped with conductive p-type impurities (for example, B), and 8 is formed on the external base lead electrode 7. An insulating film made of SiO ₂ or the like, 9 is an external base lead electrode 7 and an insulating film 8
Sidewalls 10 formed on the sidewalls of the electrodes are emitter extraction electrodes made of polysilicon or the like doped with an n-type impurity (for example, As) that is buried so as to be in contact with the high-concentration emitter diffusion layer 6, and 11 is an electrode. A high-concentration diffusion region (n) of n-type having a so-called pedestal structure, which is formed between the internal base diffusion layer 4 under the high-concentration emitter diffusion layer 6 and the low-concentration collector layer 2. 12 is the base
The emitter opening 13 is an emitter opening.

Further, w ₁ is the base / emitter opening 12
, W ₂ is the width of the emitter opening 13 not covered by the sidewall 9 with the base-emitter opening 12, and w ₃ is the base width between the emitter and collector. First, as shown in FIG. 7, the conventional bipolar transistor was operated in a high current region to increase the speed. However, in the base portion of the element operating in this high current region, the so-called base pushing effect (Kirk effect) in which the p region of the base is enlarged occurs, and the base width w ₃ is substantially increased, resulting in the operation. There was a slowdown. This is because the operating speed of the bipolar transistor is inversely proportional to the square of the base width w ₃ .

Therefore, as shown in FIG. 8, recently, by adopting a pedestal structure in which an n-type high-concentration diffusion region 11 is formed immediately below the internal base diffusion layer 4, a base which occurs during operation in a high current region is adopted. It has been attempted to suppress the push-out effect and increase the speed. This is because in the high current region, the p region of the base of the bipolar transistor tries to expand due to the seepage of holes.
This is because the n-type high-concentration diffusion region 11 is arranged immediately below the base, and this prevents the p region from expanding.

[0006]

As described above, in the conventional bipolar transistor, the n-type high-concentration diffusion region 11 is arranged immediately below the base, so that the push-out effect of the base, which is a factor inhibiting high-speed operation, is suppressed. However, the speed was increased. In addition to the above, as a means for preventing the base extrusion effect, for example, the low concentration collector layer 2 shown in FIG.
It is conceivable that the high-concentration collector burying layer 1 is arranged immediately below the base by forming a thin layer. However, when such a structure is adopted, the depletion layer that has spread in the low-concentration collector layer 2 during device operation is changed to the external base diffusion layer 5
Also, since the high-concentration collector buried layer 1 is arranged immediately below the internal base diffusion layer 4, it becomes difficult to spread, and there arises a problem that a kind of capacitor is formed in that portion and the parasitic capacitance increases. This increase in the parasitic capacitance causes the charge to be accumulated in the element, so that the switching is ON or OF.
It takes time to reach F, which is a factor that hinders the speeding up of device operation.

In this respect, the bipolar transistor shown in FIG. 8 has an np immediately below the high-concentration emitter diffusion layer 6 as shown in the figure.
Since the high-concentration diffusion region 11 is formed only in the operation region of the bipolar transistor constituted by n, the spread effect of the base is suppressed and the parasitic capacitance is suppressed to the minimum. On the other hand, as another factor that impedes speeding up other than the above, there is a parasitic resistance in the element. This parasitic resistance is the resistance of the current flowing in the operating region of the element,
The smaller the resistance, the faster the device operation. If this is seen in FIG. 8, the collector parasitic resistance in the low-concentration collector layer 2 immediately below the high-concentration emitter diffusion layer 6 can be considered.

In the case of FIG. 7, the low-concentration collector layer 2 is epitaxially grown thick in order to reduce the parasitic capacitance as much as possible for the above reason, and the collector resistance increases accordingly and the operating speed slows down. was there. Further, in the case of FIG. 8, the high concentration diffusion region 11 is n
Since the resistance is lowered to some extent because it is in the pn operation region, the low-concentration collector layer 2 has almost the same thickness, and there is a problem that the collector resistance reduction effect is small and the operation speed becomes slow.

Therefore, the present invention has been made in view of such a conventional problem, and it is possible to reduce the base pushing effect, the parasitic capacitance, and the parasitic resistance, which are the factors inhibiting the speedup of the bipolar transistor, as much as possible. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can achieve high speed.

[0010]

In order to achieve the above-mentioned object, a semiconductor device according to a first aspect of the present invention has one conductivity type high-concentration collector layer below an element formation region and one conductivity type low concentration collector layer thereon. A concentration collector layer is provided, an internal base layer of a reverse conductivity type is selectively provided on the upper part of the low concentration collector layer, and an external base layer of a reverse conductivity type is provided on both sides of the internal base layer. In a semiconductor device comprising a bipolar transistor having a one-conductivity-type emitter layer provided on the upper part of the internal base layer, selectively protruding from the upper part of the high-concentration collector layer to the lower-concentration collector layer in correspondence with the position of the emitter layer. A first conductive region formed of a one-conductivity-type high-concentration layer and a second conductivity-type high-concentration layer provided near a junction between the internal base layer and the low-concentration collector layer. Characterized in that and a conductive region.

A semiconductor device according to a second aspect of the invention is
To achieve the above object, the width of the first conductive region is substantially equal to the width of the internal base layer, and the width of the second conductive region is substantially equal to the width of the emitter layer. And In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to a third aspect of the present invention comprises a high-concentration collector layer of one conductivity type, a low-concentration collector layer of one conductivity type, a base lead electrode of a reverse conductivity type, and an insulating layer. After sequentially stacking, a step of selectively removing the base lead electrode and the insulating layer corresponding to a region where the internal base layer is to be formed to form a first opening, and using the base lead electrode as a mask, one conductive layer is formed. -Type impurity ions are ion-implanted in a predetermined range from the high-concentration collector layer to the low-concentration collector layer to form a high-concentration first conductive region, and exposed to the first opening. Forming an internal base layer of opposite conductivity type on the surface of the low concentration collector layer, and then forming sidewalls selectively on both side walls of the first opening to form the first opening. Than After the second opening is formed, the second opening is formed near the junction between the internal base layer and the low concentration collector layer with impurity ions of one conductivity type using the base extraction electrode and the sidewall as a mask. High concentration second ion implantation through the
The method is characterized by including a step of forming a conductive region and a step of forming an emitter layer of one conductivity type on the surface portion of the internal base layer exposed in the second opening.

[0012]

According to the present invention, as shown in FIG. 1, the second diffusion region 3 corresponding to the conventional high-concentration diffusion region 11 shown in FIG.
In addition to 1, the first diffusion region 34, which is another high-concentration diffusion region, is selectively provided. As a result, the low-concentration collector layer 22 is formed to have a large thickness immediately below the external base diffusion layer 25 and a thin thickness immediately below the internal base diffusion layer 24. As described above, increasing the thickness of the low-concentration collector layer 22 over the entire area increases the parasitic capacitance. However, as in the present application, the thickness of the low-concentration collector layer 22 can be reduced only in the region immediately below the internal base diffusion layer 24. In this case, the parasitic capacitance does not increase so much, and the collector parasitic resistance can be reduced. As a result, a bipolar transistor that operates at a higher speed can be obtained.

Further, the second diffusion region 31 suppresses the base pushing out effect during the operation of the bipolar transistor in the high current region as described above, and in the present invention, the width thereof is the same as that of the high concentration emitter diffusion layer 26 of npn. Since it is kept in the operating region, the parasitic capacitance between the base and the collector can be minimized. Moreover, the first diffusion region 34 is
In accordance with a current path that is provided in the low concentration collector layer 22 and radiates downward from the high concentration emitter diffusion layer 26,
The n-type high-concentration diffusion region is formed below the external base diffusion layer 25, which has the same width w ₁ as the internal base diffusion layer 24 and has a deeper diffusion depth than the internal base diffusion layer 24 and is apt to have large parasitic capacitance. Since it is not formed, the effect of reducing the parasitic resistance in the collector and the effect of not increasing the extra parasitic capacitance can be maximized.

Furthermore, since the first diffusion region 34 and the second diffusion region 31 are formed by ion implantation using the base extraction electrode, the base extraction electrode and the side wall as a mask respectively, most of the conventional self-alignment process is performed. No need to change.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 is a cross-sectional view showing a configuration of a self-aligned bipolar transistor according to an embodiment of the present invention, FIGS. 2 and 3 are views for explaining a manufacturing process of the bipolar transistor of FIG. 1, and FIG. 5 and 6 are sectional views showing the structure of a comparative example for comparison with the bipolar transistor of this embodiment.

In these figures, 21 is an n-type high-concentration collector burying layer (n ⁺ ) and 22 is an n-type low-concentration collector burying layer (n ⁻ ).
It is connected via 1 to a collector electrode (not shown). 23
Is a field oxide film formed by a LOCOS method for element isolation, 24 is a high-concentration p-type internal base diffusion layer (p) formed in the upper center of the low-concentration collector layer 22, and 25 is an internal base diffusion. A high-concentration p-type external base diffusion layer (p) 26 provided on both sides of the low-concentration collector layer 22 on both sides of the layer 24 is a high-concentration n-type diffusion layer formed near the center of the upper part of the internal base diffusion layer 24. It is an emitter diffusion layer (n). Reference numeral 27 denotes an external base lead electrode made of p-type polysilicon doped with an impurity such as boron (B) having conductivity on the external base diffusion layer 25, and 28 is formed on the external base lead electrode 27. An insulating layer made of SiO ₂ or the like, 29 is a sidewall insulating layer formed on the sidewall of the base / emitter opening 32 obtained by etching the external base lead electrode 27 and the insulating layer 28, and 30 is in contact with the high-concentration emitter diffusion layer 26. Is an emitter extraction electrode made of n-type polysilicon doped with an impurity such as As buried in.
Reference numeral 31 is formed between the internal base diffusion layer 24 and the low-concentration collector layer 22 below the high-concentration emitter diffusion layer 26 by ion implantation while controlling impurity ions such as P.
This is the second diffusion region (n) of high density n-type having a pedestal structure. 32 is a base / emitter opening, 33 is an emitter opening, w ₁ is the width of the base / emitter opening 32, and w ₂ is the width of the emitter opening 33 not covered with the sidewall insulating layer 29. A first diffusion region 34 is formed by implanting ions from the base / emitter opening 32 while controlling impurity ions such as P in a range from above the high concentration collector buried layer 21 to approximately the center of the low concentration collector layer 22. Is.

Next, a method of manufacturing the bipolar transistor of this embodiment will be described. First, as shown in FIG. 2A, a high-concentration collector burying layer 21 made of an n ⁺ type silicon layer is formed on a silicon substrate (not shown) by thermal diffusion or the like, and silicon is formed on the high-concentration collector burying layer 21. Is epitaxially grown to form an n ⁻ -type low-concentration collector layer 22, and then the low-concentration collector layer 22 made of silicon is selectively thermally oxidized by a LOCOS method or the like to form a field oxide film 23 having a thickness of about 6000 Å. To do.

Next, as shown in FIG. 2B, the conductivity of the surface of the low-concentration collector layer 22 and the field oxide film 23 in which impurity ions such as boron (B) to be the base extraction electrode 27 are introduced in advance. The doped polysilicon having the property is deposited by the CVD method at about 3000 Å.
Then, an insulating layer 28 of SiO ₂ is formed thereon by the CVD method.
Is deposited to about 3000 Å, a photoresist is applied, and a photolithography technique is used to form a resist mask in which the central portion of the element formation region is removed by about 0.6 μm in width.
Using the resist mask, anisotropic etching is performed by RIE or the like to form the base / emitter opening 32. Then, using the base / emitter opening 32, n-type impurity ions such as P are implanted in the range from the upper portion of the high concentration collector buried layer 21 to the half of the low concentration collector layer 22 having the above average range. The acceleration energy is controlled as described above (for example, 400 kev to 3 Me
V), and the dose amount at that time is such that the concentration gradually decreases as it goes upward from the high-concentration collector burying layer 21, or the impurity concentration increases gradually from the surface of the high-concentration collector burying layer 21. 1 × 10 ²¹ to 1 × 10 ¹⁷ c so as to gradually decrease after increasing and reaching the maximum value
Ion implantation is performed in the range of m ^-3 . As a result, the ion implantation region 34b to be the first diffusion region 34 is formed. Next, in order to form the internal base diffusion layer 24, impurity ions such as B are implanted at 10 keV and 3.0 × 10 ¹³ cm ^-2 using the base / emitter opening 32 as described above.
Ion implantation is performed to a shallow extent to form an ion implantation region 24a.

Next, as shown in FIG. 3C, the insulating layer 2
8 and so as to cover the surface of the base-emitter opening 32, after the SiO ₂ was about 2000Å by CVD, on the side wall portion of the inner base-emitter opening 32 by anisotropic etching such as RIE The sidewall insulating layer 29 is formed. Here, since the width of one sidewall insulating layer 29 is set to about 0.2 μm, the emitter opening 33 of about 0.2 μm is formed. Then, using the emitter opening 33, n-type impurity ions such as P and As are formed near the junction between the internal base diffusion layer 24 and the low-concentration collector layer 22 whose average range is formed in a later step. controlling the acceleration energy so that (for example a P ⁺ 3
Ion implantation is performed at a dose of 4 × 10 ¹² cm ⁻² at 00 keV or 650 keV of As ⁺ ). As a result, the ion implantation region 31b to be the second diffusion region 31 is formed.
Is formed.

Next, as shown in FIG. 3D, the emitter opening 33 and the sidewall insulating layer 29 are covered.
A 100-layer polysilicon layer, for example, is formed on the surface by the CVD method.
After depositing about 0Å, As ion implantation (As ⁺ 40
Kev, 1 × 10 ¹⁶ cm ⁻² ). Then, etching is performed using the resist mask formed by the photolithography process, the polysilicon layer is removed except for the base / emitter opening 32, and the emitter extraction electrode 30 is formed.

After that, heat treatment (1100 ° C., 5
Second), the external base lead electrode 27
B introduced into the inside and As introduced into the emitter extraction electrode 30 are thermally diffused and activated in the low concentration collector layer 22, respectively, and an external base diffusion layer 25 and a high concentration emitter diffusion layer 26 are formed. At the same time, the ion-implanted regions 24a, 31b and 34b, which have been ion-implanted in advance, are activated to form the internal base diffusion layer 24, the high concentration emitter diffusion layer 26, the second diffusion region 31 and the first diffusion region 34. The semiconductor device as shown in FIG. 1 can be formed by self-alignment.

The half of the present embodiment formed in this way
In the conductor device, the second diffusion region 31 shown in FIG.
Pushing the base during operation of the transistor in the high current region
While suppressing the protrusion effect, the width of the second diffusion region 31 is reduced.
Since it is the same as the high concentration emitter diffusion layer 26,
Parasitic capacitance between collectors can be minimized
It was Further, the first diffusion region 34 is filled with a high concentration collector.
From the upper part of the buried layer 21 to the middle of the low concentration collector layer 22
The high concentration emitter diffusion layer 26
Internal base to match the current path that radiates downward from
Width w of diffusion layer 24 ₁Since it is the same as
In addition to further reducing the raw resistance, the internal base diffusion layer 2
Below the external base diffusion layer 25 with a diffusion depth greater than 4
Since an n-type high-concentration diffusion region is not formed, extra parasitic capacitance
Aim to increase the speed by not increasing the amount.
You can In addition, the concentration of the first diffusion region 34 of the present embodiment
The distribution goes from the high concentration collector buried layer 21 to the upper side.
Therefore, it may be temporarily reduced or the high concentration collector buried layer
21 The impurity concentration increases from the surface to the
I configured it to gradually decrease after reaching a high price
Therefore, the resistance is reduced and the parasitic capacitance under the internal base diffusion layer 24 is reduced.
It is intended to further increase the speed by suppressing the generation of quantity.

Next, the characteristics of the semiconductor device of this embodiment are shown in FIG.
~ It demonstrates in comparison with the block diagram of the comparative example shown in FIG. The inventors of the present invention change the manufacturing process sequence when forming the first diffusion region 34 and the second diffusion region 31 by ion implantation, as shown in FIG.
6 is a prototype of a bipolar transistor having the structure shown in FIG.

First, the semiconductor device shown in FIG. 4 is a bipolar transistor having only the second diffusion region 31a having a pedestal structure. The second diffusion region 31a is formed by using the base / emitter opening 32 to form the sidewall insulating layer 2
Ion implantation was performed before forming No. 9 (note that the impurity ions and the dose amount thereof described in FIGS. 4 to 6 are the same as those in the above embodiment). Therefore, the second diffusion region 31a is formed to have the same width as the internal base diffusion layer 24, unlike the second diffusion region 31 of the above embodiment.

When the bipolar transistor of FIG. 4 is used for operation, the base diffusion effect is prevented by the second diffusion region 31a, and the n-type high-concentration region is present in the npn operating region. There is some effect of reducing parasitic resistance. However, in the bipolar transistor of FIG. 4, as compared with the case of FIG. 1, parasitic capacitance is generated in the lower portion of the internal base diffusion layer 24 other than the operation region, the operation speed is reduced, and the first diffusion region 34 is not provided. It can be seen that the collector resistance is high and the speed cannot be increased.

Next, in the semiconductor device shown in FIG. 5, the second diffusion region 31 of the pedestal structure is not provided, but the first diffusion region 3 is used.
Only 4a is formed. This first diffusion region 3
4a is different from the case of the above-described embodiment in that ion implantation is performed using the emitter opening 33 after forming the sidewall insulating layer 29. Therefore, the first diffusion region 3
Unlike the first diffusion region 34 of the above-described embodiment, 4a is formed to have the same width as the high concentration emitter diffusion layer 26.

When the bipolar transistor of FIG. 5 is used for operation, the parasitic capacitance between the base and the collector is small, and the first diffusion region 34a has an effect of reducing the collector resistance to some extent. However, in the bipolar transistor of FIG. 5, since the current from the emitter flows radially to the collector side, the effect of reducing the collector resistance is small compared to the case of the present embodiment only with the width of the second diffusion region 31a, and moreover, Since the second diffusion region 31 is not formed, it can be seen that the base extrusion effect occurs and the speed cannot be increased.

Next, in the semiconductor device shown in FIG. 6, the second diffusion region 31 of the pedestal structure is not provided and the first diffusion region 3 is formed.
Only 4 was formed. This first diffusion region 34
In the same manner as in the above-mentioned embodiment, ion implantation is performed using the base / emitter opening 32 before forming the sidewall insulating layer 29. When the bipolar transistor of FIG. 6 is used for operation, the parasitic capacitance between the base and the collector is small as in the case of FIG. 5, and the first diffusion region 3 is used.
4, a significant reduction effect of the collector resistance can be obtained (the width is w _{1 in} terms of parasitic resistance, which is different from the case of FIG. 5). In terms of parasitic capacitance, the effect of reducing parasitic capacitance is large because the diffusion depth is not formed in the external base diffusion region, which is deeper than the internal base diffusion region. what if,
When the first diffusion region 34 is formed so as to extend right under the external base diffusion layer 25, the thickness of the low-concentration collector layer 22 directly under the external base diffusion layer 25 becomes particularly thin, so that the parasitic capacitance is particularly large in this portion. turn into. But,
In the case of FIG. 6, since the second diffusion region 31 is not formed, the base extrusion effect occurs, and it is understood that the speed cannot be increased.

As described above, the present inventors study in detail the structure relating to the positions and the widths of the first diffusion region 34 and the second diffusion region 31 from the viewpoint of the base pushing effect, the parasitic resistance and the parasitic capacitance. At the same time, as a result of considering the manufacturing process, the structure and manufacturing method described in the above-mentioned embodiment have been adopted. In the bipolar transistor of the above embodiment, the n-type region and the p-type region may be reversed and the same effect as described above can be obtained.

Further, in the self-aligned bipolar transistor having the same structure as that of the above-described embodiment, as a process other than the above, for example, an SST (Super) is formed by over-etching the external base region with a Si ₃ N ₄ film.
Self-aligned process techn
transistor, or external base region is formed by a sidewall electrode.
It goes without saying that it can be applied to the transistor described in Japanese Patent Publication No. 183538.

[0031]

As described above, according to the present invention,
In the self-aligned bipolar transistor, by forming the first diffusion region and the second diffusion region in a predetermined width and a predetermined region, the base pushing effect, the parasitic capacitance and the parasitic resistance, which are obstacles to speeding up, can be minimized. By reducing the number, the operation speed of the device can be increased.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a self-aligned bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the bipolar transistor of FIG.

FIG. 3 is a diagram illustrating a manufacturing process of the bipolar transistor of FIG.

FIG. 4 is a cross-sectional view showing the configuration of a comparative example for comparison with the bipolar transistor of this example.

FIG. 5 is a cross-sectional view showing the configuration of a comparative example for comparison with the bipolar transistor of this example.

FIG. 6 is a cross-sectional view showing the configuration of a comparative example for comparison with the bipolar transistor of this example.

FIG. 7 is a sectional view showing a configuration of a conventional self-aligned bipolar transistor.

FIG. 8 is a cross-sectional view showing the configuration of another conventional self-aligned bipolar transistor.

[Explanation of symbols]

 21 high-concentration collector buried layer (high-concentration collector layer) 22 low-concentration collector layer 24 internal base diffusion layer (internal base layer) 25 external base diffusion layer (external base layer) 26 high-concentration emitter diffusion layer (emitter layer) 27 external base Extraction electrode 28 Insulation layer 29 Sidewall insulation layer (sidewall) 30 Emitter extraction electrode 31 Second diffusion region (second conductive region) 32 Base / emitter opening (first opening) 33 Emitter opening (second) Opening) 34 First diffusion region (first conductive region)

Claims (3)

[Claims] 1. A one-conductivity-type high-concentration collector layer (21) is provided below an element formation region, and a one-conductivity-type low-concentration collector layer (22) is provided thereon. A reverse conductivity type internal base layer (24) is selectively provided on the upper portion, and reverse conductivity type external base layers (25) are provided on both sides of the internal base layer (24). (24) In a semiconductor device composed of a bipolar transistor having an emitter layer (26) of one conductivity type provided on an upper portion thereof, the low concentration collector layer (21) is provided at a position corresponding to a position of the emitter layer (26). Concentration collector layer (2
2) a first conductive region (34) selectively protruding to a high conductivity layer of one conductivity type, the internal base layer (24) and the low concentration collector layer (2).
2. A semiconductor device, comprising: a second conductive region (31) formed of a high-concentration layer of one conductivity type, which is provided in the vicinity of a junction with (2). 2. The width of the first conductive region (34) is substantially equal to the width of the internal base layer (24), and the width of the second conductive region (31) is the width of the emitter layer (26). The semiconductor device according to claim 1, wherein the semiconductor device is formed to be substantially equal to 3. A high-concentration collector layer (21) of one conductivity type, a low-concentration collector layer (22) of one conductivity type, a base lead electrode (27) of an opposite conductivity type, and an insulating layer (28) are sequentially laminated. A step of selectively removing the base lead electrode (27) and the insulating layer (28) corresponding to a region where the internal base layer (24) is to be formed to form a first opening (32); Using the extraction electrode (27) as a mask, impurity ions of one conductivity type are ion-implanted in a predetermined range from the upper portion of the high concentration collector layer (21) to the low concentration collector layer (22), and the high concentration first conductive region is formed. (34), and a step of forming an internal base layer (24) of opposite conductivity type on the surface of the low concentration collector layer (22) exposed in the first opening (32). Then, the first opening ( Selectively forming a side wall (29) on both side walls 2), after forming the first narrow second opening than the opening (32) (33),
Using the base extraction electrode (27) and the side wall (29) as a mask, impurity ions of one conductivity type are introduced into the internal base layer (24) and the low concentration collector layer (2).
2) forming a high-concentration second conductive region (31) by implanting ions near the junction with the second opening (33); and the second opening (33). And a step of forming an emitter layer (26) of one conductivity type on the surface portion of the internal base layer (24) exposed in FIG.