JPH05100849A - Buffer storage control system - Google Patents

Abstract

PURPOSE:To execute an instruction with sequencing after all the move-in processings of data from a main storage device to a buffer storage are terminated. CONSTITUTION:A data processor composed of an instruction control part 27, an arithmetic control part 28 and a storage control part 9 is provided with a non-move-in processing detection means 1 where a move-in accompanied by a storage request held by a storage buffer 11 detects that there is a move-in request that is not previously executed and an instruction control part processing interlocking means 2 interrupting the processing of an instruction control part 27 if a non-move-in processing is detected when the instruction which requires sequencing is transferred from the instruction control part 27 to the storage control part 9 in a control system controlling data transfer between the main storage device 8 storing data in common in plural data processors, and the buffer storage 151 of the storage control part 9 in a store-in system and executing the storage processing through the storage buffer 11 which temporarily holds the storage request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data when a plurality of data processing systems for executing instructions by pipeline processing equipped with a buffer memory device controlled by a store-in method use a common main memory device. The present invention relates to a buffer storage control method for guaranteeing serialization of a processing device.

[0002]

2. Description of the Related Art In recent years, for data processing systems,
It is required to process a large amount of data at high speed.
To meet this demand, a central processing unit (CPU)
Executes an instruction by pipeline processing,
A multiprocessor system is employed that uses a PU to access a common main memory unit (MSU).

Since the operation of an MSU that stores a large amount of data is slow, each CPU has a buffer memory (LBS) that operates at a high speed, and the data of the MSU is subdivided into a plurality of blocks and the required data is stored. A copy of the block is stored in a small amount of memory. Data access from the CPU is first performed to the LBS, and when the target data does not exist in the LBS, the MSU is accessed, the block in which the target data exists is read from the MSU, and stored in the LBS. (This processing is called MI: move-in). By hierarchizing the storage device in this way, the number of accesses from the CPU to the MSU is reduced,
The processing time can be significantly reduced.

Further, as an LBS control method in a data processing system having such a multiprocessor structure, there is a store-through method in which when rewriting the data of the LBS, the data of the MSU corresponding to the LBS is also rewritten. , At the time of rewriting the LBS, the MSU is not rewritten, and the LBS entry is MSU.
There is a store-in method in which the rewritten LBS data is reflected in the MSU (MO: move out) when the data is returned to.

Since the store-through method requires no MO operation, it is easier to control than the store-in method. However, since the MSU is accessed each time the store is accessed, there is a disadvantage in that if the number of CPUs sharing the MSU increases, the busy rate of the common bus increases and the average access time to the MSU increases.

On the other hand, in the case of the store-in type LBS, since the access to the MSU is limited during the MI and MO operations, it is possible to keep the bus busy rate lower than that of the store-through type. In many cases, the store-in method has been adopted. A conventional example of the control method of the LBS adopting such a store-in method is shown in FIGS.
Will be described. 6 is a configuration diagram of a conventional example, FIG. 7 is a timing explanatory diagram of states executed in main pipeline processing and sub pipeline processing, FIG. 8 is an operation time chart, FIG. 9 is an explanatory diagram of LBS exclusive control, and FIG. It is a specific example of a MOS.

First, before describing the operation of the conventional example, the operation of the CPU subjected to pipeline processing will be described. CP
U is usually divided into three units, which are called an instruction control unit (I unit), an operation control unit (E unit), and a storage control unit (S unit), respectively. The I unit controls the decoding of instructions and the processing based on the decoding. E
The unit executes the operation instructed by the I unit.
The S unit reads and writes the instructions and operands designated by the I unit.

In the I unit, instruction execution is divided into a plurality of states and executed by pipeline processing. Here, the case of being divided into 6 states of D, A, T, B, E and W will be described. In each state D: Decode instruction (decode) A: Operand address calculation T: TLB (logical / physical address conversion) and TAG
(Flag) read B: LBS read E: Operation execution W: Write to register Hereinafter, this pipeline is referred to as the main pipeline.

The S unit has a pipeline independent of the I unit. Here, a case where the state is divided into four states of P, T, B and R will be described. In each state P: Determination of priority of various requests T: Reading and writing of TLB and TAG B: LBS reading and writing R: Processing such as reporting status to I unit and E unit. Hereinafter, this pipeline is called a sub-pipeline.

The T and B states of the main pipeline are
As shown in FIG. 7, it operates in synchronization with the T and B states for operand access in the subpipeline. The logical address of the operand is generated in the I unit in the A cycle and sent to the S unit. The data to be stored is read from the register specified by the instruction and sent to the E unit. The E unit holds this and sends it to the S unit in the E state.

Next, the control operation of the LBS will be described with reference to FIG. As described above, the logical address sent from the I unit in the P cycle is [T cycle Logical Address Register] (TLA) in the T cycle.
R) 17 and buffer memory (TLB) 131 for converting a logical address into a physical address and a tag memory (TAG) 141 in which a flag is stored are accessed. The logical address and the physical address are 31 bits, and bits 1 to 11 of the logical address are a segment index, bits 12 to 19 are a page index, and bits 20 to 31 are a byte index. The byte index is the displacement within the page and is equal to bits 20 to 31 of the physical address.

TLB131 is 2 of PRIMARY and ALTERNATE
There are two ways, one way is from line 256
Each line is composed of bits 1 to 1 of the logical address.
Bit 11 and bit 1 to bit 19 of physical address are paired
And hold. 8 for TAG 141 and LBS 151
One way consists of 64 lines.
It Way and line of TAG141 is LBS15
One-to-one correspondence with one way and line, LB
The address information of the data in S151 and the LBS 151
Change bit that indicates that the data in the
To (C _L) And the block is writable (exclusive type)
Locked or unwritable (common type) block
Has a flag (EX) indicating whether or not

The address held by the TAG 141 holds bits 1 to 19 of the physical address, and the LBS 151
1 line holds the contents of the MSU in blocks of 64 bytes. T is determined by bits 12 to 19 of the logical address held by TLAR17.
Select the line of LB131 and read the logical address and physical address from each of PRIMARY and ALTERNATE. TL
The logical address read from B131 is compared with bits 1 to 11 of the TLAR 17 in the logical address comparator 132. The logical address comparator 132 is PRIMAR.
In Y and ALTERNATE respectively, logical address match is checked at the same time. A signal indicating that the logical addresses match from the two logical address comparators is sent to the physical address selector 134. When the logical addresses on the PRIMARY side match, the physical address on the PRIMARY side is selected, and A
LTERNA If the logical address on the TE side matches, ALTERNA
The physical address on the TE side is selected.

Further, the line of the TAG 141 is selected by the bits 20 to 25 of the TLAR 17 and the address of the data of the LBS 151 is simultaneously read from the eight ways. Physical address comparator 142 provided for each way
The physical address read from the TAG 141 by
The physical address read from the TLB 131 is compared. The result of the comparison is held in the register (LWNR) 114 and is referred to when the way of the LBS 151 is selected and the way of the TAG 141 that registers the C _L bit is selected.

The LBS write way decision circuit 152 is L
The output of the WNR 114 is used as an input to determine which way of the LBS 151 is to be accessed and which way of the TAG 141 the C _L bit is set, and a writable signal is sent to each. Register (BLAR) 18
Holds bit 20 to bit 25 of TLAR17 for B cycles and selects the line of LBS 151 with this output.

The data to be stored is sent from the E unit and IU STDV indicating that this data is valid
A signal is received from the I unit and registered (EUSTD
R) Load the data into 20. The output of the EUSTDR 20 is matched with the address of the LBS 151 by the ALIGN circuit 29, taken into the register (BDIR) 22 via the register (STDR) 113, and written into the LBS 151.

Next, the store access operation will be described in detail with reference to the timing chart of FIG. First, in the P cycle, the I unit 27 sends a store request and a logical address to be stored. When the priority of this request is taken, the first flow of the store is started. In the T cycle, TLAR17 receives the logical address 000 sent from the I unit 27 in the P cycle.
01004 is captured and held. The line of the TLB 131 and the TAG 141 is selected by this logical address.
As a result of comparing the logical addresses by the logical address comparator 132, the PRIMARY side matches and the physical address 000E40
Converted to 04.

The physical address read from the TAG 141 and the physical address obtained from the TLB 131 are compared in the physical address comparator 142. As a result, the way 3 of the TAG 141 is hit and the block to be stored is LB.
It is detected that it exists in the way 3 of S151. The converted physical address is BAAR19 in the B cycle.
Held in. The output of BLAR18 is changed to STLAR11.
2 is held as the logical address to be stored after R cycles. Further, after the R cycle, the way number 3 of the LBS 151 is held in the LWNR 114.

In this R cycle, the IU STDV signal indicating that the data is transferred from the I unit 27 to the E unit and the store data from the E unit 29 are sent. The S unit that received the IU STDV signal is the second store
Set the OP STORE REQUEST signal to start the flow. The OP STORE REQUEST signal starts the second store flow. The EUSTDR 20 uses the IU STDV signal sent in the immediately preceding cycle as a timing signal for EU
Take in STORE DATA "0043D5F2".

Next, in the T cycle, the same TA as the line selected by the first flow of the store by TLAR17.
Select the G line. Way to select is LWNR1
The way 3 is selected by referring to the value of 14. TAG14
1 is written to the selected line of the way 3 of 1 as the C _L bit indicating that the data of the LBS 151 has been changed. Since it is not necessary to convert the logical address to the physical address in this flow, the TLB13
BY PASS TLB so that address translation by 1 is not performed
The signal is set. Further, the data of the EUSTDR 20 is transferred to the STORE Dara Register (STDR) 113.

Next, in the B cycle, the store data is written to the selected line of the way 3 of the LBS 151, and all the processing is completed. Finally, in the R cycle, an STV (STatus Vaiid) signal indicating that the processing of the store request is completed is returned to the I unit 27, and the interlock (continuous E state) of the main pipeline is released.

A plurality of Cs having a store-in type LBS
In a multiprocessor system in which a PU is connected to a common MSU, an exclusion that prohibits multiple CPUs from simultaneously storing in the same block in order to guarantee data matching between the LBS and MSU Control is needed. Therefore, the block with main memory is one CP
It is common to perform control so that it exists only in the LBS of U. However, in this method, when a plurality of CPUs need a common block as a read target,
The overhead required for communication between the CPUs increases, resulting in a significant decrease in performance.

Therefore, an attribute indicating whether or not writing is permitted is given to each block, and exclusive control between the CPUs is performed only for the block where writing is permitted,
The read-only block can be shared by a plurality of CPUs, so that the performance can be improved. These two types of blocks are called an exclusive type block and a shared type block, respectively. The MSU always grasps the address of the block held by each CPU and whether the block is an exclusive type or a shared type, and the It is necessary to perform exclusive control that does not occur. Therefore, the MSU carries out control by giving a copy of the TAG of each CPU.

The operation of the exclusive control in which the MSU has a copy of the TAG in this way will be described with reference to FIG. First,
A case will be described in which the CPU 6 has the block A as an exclusive type, and after the store is performed with respect to the block A, a store request for the block A is generated in the CPU 7. Block A is exclusive and is held by CPU 6, so CPU 7
Block A does not exist. Therefore, the CPU 7 interlocks the main pipeline to hold the store, and the sub pipeline control circuit 12 causes the MSU ReQues
The MI request is set in the t Register (MRQR) 25.
MI Address is Move In Address Re from BAAR19.
Msu ReQuest Addres via gister (MIAR) 30
s Register (MRQAR) 26 (1).

From MRQR25 and MRQAR26 to MSU
An exclusive MI request for block A is issued to 8 (2).
The MSU that has received the exclusive MI request sends the TA of the CPU 6
The TAGC 82 storing the copy of G141 is searched (3), it is detected that the block A is held by the CPU 6 in the exclusive type, and it is reported to the exclusive control circuit 81 (4).

The MSU 8 issues an invalid MO request for block A to the CPU 6 (5). The invalid MO request of the block A from the MSU 8 is an Msu Order Stack (MOS) 3 for holding the request from the MSU in the S unit of the CPU 6.
Held at 1. As shown in FIG. 10, the MOS 31 requests the MO request from the MSU to be MSU Order In Regist first.
er (MOIR) 311. Then INPOI
Register 3 in STACK designated by NTER 313
12 and the value of INPOINTER 313 is incremented. Further, the MO requests are sequentially read from the register 312 in STACK designated by OUTPOINTER 314, and the value of OUTPOINTER 314 is incremented. The read MO request is input to the sub pipeline from the register (MOOR) 315 (6), and the MO processing is started (7).

The CPU 6 moves the block A to the MSU 8 and invalidates the flag Ex for the block A of the TAG 141 from exclusive (8). The MSU 8 writes the MO data (9) and, at the same time, the TAGC 8 corresponding to the CPU 6
2 is changed to a state indicating that the block A does not exist in the CPU 6 (10).

After that, the latest data of the block A is read (11), and the TAGC 83 corresponding to the CPU 7 is changed to a state indicating that the block A exists in the CPU 7 in the exclusive type (12). The data of block A is sent to CPU 7 by M
I (13), the pending store is performed for the block A, and the interlock of the main pipeline is released.

Further, the flag Ex for the block A of the TAG 141 of the CPU 7 is changed to the exclusive type, and the C _L bit is changed to "1" indicating that the data is changed. next,
A case where a store request is issued to the block A in the CPU 7 while the CPU 6 and the CPU 7 are the shared type and holds the block A at the same time will be described.

The CPU 7 holds the block A,
Store cannot be executed because it is not exclusive type.
Therefore, the CPU 7 suspends the store by interlocking the main pipeline, and issues a block change request for the block A from the shared type to the exclusive type to the MSU 8.

MSU 8 which received the block change request
Searches all TAGC and detects that the block A is held in the CPU 6 in a shared type. MSU8 is CP
A block invalidation (BI) request for block A is issued to U6. CP that received BI request of block A from MSU
U6 invalidates the state of block A of TAG 141 from shared and notifies the MSU that the block change is complete.

When the MSU receives the completion notice, the CPU 6
The TAGC 82 corresponding to the CPU 6 is changed to a state indicating that the block A does not exist in the CPU 6, and the T corresponding to the CPU 7
The AGC 83 is changed to a state indicating that the block A exists in the CPU 7 in the exclusive type. After that, the CPU 7 sends a change permission notification from the shared type of the block A to the exclusive type.

After receiving the change permission notification sent from the MSU 8, the CPU 7 sets the block A to the exclusive type,
The pending store is performed for block A and the interlock of the main pipeline is released. By the control as described above, the store-in type LBS and MS
The data match with U is maintained. However, according to the control described above, the main pipeline has to wait until the store to the LBS is completed, which results in a large decrease in performance. Therefore, a register (STB: store buffer) for temporarily holding the store data is provided, the store from the main pipeline is held in the store buffer, and the I unit ends the store at the time of writing to the store buffer. In view of this, a method was devised in which the main pipeline is advanced and the S unit controls writing to the LBS within its own unit.

The structure provided with this STB is shown in FIG.
A specific example of the B control circuit is shown in FIG. In FIG. 11, STB11 is four sets of STLAR112 and STDR1.
13, LWNR 114 and STB control circuit 111. Further, the STB control circuit 111 is similar to that shown in FIG.
As shown in 2, INPOINTER51, OUTPO
It is composed of INTER 52 and STAR VALID REG 53.

The INPOINTER 51 is a 2-bit counter, and the STLAR 112 and STDR 11 to be used next.
Specify 3. The OUTPOINTER 52 is a 2-bit counter, and the STLAR 112 and STDR to be processed next.
Specify 113. These counter values are decoded by ANDs 54 and 55, the registers designated by STLAR and STDR are selected, and data is input / output. The INPOINTER 51 is designated by a vacant register, and the OUTPOINTER 52 is designated by the sub-pipeline control circuit 12 based on the priority determination in the P state.

The STAR VALID REG 53 is a 4-bit register, and each bit has each STLAR and STD.
Corresponding to R, when this bit is set to 1, it indicates that the corresponding register holds a valid store request. When valid store requests are held in all four store buffers, the STB FULL signal is set by AND 5 and 6 to suppress new store requests and sent to the sub-pipeline control circuit, and S unit busy. Send signal SU BUSY to I unit.

FIG. 13 shows an operation timing chart when the block to be stored in the LBS has the exclusive type in the configuration of FIG. In this case, the STV described in FIG.
The signal is returned in the R cycle of the first flow of the store request, the main pipeline is not interlocked, and the state immediately shifts to the W state. That is, when the store request is stored in STB11, the STV signal is sent to the I unit, the data in STB11 is read, and the store process is executed.

Further, in FIG. 14, after the CPU 6 has the block A as an exclusive type and stores to the block A,
7 shows a time chart of the CPU 7 when a store request for the block A is generated in the CPU 7. In this case, the block A is the CP in the T cycle of the first flow.
Since it exists only in U6, no TAG match was detected,
The exclusive MI request is set in the R cycle, but the STV signal is returned to the I unit and the main pipeline does not interlock. That is, the data of BAAR19 is transferred to MIAR30 in R cycles and then M
An address is sent from the RQAR 26 and an exclusive MI request is sent from the MRQR 25 to the MSU. In response to this MI request, the MSU sends an invalidation MO request to the block A to the CPU 6, causes the MSU to transfer the data, and then transfers the data in the block A from the MSU to the CPU 7, as described above. After the data is set in the LBS of the CPU 7, the second store flow is executed.

Further, FIG. 15 shows that the CPU 6 and the CPU 7 are of the shared type and hold the block A at the same time.
7 shows a time chart of the CPU 7 when a store request is issued to the block A in FIG. In this case, a TAG match is detected in the T cycle of the first flow, it is detected that this block is a shared type, and a request to change the block A to an exclusive type is set in the R cycle. In this case, the STV signal is not returned to the I unit. The reason why the STV signal is not returned is that the store request for block A is C
This is because if they occur at the same time in the PU 6, the data of the block A having different contents will exist in the CPU 6 and the CPU 7, and the consistency cannot be guaranteed. Therefore, in this case, the main pipeline is interlocked. That is, the data of the BAAR 19 is transferred to the MIAR 30 in the R cycle, and subsequently, the address is sent from the MAQAR 26 and the block change request is sent from the MRQR 25 to the MSU. The second flow is executed after receiving the block change permission notification from the MSU in response to this block change request, and the STV signal is returned to the I unit in this R cycle, and the interlock of the main pipeline is released. ..

[0040]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When the store-in control method using B is adopted, when the instruction from the I unit is recorded in the STB, the instruction is released at the time of recording and the processing is completed.

Therefore, the instructions executed in the I unit are CS (Compare an
If the instruction is one that requires CPU serialization, such as a d Swap) instruction or a CDS (Compare and Double Swap) instruction, a store accompanied by MI recorded in the STB is executed before the execution of this instruction occurs. There is a problem that all the instructions must be completed.

According to the present invention, in the method of controlling the buffer storage by using the store buffer in the store-in control method, for the instruction requesting the serialization, all the data recorded in the store buffer is the main storage. It is an object of the present invention to provide an improved buffer storage control method that guarantees serialization so that it is executed after being reflected in.

[0043]

Means adopted by the present invention for solving the above-mentioned problems will be described with reference to FIG. FIG. 1 shows the principle of the present invention. A data processing device including an instruction control unit 27, an operation control unit 28, and a storage control unit 9 includes a main storage device 8 that stores data commonly among a plurality of data processing devices, and a buffer storage 151 of the storage control unit 9. Store-in control of data transfer between
In the control method in which the store processing to the buffer storage 151 is performed via the store buffer 11 that temporarily holds the store request, the move-in with the store request held in the store buffer 11 has not been executed yet. When a move-in process detecting means 1 for detecting the presence of a move-in request and a command requiring serialization are transferred from the command controller 27 to the storage controller 9,
And an instruction control unit process interlock unit 2 for interrupting the process of the instruction control unit 27 when the unmoved-in process detection unit 1 detects the unmoved-in process.

[0044]

In the store buffer 11, a request involving move-in processing that requires data transfer from the main storage device to the buffer storage 151 from the instruction control unit 27 is stored. The non-move-in process detection means 1 uses the store buffer 11
It is checked whether or not a request for which the move-in process has not been executed is stored, and if there is an unprocessed request, an unprocessed signal is output.

The instruction control unit processing interlock means 2 is
When an instruction requiring serialization is transferred from the instruction control unit 27 to the storage control unit 10 and an unprocessed signal is output from the unmove-in process detection means 1, an instruction is sent to the instruction control unit 27. A signal is sent to interrupt the processing of the control unit.

When the instruction control unit 27 receives the processing interruption signal from the instruction control unit processing interlock means 2, the processing is interrupted. When the process of the instruction control unit 27 is interrupted, the command accompanied by the new move-in process is not transferred to the storage control unit 9, and the move-in process stored in the store buffer 11 is continued.

When all the processes stored in the store buffer 11 are processed, an unprocessed no signal is sent to the output of the unmove-in process detection means 1, and the command control section 27 from the command control section processing interlock means 2. Stop sending the signal that interrupts the process. When the suspension of the processing in the instruction control unit 27 is released, the suspended instruction requiring serialization is transferred to the storage control unit 10 and the processing is executed.

As described above, it is detected whether or not there is a process which is stored in the store buffer and is not yet subjected to the move-in process, and when there is an unprocessed and an instruction requiring serialization is input. Since the processing of the instruction control unit is interrupted, all the processing accompanied by the unprocessed move-in is executed during the interruption, and the instruction requiring serialization is executed after all the processing is completed. Therefore, serialization can be guaranteed.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a concrete example of a non-move-in process detection means and an instruction control unit process interlock means, FIG. 4 is a concrete example of a move-in buffer part, and FIG. 5 is a move-in buffer. It is an operation time chart.

In FIG. 2, the store buffer (STB)
Except for the move-in buffer (MIB) unit 10 that controls the transfer of data blocks from the unit 11 and the MSU, it is as described with reference to FIGS. Also,
In the embodiment, the unmove-in process detecting means 1 described with reference to FIG.
The instruction control unit processing interrupt means 2 is installed in the STB unit and will be described later in detail with reference to FIG.

First, the MIB section 10 will be described with reference to FIG. In the embodiment, one block of LBS is 64 bytes,
The data bus between the CPU and the MSU has a width of 8 bytes, and the transfer data from the MSU is transferred in 8 bytes, divided into 8 times. The MIB unit 10 first moves this data to Move.
Received in the In Data Buffer Register (MIDBR) 103, and from here, Move In Data Register (MIDR) 1
Set each 8 bytes to 04. MIDR 104 to 64
Writing to the LBS is performed after setting all the bytes of data. The MSU sends the DOW signal eight times prior to the MI data in order to instruct the timing for fetching the MI data, and the DOW signal is recorded in the shift register 101. Also, the identification number added to the MI request and sent from the CPU is sent back. This M
Holding the identification number from SU is Msu Move In ID Reg
ister (MMIIDR) 106.

In addition, the Move In Address Register (MIA
In R) 107, the address of the data block that MI from the MSU to the LBS is stored. M from MSU to LBS
As for I, as shown in FIG. 5, the DOW signal instructing the data acquisition timing is continuously transferred eight times from the MSU.
This DOW signal is recorded in the shift register 101 and sequentially shifted.

Based on the DOW recording condition of the shift register 101, the number generating circuit 102 generates a block number for storing data in the MIDR 104. With this signal,
8 transferred from MSU and recorded in MIDBR103
The byte data is sequentially stored in the MIDR 104, and when all the data is stored, it is moved to the BDIR 22 and read into the LBS.

When the MI from the MSU to the LBS is started, the identification number sent in addition to the MI request to the MSU is returned together with the DOW signal, and the MMIID is returned.
It is stored in R106. The stored identification number is held in the MMIIDR 106 until the MI data is stored in the LBS.

Next, referring to FIG. 3, the unmove-in processing detecting means 1 and the instruction control processing interlock means 2
Will be described. In FIG. 3, STLAR 112,
STDR113, LWNR114 and selector 11
5, 116 and 117 are as described in FIG. 11, and the STB control circuit 111 is as described in FIG.

Move In ID Register (MIIDR) 11
The 8 and Move In Pend (MIP) latches 121 are each composed of 4 sets, and include STLAR 112 and STDR 11
Data corresponding to 4 sets of registers of 3 and LWNR and one to one are stored. The MIIDR 118 stores the identification number of the MI request to the MSU. Further, the MIP latch 121 indicates that when the latch is on, the block to be stored in the store buffer does not exist in the LBS, so that the MIP latch 121 is currently waiting for MI from the MSU.

Further, in the non-move-in process detecting means 1, 119 is a comparator, which compares the ID of the MIIDR 118 and the MMIIDR 106 described in FIG.
The output is "1". Further, 120 is an AND circuit, and 122 is an OR circuit.

The instruction control unit processing interlock means 2 is
AND circuits 124 and 125 and register (SRCR)
It is composed of 123. The SRCR 123 to which the instruction requesting the serialization is transferred from the I unit and the output of the unmove-in process detecting means 1 is "1" is set to set the output to "1". Further, when the signal from the unmove-in process detecting means 1 is converted from "1" to "0", SRCR1
23 is reset and outputs "0".

Next, the operation of the embodiment when the operand access request accompanied by the serialization request occurs in the state where the LBS misses in the execution of the store request without the serialization request and the MI data waits. Will be explained. A store request is sent from the signal line 1101 to the P state, a serialization request is sent from the signal line 1102, and a logical address is sent from the signal line 1103. When the priority of this request is taken by the sub-pipeline control circuit 12, the signal line 1103
The logical address from is selected by the selector 16, and the first flow of the store process is started.

In the T state, this logical address is TLA
Held in R17. Based on the output 1104 of the TLAR 17, the TLB unit 13 converts the logical address into an absolute address, and the TAG unit 14 checks whether or not there is a block to be stored in the LBS 151. L
When it is detected that the block to be fetched does not exist in the BS 151, it is reported to the sub-pipeline control circuit 12 via the signal line 1106.

In the B state, the logical address is the signal line 11
04 is input to the BLAR 18 and the absolute address is stored in the BAAR 19 to which the signal line 1105 is input. The sub pipeline control circuit 12 uses the signal line 111
A value of 0 notifies that an MI request has occurred in the MIB section. This notification is also sent to the STB unit 14 and the MIP latch 121 is set.

In the R state, the logical address is the signal line 11
08 is input, the way number for reading data is the signal line 1107, and STLA in STB is input.
It is taken into R112 and LWNR114. MIB part 1
In 0, the MI request notification signal notified from the sub-pipeline control circuit 12 to the B state is taken as the data fetch timing instruction signal (CE) and the output 1109 of the BAAR 19 is fetched into the MIAR 107. Further, the STV signal is returned to the I unit from the signal line 1117, and the main pipeline continues processing without interlocking. Also, in this state, the signal line 1 from the I unit
A STDV signal is sent from 113.

At the next state after receiving the STDV signal, E
Stored data from the unit is taken into the EUSTDR 20 which receives the signal line 1114 as an input. In this state, the MRQAR 26 takes in the output 1114 of the MIAR 107 in the MIB, and the request contents (MI request in this case) and the request identification number to the MSU for this address are transmitted from the signal lines 1112, 1111 to MRQR25, MR, respectively.
It is taken into the QIDR 24 and sent to the MSU. The identification number of the signal line 1111 is also set in the MIDR 118 in the STB.

The state in which the MIP latch 121 in the STB is set indicates that a store request in which MI data has never been sent from the MSU is held in the STB, and the four latches The output is the OR circuit 122
, And is added to AND circuits 124 and 125 of the instruction control unit processing interlock means 2. However, SRC
The output of the AND circuit 125 is "0" because a signal that is an instruction requesting serialization is not set in R123.
Becomes

In this state, when an operand access request accompanied by a request for serialization is received from the I unit, the output of the AND circuit 124 becomes "1" and the SRCR
123 is set and the output of the AND circuit 125 is "1".
Therefore, the STV signal is not returned in the R cycle of this request,
The signal is held in the S unit, and a SU BUSY signal indicating that the S unit cannot accept a new request from the I unit is sent from the signal line 1116 to the I unit. During this time, the main pipeline processing is interlocked and stopped.

The first DOW signal from the MSU is signal line 11
When sent from 18, MSU from the MSU to the next state
The identification number of I is sent from the signal line 1119. This MI ID is held in the MMIIDR 16 in the MIB during MI operation. The output of the MMIIDR 106 is the signal line 112.
1 is sent to STB. This value is the MIID in STB
The value of R118 is compared with the comparison circuit 119. MI
If the IDs of the two match, the comparison circuit 119 outputs "1". The comparison result is “1” and the MIP latch 12
If 1 is set, the AND circuit 120 outputs "1". The output of the AND circuit 120 is MIP
It is connected to the reset terminal of the latch 121, and when the output of the AND circuit 120 takes "1", the MIP latch 121
Is reset.

When all the MIP latches are reset, the signal line 1115 is turned off, and the sub-pipeline control circuit 12 resumes execution of the pending operand access request accompanied by the serialization request. When this operand access is completed, the S unit returns the STV signal to the I unit and simultaneously turns off the SU BUSY signal.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications can be made according to the gist of the invention.

[0069]

As described above, according to the present invention, the following effects can be obtained. Detects whether there is any processing that is not stored in the store buffer and that has not been moved in. If there is an unprocessed instruction and an instruction that requires serialization is input, the processing of the instruction control unit is interrupted. As a result, all processing with unprocessed move-ins is executed during suspension, and after all processing is completed, instructions that require serialization are executed, so serialization is guaranteed. be able to.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a specific example of an unmove-in process detection means and an instruction control unit processing interrupt means of the embodiment.

FIG. 4 is a specific example of a move-in buffer unit.

FIG. 5 is an operation time chart of the move-in buffer.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is an explanatory diagram of states executed in main pipeline processing and sub pipeline processing.

FIG. 8 is an operation time chart of the embodiment.

FIG. 9 is an explanatory diagram of LBS exclusive control.

FIG. 10 is a concrete example of a MOS.

FIG. 11 is a configuration diagram of a conventional example provided with an STB.

FIG. 12 is a specific example of the STB control circuit of the same embodiment.

FIG. 13 is a store access operation time chart in the case where the exclusive block of the embodiment is held.

FIG. 14 is a store access operation time chart when the exclusive block of the embodiment is not held.

FIG. 15 is a store access operation time chart when the shared block of the embodiment is held.

[Explanation of symbols]

1 non-move-in processing detection means 2 instruction control section processing interlock means 6, 7 CPU 8 main storage unit (MSU) 9 storage control section 10 move-in buffer (MIB) section 11 store buffer (STB) section 12 sub-pipeline control circuit 13 Logical / physical address conversion buffer storage (TLB)
Unit 14 tag memory (TAG) unit 15 buffer storage (LBS) unit 27 instruction control unit (I unit) 28 arithmetic control unit (E unit) 131 logical / physical address conversion buffer storage (TL)
B) 141 Tag memory (TAG) 151 Buffer storage (LBS) 17, 18, 19, 20, 22, 24, 25, 26, 1
03, 104, 107, 112, 113, 114, 11
8,123 registers 16, 21, 23, 108, 115, 116, 117
Selector 119,132,142 Comparator 54,56,120,124,125 AND circuit 121 Latch 122 OR circuit

Claims (2)

[Claims] 1. A data processing device comprising an instruction control unit 27, an operation control unit 28, and a storage control unit 9, and a main storage device 8 and a storage control unit 9 which store data in common among a plurality of data processing devices. In the control method, the data transfer to and from the buffer memory 151 is controlled by the store-in method, and the store processing to the buffer memory 151 is performed via the store buffer 11 that temporarily holds the store request. The move-in accompanied by the store request held in the store buffer 11 requires serialization by the instruction control unit 27 and the un-move-in process detection unit 1 that detects that there is a move-in request that has not been executed yet. When an instruction is transferred to the storage control unit 9, and the unmoved-in processing is detected by the unmoved-in processing detecting means 1, the life is Buffer storage control method characterized by comprising an instruction control unit processing interlocking means 2 for interrupting the processing of the control unit 27. 2. The unmove-in process detection means 1 compares the identification number of the move-in request set by the move-in request stored in the store buffer 11 with the identification number returned from the main storage device 8 and matches them. 2. The buffer storage control according to claim 1, further comprising: a plurality of latches 121 that are reset when the latch circuit 121 is activated, and an OR circuit 122 that detects that any one of the plurality of latches 121 is set. method.