JPH049336B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a clock signal generation circuit, and more particularly to a high speed clock signal generation circuit.

(Background of the Invention) Conventionally, a clock signal for timing control of a microprocessor (CPU) is a low frequency signal of, for example, about 30 kHz, and is generally generated by a crystal oscillator. If the clock signal frequency is low,
One machine cycle for executing one instruction by the CPU becomes longer, slowing down the processing speed. Increasing the clock signal frequency in order to operate this CPU at high speed increases power consumption, making it difficult to operate it on batteries for long periods of time. Therefore, the conventional clock signal generation circuit has the drawback that it is difficult to achieve both low power consumption operation of the CPU and high speed operation during one machine cycle period.

(Object of the Invention) An object of the present invention is to provide a clock signal generation circuit that intermittently oscillates a high-speed clock signal.

Another object of the present invention is to provide a clock signal generation circuit that can be used as a high-speed clock source for a microprocessor that operates with two systems of clock signals.

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Circuit Configuration of the Invention) FIG. 1 shows a high-speed clock signal generation circuit according to an embodiment of the invention.

In FIG. 1, this high-speed clock signal generation circuit is comprised of a crystal oscillation circuit 1, a ring oscillation circuit 2, a counting circuit 3, and a control circuit 4.

The crystal oscillator circuit 1 includes an inverter 5, a crystal oscillator 6, a resistor R, and capacitors C1 and C2, and outputs a low-speed basic clock signal (for example, 10 to 50 kHz). This basic clock signal A is used, for example, as a clock source for operating the CPU at low speed.

The ring oscillation circuit 2 includes a delay circuit 7 and a gate circuit 8
consists of a high-speed clock signal (e.g. 1 to
12MHz). The OR delay circuit 7 is composed of a plurality of inverters 9 and a Schmitt trigger circuit 10 connected in series, and the gate circuit 8 is composed of an inverter 11 and a two-input logic circuit 12 connected in series. The signal input section of the delay circuit 7 and the signal output section of the inverter 11 are commonly connected, and the signal output section of the delay circuit 7 is connected to one signal input section of the logic circuit 12. The oscillation of the ring oscillation circuit 2 is controlled by a control signal input to the other signal input terminal of the logic circuit 12, and its oscillation frequency is determined by the number of stages of inverters 9 forming the delay circuit 7. Schmitt trigger circuit 10 is used to stabilize the ring oscillation condition.

The counting circuit 3 includes D-type flip-flops 13, 14, 1 having a reset function connected in series.
5, 16 and the terminals of these flip-flops.
4-input logic circuit 17 into which the NOR output signal is input
It counts the number of pulses of the high-speed clock signal output from the ring oscillation circuit 2 and outputs a control pulse signal. This high-speed clock signal C is used, for example, as a clock source for operating the CPU at high speed. flipflop 13,
Reset terminals R of 14, 15, and 16 are commonly connected to the output part of the oscillation circuit 1, and the reset terminals R of the flip-flop 1
The signal input section 3 is commonly connected to the inverter 9 and the clock signal output terminal 20. This signal output terminal 20 is connected, for example, to a clock signal input section of a microprocessor.

The control circuit 4 has a flip-flop 18 and two inputs.
It is composed of an OR logic circuit 19 and outputs a control signal for controlling the oscillation operation of the ring oscillation circuit 2 in response to a pulse signal output from the control circuit 3. The flip-flop 18 has a signal input terminal connected to a clock input terminal 20 of a microprocessor, a data signal terminal D connected to an output terminal of the NOR logic circuit 17, and an output terminal of the crystal oscillation circuit 1. The ring oscillation circuit 17 has a reset terminal R connected to the ring oscillation circuit 17, and receives the output signal of the ring oscillation circuit 17 to the data terminal D. The OR logic circuit 19 has two input signal sections connected to the output terminal Q and the reset terminal R of the flip-flop 18, respectively, and its signal output section is connected to the other signal input section of the OR logic circuit 12.

(Circuit Operation of the Invention) Next, the operation shown in FIG. 1 will be explained according to the operation timing chart shown in FIG. 2. Note that (A) to (I) are the first
FIG. 3 is a waveform diagram of portions indicated by the same reference numerals in the figure.

During the fast clock period shown in Figure 2,
The crystal oscillator circuit 1 sends a low-speed reference clock signal A (for example, about 10 to 50 kHz) to a flip-flop 13,
It is supplied to the reset signal terminals R of 14, 15, 16, and 18 and to the OR logic circuit 19. When the basic clock signal is logic “1”, flip-flop 1
3, 14, 15, and 16 are in the reset state, and each Q output becomes logic "1", "1", "1", "1",
These signals are input to the NOR logic circuit 17 and output logic "0" (D, E, F, G, H in Figure 2).
reference). A flip-flop 18 to which the reset signal and the output signal of the logic circuit 17 are simultaneously input.
The Q output of will be logic "0". Therefore, the OR logic circuit 19 outputs a logic "1" and stops the oscillation operation of the ring oscillation circuit 2, so a logic "0" is output to the clock signal output terminal 20 (see FIG. 2I,
(See B and C). Next, the basic clock signal is logic “1”
When it changes from to “0”, flip-flop 1
3, 14, 15, 16, and 18 are released from the reset state. At the same time, the output of the logic circuit 19 changes from logic "1" to "0", and the ring oscillation circuit 2 starts oscillating and outputs a high speed clock pulse signal (see FIG. 2C). As a result, as shown in FIG. 2e, the high speed clock pulse signal is generated during the "0" level period of the control signal B, and is used, for example, as a timing control signal for the machine cycle of a microprocessor. The counting circuit 3 starts counting, and when it counts 15 pulses of the high speed clock signal, it outputs a pulse signal to the signal input terminal D of the flip-flop 18 (see FIG. 2H). This flip-flop 18 outputs a logic “1” to the OR logic circuit 19.
Therefore, the OR logic circuit 19 generates an output signal of logic "1" and stops the oscillation operation of the ring oscillation circuit 2 (see FIG. 2 I and B). Therefore, the clock signal output terminal 20 becomes logic "0" and the flip-flops 13, 14, 15, 16,
The 18 output signals Q are respectively logical "1", "1", "1",
It is held at “1”.

Next, when the output signal of the oscillation circuit 1 changes from logic "0" to "1", the flip-flops 13 and 1
4, 15, 16, and 18 are in the reset state, and at the same time, the output terminal Q of the flip-flop 18 changes from logic "1" to "0".

The output signal of oscillation circuit 1 changes from logic “1” to “0”
, flip-flops 13, 14, 1
5, 16, and 18 are released, the ring oscillation circuit 2 starts oscillating again, and thereafter outputs high-speed clock pulse signals intermittently using the same operating means. In this manner, the clock generating circuit shown in FIG. 1 generates a high-speed clock signal at a constant period using the counting circuit 3.

Switching to the low-speed clock period for low power consumption operation shown in FIG. 2 is carried out by, for example, a switch not shown, and the low-speed clock A is directly input to the CPU from the crystal oscillator circuit 1. used for. This operation mode switching can also be done by software.

In the circuit shown in FIG. 1, the high speed clock generation period is set shorter than the logic "0" level period of the low speed clock signal, as shown in FIGS. 2A and 2B.

Generally, microcomputers and microprocessors are controlled by a clock signal of a constant frequency. However, it is not necessary for such a circuit to always operate at high speed; if it operates at high speed for only the necessary machine cycles as shown in Figure 2C, and operates at normal speed for the rest of the time, it will be possible to use a microcomputer or It is possible to achieve both high-speed operation and low power consumption of the microprocessor. Since the clock signal generation circuit of the present invention can generate a clock signal that enables the above-described operation, it can be applied as a clock source for microcomputers and microprocessors configured to operate with multiple clock sources. be.

As explained above, the clock signal generation circuit of the present invention intermittently outputs a high-speed clock signal based on a low-speed clock signal, and can be used as a timing control signal for microcomputers, microprocessors, etc., and can control these machine cycles. It becomes possible to increase the speed. Since the inventive circuit generates a high speed clock signal only during the period necessary for the machine cycle of the device, the average power consumption of the clock signal generation circuit is greatly reduced.

This inventive circuit can be very easily implemented using an integrated circuit using MOS type transistors.

[Brief explanation of drawings]

FIG. 1 is a diagram of a high speed clock signal generation circuit according to the present invention, and FIG. 2 is an operation timing diagram for the embodiment of FIG. 1...Crystal oscillation circuit, 2...Ring oscillation circuit,
3... Counting circuit, 4... Control circuit.

Claims (1)

[Scope of Claims] 1. A ring oscillation circuit that outputs a high-speed clock signal, a counting circuit that outputs a control signal after counting the number of clock pulses of the high-speed clock signal for a predetermined period, and the control signal of the counting circuit is inputted. then stops the operation of the ring oscillation circuit for a predetermined period,
and a control circuit that outputs a signal to the ring oscillation circuit to start operation of the ring oscillation circuit when the low-speed clock signal output from the crystal oscillation circuit is input. 2. The ring oscillation circuit is characterized by comprising a delay circuit and a gate circuit that selectively feeds back the output signal of the delay circuit as the high-speed clock signal to the input section of the delay circuit according to the output signal of the control circuit. A signal generating circuit according to claim 1. 3 The frequency of the low-speed clock signal is approximately 10 to 50k.
Hz, and the frequency of the high speed clock signal is approximately 1
2. The clock signal generating circuit according to claim 1, wherein the clock signal generating circuit has a frequency of 12 MHz.