JPH0491481A - Mis field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a high integration, and high performance MIS field transistor capable of operating at high speed by installing a trench in a semiconductor substrate of one conductivity type on both ends of a side wall insulation film, providing an insulation film partially on the side walls of the trench, burying the insulated trench, and installing a conducing film so that it may face the side of a source/drain region. CONSTITUTION:An electrode 9 is installed on an n-type silicon substrate 1 by way of a gate oxide film 8. A low concentration p-type source/drain region 3 is installed directly upper a side wall insulation film 10 formed on the side wall of the gate electrode 9 based on self-alignment where a trench 4 is installed in the n-type silicon substrate 1 on both ends of the side wall insulation film 10 based on self-alignment. An oxide film 5 is installed on a part of the side wall of the trench 4 and the bottom. The trench 4 where the oxide film is installed is buried and moreover, a conductive film 7 is installed so that it may come into contact with the p-type source/drain region.

Description

[Detailed Description of the Invention] [Summary] A gate electrode is provided on a semiconductor substrate of one conductivity type via a gate oxide film, and a low concentration source/drain region is formed under a sidewall insulating film with self-alignment formed on the sidewall of the gate electrode. A trench is provided in the semiconductor substrate of one conductivity type at both ends of the sidewall insulating film, an insulating film is provided on a part of the side surface and the bottom of the trench, and the trench provided with the insulating film is filled with Since a MIS field effect transistor is formed with a structure in which a conductive film is provided in contact with the side surface of the source/drain region, the source/drain region includes a shallow, low concentration impurity region that minimizes lateral diffusion under the gate electrode. Because the gate length can be made finer, the gate length can be made finer, and the source/drain regions can be made of a low-resistance conductive film, so the transfer conductance can be increased, and the source train made of the conductive film can be made finer. Since the region can be formed on the insulating film, the capacitance of the source/drain region can be reduced, resulting in higher speeds, and since the source/drain region can be formed in which only the low concentration impurity region is in contact with the semiconductor substrate, the junction breakdown voltage can be increased, resulting in higher performance. MIS field effect transistor that made this possible.

"Industrial Application Field" The present invention relates to MIS type semiconductor devices, and particularly to a P-channel MIS field effect transistor that is difficult to miniaturize and speed up.

Conventionally, P-channel MIS field effect transistors*
-1□ Regarding channeling, there is no need to take into account the deterioration of the transfer conductance over the lifetime due to the so-called pot electron effect.
There is no need to form a doped (rain) structure, and a conventional MIS field effect transistor is formed in which a highly doped source/drain region is provided in a self-aligned line at both ends of a gate electrode. However, at present, boron, which has a large diffusion coefficient, is the only ion species that forms the source and drain regions, so the source train region is formed deep, and the lateral diffusion under the gate electrode is large, easily causing the punch-through phenomenon. Therefore, problems such as the inability to miniaturize the gate length and the large capacitance and resistance of the gate capacitance and source train region are becoming a major obstacle to higher integration and higher speed9. There is a need for a means for forming a high-speed, highly integrated P-channel MIS field effect transistor in which the gate length can be miniaturized and the gate capacitance and the capacitance and resistance of the source and drain regions can be reduced.

[Prior Art] FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor, in which 51 is an n-type silicon (Si) substrate, 52 is an n-type silicon (Si) substrate, and 52 is an n-type silicon (Si) substrate.
53 is a p-type channel stopper region, 53 is a p-type source train region, 54 is a field oxide film, 55 is a gate oxide film, 56 is a gate electrode, 57 is an oxide film for impurity blocking,
Reference numeral 58 indicates a phosphosilicate glass (PSG) film, and reference numeral 59 indicates an AI wiring.

In the figure, a gate electrode 56 is provided on an n-type silicon (Si) substrate 51 with a gate oxide film 55 interposed therebetween.
A p-type source/drain region 5 is provided at both ends of the gate electrode 56.
A P-channel MIS field effect transistor with a conventional structure is formed.9 Although the manufacturing process is extremely simple and easy to make, the highly doped source train region formed by boron ion implantation is formed deep. Therefore, the lateral diffusion under the gate electrode is large, and the curvature of the diffusion layer is also large, so the depletion layer spreads widely and punch-through phenomenon easily occurs.As a result, the gate length cannot be miniaturized, making it difficult to achieve high integration. Problems to be solved by the present invention The problems to be solved by the present invention are as follows: As shown in the conventional example, in a conventional conventional P-channel MIS field effect transistor, the highly doped source/drain region cannot be formed shallowly, so the lateral diffusion under the gate electrode is large, and punch-through phenomenon easily occurs. Because of this, it was difficult to further reduce the gate length and achieve high integration.
It was difficult to reduce the gate capacitance because it was difficult to miniaturize the gate length, and it was difficult to increase the speed because it was impossible to reduce the capacitance and resistance because the source/drain regions were formed by impurity diffusion.

Means for Solving Problem 1] The problem described above is that the semiconductor substrate of one conductivity type and the
A gate insulating film provided on a conductive substrate 1-1, a gate electrode provided on the gate insulating film, and sources of opposite conductivity types provided equidistantly on the semiconductor substrate at both ends of the gate electrode. a drain region, a trench provided in the semiconductor substrate equidistantly outward from both ends of the gate electrode, an insulating film provided on a part of the side surface and a bottom surface of the trench, and the insulating film provided. This problem is solved by the MIS field effect transistor of the present invention, which includes a trench buried therein and a conductive film in contact with the side surfaces of the source and drain regions.

[Function] That is, in the semiconductor device of the present invention, a gate electrode is provided on a semiconductor substrate of one conductivity type via a gate oxide film, and a low-concentration insulating film is formed under a sidewall insulating film in which a self-line is formed on the sidewall of the gate electrode. A source/drain region is provided, a trench is provided in one conductivity type semiconductor substrate at both ends of the sidewall insulating film,
An MIS field effect transistor is formed having a structure in which an insulating film is provided on part of the side surfaces and the bottom of the trench, and a conductive film is provided that buries the trench provided with the insulating film and is in contact with the side surfaces of the source and drain regions. 9
Therefore, all the constituent regions can be formed as self-aligned lines, and source/drain regions including shallow, low-concentration impurity regions with minimal lateral diffusion under the gate electrode can be formed, resulting in higher integration by miniaturizing the gate length. of,
The gate length can be miniaturized, and the source/drain region made of a low-resistance conductive film without a relatively high-resistance, high-concentration impurity region can be formed, which increases the transfer conductance. In order to increase speed by reducing the capacitance of the source train region, it is possible to reduce the capacitance of the source train region by making only the low concentration impurity region contact the semiconductor substrate, and surrounding the conductive film other than the low concentration impurity region with an insulating film. By forming the source/drain region, the breakdown voltage of the junction can be increased, thereby making it possible to improve the performance. That is, high integration,
M enables the formation of high-speed, high-performance semiconductor integrated circuits
An IS field effect transistor can be obtained.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view of a first embodiment of the MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view of the MIS field effect transistor of the present invention.
FIG. 3 is a schematic side sectional view of a second embodiment of a field effect transistor; FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention; FIGS.
e) is a process cross-sectional view of one embodiment of the manufacturing method for the MIS field effect transistor of the present invention.

Identical objects are indicated by the same numbers and symbols throughout the figures.

Figure 1 shows the MI of the present invention when using an n-type silicon substrate.
This is a schematic side sectional view of the first embodiment of the S field effect transistor, where ■ is a low type silicon substrate of about 10 cm, 2 is an n-type channel stopper region of about 10 cm, and 3 is a p-type source of about 1017cn+-3. Drain region, 4 is a trench for forming a source train region with a depth of approximately 500 nm, 5 is a buried oxide film with a thickness of approximately 1100 nm, 6 is a field oxide film with a thickness of approximately 600 nm, 7 is a buried conductive film, and 8 is a trench with a thickness of approximately 18 nm. 9 is a gate electrode of about 300 nm+, 10 is a sidewall oxide film of about 250 nm, 11 is an oxide film for impurity blocking of about 35 nm, and 12 is a phosphorus size of about 600 nm. Gate oxide film 8 on − type silicon substrate 1
A low concentration p-type source/drain region 3 is provided directly below a sidewall insulating film 10 formed with a self-line on the sidewall of the gate electrode 9. A trench 4 is provided in a self-aligned silicon substrate 1, an oxide film 5 is provided on a part of the side surface and the bottom of the trench 4, and the trench 4 provided with the oxide film 5 is buried, and a p-type source/drain region 3 is provided. A P-channel MIS field effect transistor is formed having a structure in which a conductive film 7 is provided in contact with the side surface of the p-channel MIS field effect transistor. Here, the buried conductive film 7 is only in contact with the p-type source train region 3 and must be separated from the n-type silicon substrate 1, so the trench 4 for forming the source train region is formed in two steps, and the trench The desired structure is obtained by forming an oxide film 5 on a part of the side surface and the bottom surface of the cell line 9 (the manufacturing method will be described in detail later). Since the source train region including the shallow, low concentration p-type source/drain region 3 can be formed with minimal lateral diffusion under the gate electrode 9, high integration due to the miniaturization of the gate length can be achieved. Since the length can be miniaturized and the source/drain region made of the low resistance conductive film 7 without a relatively high resistance high concentration impurity region can be formed, the transfer conductance can be increased and the source/drain region made of the conductive film 7 can be buried. Since it can be formed on the oxidized film 5, the capacitance of the source and drain regions can be reduced, thereby increasing the speed.
By forming a source/drain region surrounded by an oxide film 5 in which conductive films 7 other than those in contact with the lightly doped p-type source/drain region 3 are buried, the breakdown voltage of the junction can be increased and performance can be improved.

FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention, where 1 to 5.7 to 13 are the same as in FIG. 1, and 14 is a source/drain region and an element isolation region formed. trench shown.

In the figure, the element isolation region is formed using the so-called trench element isolation method, and a low concentration p-type source train region 3 is provided only on the gate side, and is in contact with the buried conductive film 7. In addition to the same effects as the first embodiment, this embodiment has the same structure as the first embodiment except for the high integration due to the absence of the bird's beak and various problems caused by the bird's beak. It is possible to improve the deterioration of the characteristics of

FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention, in which the present invention is made of 5OI (Si)
1.3.4.7 to 13 are the same as in Figure 1, 15 is an n-type recrystallized silicon substrate, and 16 is an insulating isolation oxide film on a silicon substrate. 9 In the figure, a lightly doped p-type source/drain region 3 is provided on an n-type recrystallized silicon substrate 15 whose side and bottom surfaces are surrounded by an oxide film 16. The structure is substantially the same as that of the first embodiment except that a low-resistance source/drain region made of a buried conductive film is formed in contact with the side surface of the type source/drain region 3. In the present invention, it is possible to achieve the same effects as in the first embodiment and the second embodiment. ) to (e). However, only the manufacturing method for forming the MIS field effect transistor of the present invention will be described here, and the manufacturing method for forming various elements (other transistors, resistors, capacitors, etc.) mounted on general semiconductor integrated circuits will be described. 9 Figure 4 (a) An n-type channel stopper region 2 and a field oxide film 6 having a thickness of approximately 600 mm are formed on an n-type silicon substrate 1 by applying a conventional technique.9 Figure 4 (b) ) Next, about 181 gate oxide films 8 are grown.

Next, a polycrystalline silicon film containing impurities with a thickness of about 300 nm is grown. Next, an oxide film 17 of about 20 nm is grown. Next, a first nitride film 18 having a thickness of about 301 is grown. Next, using a conventional photolithography technique and using a resist (not shown) as a mask layer, the nitride film 18, oxide film 17, and polycrystalline silicon film are selectively etched to form the gate electrode 9. Then the resist is removed. Next, using a resist (not shown), a gate electrode 9 including a nitride film 18 and an oxide film 17, and a field oxide film 6 as mask layers, boron ions are implanted to form p-type sources and drains using a normal photolithography technique. 9 to form region 3. The resist is then removed.

Figure 4 (C) Next, a chemical vapor deposition oxide film having a thickness of about 250 mm is grown.

Next, the chemical vapor grown oxide film is circumferentially dry etched to form a sidewall oxide film 10 on the sidewalls of the gate electrode 9. (
Gate oxide film 8 is also etched by the overetching. ) Next, the exposed silicon substrate 1 is etched by about 100 nm (see FIG. 4(d)). Then, a second nitride film 19 of about 100 nm is grown. Next, the nitride film 19 is anisotropically dry etched to form the nitride film 19 on the exposed sidewall of the silicon substrate 1. (
The nitride film 18 is also etched at the same time. ) Next, the exposed silicon substrate 1 is etched again by about 400 mm to form a trench 4.

FIG. 4(e) Next, thermal oxidation is performed to grow an oxide film 5 with a thickness of about 100%.
Next, the nitride film 19 is etched away using boiled phosphoric acid. Next, a tungsten silicide film is grown. Then, by anisotropic dry etching, the trench 4 is filled with a buried tungsten silicide film 7 which will become the source/drain region. A P-channel MIS field effect transistor is completed by growing the (PSG) film 12, activating the impurity diffusion region by high-temperature heat treatment, controlling the depth, forming an electrode contact window, forming the A1 wiring 13, etc.

As shown in the embodiments above, according to the MIS field effect transistor of the present invention, all the constituent regions can be formed as self-aligned lines, including a shallow low-concentration impurity region with minimal lateral diffusion under the gate electrode. Since the source/drain region can be formed, the gate length can be made finer, resulting in higher integration.Also, the gate length can be made finer, and the source/drain region can be made of a low-resistance conductive film that does not have a relatively high-resistance, high-concentration impurity region. The transfer conductance can be increased because the conductive film can be formed on the insulating film, and the capacitance of the source and drain regions can be reduced because the source and drain regions made of the conductive film can be formed on the insulating film. By forming a source/drain region in which the conductive film other than the region in contact with the low concentration impurity region is surrounded by an insulating film, the withstand voltage of the junction can be increased, thereby making it possible to improve performance.

In the above embodiments, a P-channel MIS field effect transistor has been described, but instead of a low concentration p-type source/drain region formed directly under the sidewall oxide film, a Schottky film in contact with a metal film or metal silicide film is used. The present invention can also be used in an N-channel MIS field effect transistor by forming an n-type source/drain region (having a carrier concentration of about 1020 cm-" or more) with a high concentration that does not form a barrier. However, the present invention can be used in an N-channel MIS field effect transistor. Since source/drain regions cannot be formed, it is not possible to increase the breakdown voltage of the junction.

[Effects of the Invention] As described above, according to the present invention, in a MIS field effect transistor, it is possible to form a source train region including a shallow, low concentration impurity region that suppresses lateral diffusion under the gate electrode. The gate length can be made finer, the source and drain regions can be formed with a low resistance conductive film, increasing the transfer conductance, and the source and drain regions made of a conductive film can be formed on an insulating film. Because it can be formed, it is possible to increase the speed by reducing the capacitance of the source train region, and because it is possible to form the source drain region in which only the lightly doped impurity region is in contact with the semiconductor substrate, it is possible to increase the junction breakdown voltage, which can improve performance. MIS enables the formation of highly integrated, high-speed, and high-performance semiconductor integrated circuits.
A field effect transistor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view of the MIS field effect transistor of the present invention.
FIG. 3 is a schematic side sectional view of a second embodiment of a field effect transistor; FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention; FIGS.
e) is a process sectional view of an embodiment of the manufacturing method for an MIS field effect transistor of the present invention, and FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor. In the figure, 1 is an n-type silicon substrate, 2 is an n-type channel stopper region, 3 is a p-type source/drain region, 4 is a trench for forming the source/drain region, 5 is a buried oxide film, 6 is a field oxide film, 7 8 is a buried conductive film, 8 is a gate oxide film, 9 is a gate electrode, 10 is a sidewall oxide film, 11 is an oxide film for impurity blocking, 12 is a phosphosilicate glass (PSG) film, 13 is an A1 wiring, 14 is a source/drain region and a trench for forming an element isolation region; 15 is an n-type recrystallized silicon substrate; 16 is an insulating isolation oxide film on the silicon substrate; 9;

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and an equidistant distance from the semiconductor substrate at both ends of the gate electrode. a source drain region of opposite conductivity type provided in a width, a trench provided in the semiconductor substrate equidistantly apart from both ends of the gate electrode, and an insulating material provided on a part of the side surface and bottom surface of the trench. A MIS field effect transistor comprising: a conductive film that fills a trench provided with the insulating film and is in contact with a side surface of the source/drain region. (2) The MIS field effect transistor according to claim 1, wherein the semiconductor substrate is made of a recrystallized silicon substrate.