JPH04360539A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the manufacturing method of an SOI type lateral transistor wherein the base width is reduced and a leading-out electrode from the reduced base is formed. CONSTITUTION:After a silicon nitride film 6 and a silicon oxide film 8 having a specified shape are formed on an n-type collector layer 4 on an insulative substrate 2, a p<+> type base layer 10 is formed by implanting ions through the nitride film. An n<+> type emitter layer 14 is formed by ion implantation using the silicon oxide film 8 and its side wall 12 as masks. After that, the side wall 12 and the silicon nitride film 6 on the p<+> type base layer 10 are selectively eliminated, and a p<+> type base leading-out electrode 18 composed of a polycrystalline silicon layer is formed on the exposed p <+> type base layer 10.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing semiconductor devices, and in particular to a method for manufacturing semiconductor devices, particularly SOI (Silicon On Insulator).
The present invention relates to a method of manufacturing a lateral bipolar transistor having a structure (ater).

0002

[Background Art] Improvements in SOI substrate manufacturing technology have made it possible to create active parts of silicon on the insulating layer on the order of submicrons, resulting in the creation of MOS transistors with high mutual conductance and suppressed short channel effects. Research is being conducted to However, since MOS transistors alone do not have the ability to drive loads, BiCMOS incorporating bipolar transistors is desired.

However, when developing BiCMOS on an SOI substrate, conventional vertical bipolar transistors
It is difficult to manufacture due to its structure, such as the difficulty of forming a collector buried layer in a submicron active layer. Therefore, it has been considered to form a lateral bipolar transistor using an SOI substrate.

0004

[Problems to be Solved by the Invention] However, in conventional SOI-structured lateral bipolar transistors, the base width is determined by the accuracy of mask alignment, so it is difficult to reduce the base width.
It was difficult to reduce the base resistance, and therefore it was not possible to operate at a sufficiently high speed. Therefore, the present invention reduces the base width and forms a base electrode drawn out from the reduced base, thereby improving the speed of SO.
An object of the present invention is to provide a method for manufacturing an I-structure lateral bipolar transistor.

[0005]

[Means for Solving the Problems] The above-mentioned problems include the steps of forming a collector layer made of a first conductivity type semiconductor layer on an insulating substrate, and sequentially forming a nitride film and an oxide film on the collector layer. After patterning the oxide film into a predetermined shape, impurities of a second conductivity type are introduced into the collector layer through the nitride film by ion implantation using the oxide film as a mask to form a base layer. a step of forming a sidewall made of a polycrystalline silicon layer on the side surface of the oxide film; and after selectively etching and removing the nitride film, by ion implantation using the oxide film and the sidewall as a mask, After forming an emitter layer by introducing impurities of a first conductivity type into the base layer and removing the sidewalls by etching, a thermal oxide film is formed on the emitter layer by selective oxidation using the nitride film as a mask. and forming a base electrode on the exposed base layer after selectively etching and removing the nitride film on the base layer using the oxide film and the thermal oxide film as a mask. This is achieved by a method of manufacturing a semiconductor device characterized by the following.

[0006] Furthermore, the above-mentioned problem is solved by the first
A step of forming a collector layer made of a conductive type semiconductor layer, forming an oxide film on the collector layer, patterning the oxide film into a predetermined shape, and then forming a sidewall made of a nitride film on the side surface of the oxide film. forming an emitter layer by introducing impurities of a first conductivity type into the collector layer by ion implantation using the oxide film and the sidewalls as masks; forming a thermal oxide film on the emitter layer by selective oxidation using a mask; selectively etching away the sidewall using the oxide film and the thermal oxide film as a mask; forming a base layer by introducing impurities of a first conductivity type into the collector layer in contact with the emitter layer by ion implantation using a thermal oxide film as a mask; and forming a base electrode on the base layer. This is achieved by a method of manufacturing a semiconductor device characterized by having the following.

[0007] Furthermore, the above problem is solved by the first
A step of forming a collector layer made of a conductive type semiconductor layer, forming an oxide film on the collector layer, patterning the oxide film into a predetermined shape, and then forming a sidewall made of a nitride film on the side surface of the oxide film. a step of forming a polycrystalline layer by introducing silicon into the collector layer to make it amorphous by ion implantation using the oxide film and the sidewall as a mask, and then forming a polycrystalline layer by annealing; A step of introducing a second conductivity type impurity into the polycrystalline layer by ion implantation using the sidewall as a mask, and then laterally diffusing it until it reaches under the oxide film to form a base layer; A step of introducing an impurity of a first conductivity type into the polycrystalline layer by ion implantation using the film and the sidewall as a mask to form an emitter layer, and a step of selective oxidation using the oxide film and the sidewall as a mask. , forming a thermal oxide film on the emitter layer, selectively etching away the sidewall using the oxide film and the thermal oxide film as a mask, and then forming a base electrode on the exposed base layer. This is achieved by a method of manufacturing a semiconductor device characterized by comprising the steps of:

[0008]

[Operation] In the present invention, the width of the base layer sandwiched between the collector layer and the emitter layer is defined by the horizontal thickness of the sidewall formed on the sidewall of the oxide film, so it can be controlled to 100 nm or less. . In addition, since only the surface of the p+ type base layer is exposed and the base electrode is deposited on it, ohmic contact with the base layer is good and a base electrode with a desired size can be easily formed. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on illustrative embodiments. FIG. 1 is a process diagram for explaining a method of manufacturing a lateral bipolar transistor having an SOI structure according to a first embodiment of the present invention. For example, on a silicon substrate with a thickness of 500 mm
An n-type collector layer 4 made of an n-type silicon layer with a thickness of 300 nm is formed on an insulating substrate 2 on which a silicon oxide film with a thickness of 300 nm is provided. Then, on this n-type collector layer 4, CVD (Chemical Vapor Deposits) is applied.
After sequentially depositing a silicon nitride film (Si3 N4 film) 6 with a thickness of 50 nm and a silicon oxide film (SiO2 film) 8 with a thickness of 200 nm using the silicon oxide film 8, silicon nitride film 6, and The mold collector layer 4 is patterned into a predetermined shape (see FIG. 1(a)).

[0010] Next, RIE (Reactive Io
After patterning the silicon oxide film 8 into a predetermined shape using the n-etching method, B+ (boron) ions are implanted through the nitride film using the silicon oxide film 8 as a mask. That is, by setting the ion implantation conditions to a dose of 5 x 1013 cm-2 and an acceleration voltage of 60 keV, B +
Ions are introduced into the n-type collector layer 4 to form a p + -type base layer 10 (see FIG. 1(b)).

Next, using the CVD method, the entire surface is coated with a thickness of 10
After depositing a 0 nm polycrystalline silicon layer, this polycrystalline silicon layer is removed by RIE method, and a silicon oxide film 8 is formed.
Leave it only on the side wall. In this way, a sidewall 12 made of a polycrystalline silicon layer is formed on the sidewall of the silicon oxide film 8. Subsequently, the silicon nitride film 6 is selectively etched away using the silicon oxide film 8 and the sidewall 12 as a mask. Then, using the silicon oxide film 8 and the sidewalls 12 as masks, As+ (arsenic) ions are implanted, and the As+ ions are introduced into the p+ type base layer 10 to form the n+ type emitter layer 14. Note that the conditions for ion implantation at this time are a dose of 5×10
15 cm-2 and an acceleration voltage of 200 keV (Fig. 1
(see (c)).

Next, the sidewall 12 is removed using a wet etching method to expose the silicon nitride film 6 on the p+ type base layer 10. Then, using this silicon nitride film 6 as a mask, selective wet oxidation is performed to remove the exposed side surfaces of the n-type collector layer 4 and the n+-type emitter layer 1.
A thermal oxide film 16 with a thickness of 100 nm is formed on 4 (Fig. 2
(see (a)).

Next, only the silicon nitride film 6 is removed using wet etching to expose the surface of the p+ type base layer 10. And this exposed p+ type base layer 1
0, a p+ type base lead electrode 18 made of a polycrystalline silicon layer is formed. Subsequently, after contact windows are opened in the silicon oxide film 8 and silicon nitride film 6 on the n-type collector layer 4 and in the thermal oxide film 16 on the n + -type emitter layer 14, an Al (aluminum) layer is deposited on the entire surface. . Then, this Al layer is patterned into a predetermined shape, and a collector electrode 20 is placed on the n-type collector layer 4, the n+-type emitter layer 14, and the p+-type base extraction electrode 18, respectively.
A base electrode 22 and an emitter electrode 24 are formed (Fig. 2
(see (b)).

As described above, according to the first embodiment, the p+ type sandwiched between the n type collector layer 4 and the n+ type emitter layer 14
The width of the mold base layer 10 is defined by the horizontal thickness of a sidewall 12 made of a polycrystalline silicon layer formed on the sidewall of the silicon oxide film 8. Therefore, p+ type base layer 1
The zero width can be controlled to 100 nm or less. Also,
Only the silicon nitride film 6 on the p+ type base layer 10 is selectively removed, and a p+ type layer is deposited on the exposed p+ type base layer 10.
Since the mold base extraction electrode 18 is deposited and formed, p+
The p+ type base extraction electrode 18 having good ohmic contact with the mold base layer 10 and having a desired size can be easily formed.

Next, the SOI according to the second embodiment of the present invention
Figure 2 shows the manufacturing method of a lateral bipolar transistor with the structure
This will be explained using the process diagram shown below. Note that the same components as those of the lateral bipolar transistor according to the first embodiment are given the same reference numerals, and a description thereof will be omitted. An n-type collector layer 4 is formed on an insulating substrate 2. After depositing a silicon oxide film 8a with a thickness of 200 nm on this n-type collector layer 4 using the CVD method, these silicon oxide films 8a are deposited using the CVD method.
The a- and n-type collector layers 4 are patterned into a predetermined shape. Furthermore, the silicon oxide film 8a is patterned into a predetermined shape using the RIE method (see FIG. 3(a)).

Next, using the CVD method, the entire surface is coated with a thickness of 10
After depositing a 0 nm silicon nitride film, this silicon nitride film is removed by RIE, leaving only the sidewalls of the silicon oxide film 8a. In this way, a sidewall 26 made of a silicon nitride film is formed on the sidewall of the silicon oxide film 8a. Subsequently, using the silicon oxide film 8a and the sidewall 26 as a mask, a dose of 5×10 14 cm −2 was applied.
As+ ions are implanted under the condition of an acceleration voltage of 200 keV, and the As+ ions are introduced into the n-type collector layer 4 to form the n+-type emitter layer 14a (see FIG. 3).
b)).

Next, wet oxidation is performed to remove the exposed n
A thermal oxide film 16a having a thickness of 100 nm is formed on the side surface of the type collector layer 4 and on the n+ type emitter layer 14a. At this time, since the sidewall 26 made of a silicon nitride film serves as a mask against thermal oxidation, no oxide film is formed on the surface of the n-type collector layer 4 under the sidewall 26 (see FIG. 3(c)). .

Next, using the silicon oxide film 8a and the thermal oxide film 16a as masks, the sidewall 26 is selectively etched away to expose a portion of the surface of the n-type collector layer 4 in contact with the n+-type emitter layer 14a. Then, using the silicon oxide film 8a and the thermal oxide film 16a as a mask,
B+ ions are implanted into the n-type collector layer 4 whose surface is exposed. The ion implantation conditions at this time are set to a dose of 5×10 13 cm −2 and an acceleration voltage of 60 keV. Then, an annealing treatment is performed at a temperature of 1000° C. for 5 seconds to form a p+ type base layer 10a sandwiched between the n type collector layer 4 and the n+ type emitter layer 14a. Subsequently, after depositing a p+ type polycrystalline silicon layer on the entire surface, the exposed p+ type base layer 10 is patterned into a predetermined shape.
A p+ type base extraction electrode 18 is formed on a (FIG. 4
(see (a)).

Next, the silicon oxide film 8a on the n-type collector layer 4 and the thermal oxide film 1 on the n+ type emitter layer 14a are
After opening contact windows in each of 6a, the entire surface is coated with Al.
This Al layer is patterned into a predetermined shape to form a n
A collector electrode 20, a base electrode 22, and an emitter electrode 24 are formed on the type collector layer 4, the p+ type base extraction electrode 18, and the n+ type emitter layer 14a, respectively (see FIG. 4(b)).

As described above, according to the second embodiment, the p type sandwiched between the n type collector layer 4 and the n+ type emitter layer 14a
The width of the + type base layer 10a is defined by the horizontal thickness of a sidewall 26 made of a silicon nitride film formed on the sidewall of the silicon oxide film 8a. Therefore, similarly to the first embodiment, the width of the p+ type base layer 10a can be controlled to 100 nm or less.

Further, as in the case of the first embodiment, it is possible to easily form the p+ type base extraction electrode 18 having good ohmic contact with the p+ type base layer 10a and having a desired size. . Next, a method for manufacturing a lateral bipolar transistor having an SOI structure according to a third embodiment of the present invention will be explained using the process diagram shown in FIG. Note that the same components as those of the lateral bipolar transistors according to the first and second embodiments are given the same reference numerals and explanations will be omitted.

An n-type collector layer 4 is formed on the insulating substrate 2. A silicon oxide film 8b having a thickness of 200 nm is deposited on this n-type collector layer 4 using the CVD method, and then the silicon oxide film 8b is patterned into a predetermined shape using the RIE method. Subsequently, after depositing a silicon nitride film with a thickness of 150 nm on the entire surface using the CVD method, R
This silicon nitride film is removed by the IE method, leaving only the sidewalls of the silicon oxide film 8b. In this way, a sidewall 26a made of a silicon nitride film is formed on the sidewall of the silicon oxide film 8b.

Next, using the silicon oxide film 8b and the sidewall 26a as a mask, an acceleration voltage of 100 KeV is applied.
Si+ (silicon) ions are implanted at a dose of 3×10 16 cm −2 to make the n-type collector layer 4 amorphous. Then, an annealing treatment is performed at a temperature of 600°C to form a polycrystalline silicon layer 9 (FIG. 5(
a)).

Furthermore, using the silicon oxide film 8b and sidewall 26a as a mask again, an acceleration voltage of 60 KeV is applied.
B+ ions are implanted at a dose of 5×10 13 cm −2 . Then, at a temperature of 900° C. and a time of 30 minutes, the B impurity is diffused in the lateral direction until it reaches the n-type collector layer 4 under the silicon oxide film 8b, forming a p+ type base layer 10b under the sidewall 26a ( Figure 5 (
b)). Note that the lateral diffusion of the B impurity does not need to reach below the silicon oxide film 8b in this step;
Taking into consideration the diffusion caused by heat treatment etc. in the subsequent steps, the p+ type base layer 10b is finally formed under the sidewall 26a.
It is enough.

Next, using the silicon oxide film 8b and the sidewall 26a as a mask, a dose of 5×10 14c is applied.
As+ ions were implanted into the polycrystalline silicon layer 9 under the conditions of m-2 and acceleration voltage of 200 keV, and further at a temperature of 6.
An n+ type emitter layer 14b is formed by annealing at 00° C. for 30 minutes (see FIG. 5(c)). In addition,
Since the As impurity in the polycrystalline silicon layer 9 is laterally diffused into the p+ type base layer 10b by heat treatment etc. thereafter, the interface between the p+ type base layer 10b and the n+ type emitter layer 14b is formed by a single crystal silicon layer. It is formed in the single crystal silicon layer rather than at the boundary between the polycrystalline silicon layer and the polycrystalline silicon layer.

Next, wet oxidation is performed to remove the exposed n
A thermal oxide film 16b having a thickness of 150 nm is formed on the + type emitter layer 14b (see FIG. 6(a)). At this time, since the thermal oxidation progresses to below the sidewall 26a, the thermal oxidation film 16b is formed even on the interface between the p+ type base layer 10b and the n+ type emitter layer 14b. Then,
After selectively etching and removing the sidewall 26a using the silicon oxide film 8b and the thermal oxide film 16b as masks, a silicon nitride film 28 with a thickness of 100 nm is deposited on the entire surface. After further coating the entire surface with resist 30, it is patterned into the shape of the element region (see FIG. 6(b)).

Next, this patterned resist 3
0 as a mask, silicon nitride film 28, silicon oxide film 8b, thermal oxide film 16b, n-type collector layer 4 and n+
The mold emitter layer 14b is etched until it reaches the surface of the insulating substrate 2. Then, wet oxidation is performed to expose the exposed n
A thermal oxide film 16c with a thickness of 100 nm is formed on the side surfaces of the type collector layer 4 and the n+ type emitter layer 14b (see FIG. 6).
c).

Next, the silicon nitride film 28 is removed by etching to expose the surface of the p+ type base layer 10b. After depositing a polycrystalline silicon layer over the entire surface and implanting B+ ions into the polycrystalline silicon layer, the exposed p+ type base layer 1 is patterned into a predetermined shape.
A p+ type base extraction electrode 18 is formed on 0b (see FIG. 7(a)).

Next, after forming an interlayer insulating film 32 made of a silicon oxide film over the entire surface, the interlayer insulating film 32 and silicon oxide film 8b on the n-type collector layer 4 are etched to form an opening. Then, P+ ions are implanted into the n-type collector layer 4 through this opening to form an n+-type collector extraction region 34 (see FIG. 7(b)). Note that at this time, an opening may also be formed on the n+ type emitter layer 14b to similarly form an n+ type emitter extraction region.

Next, after contact windows are opened on the p+ type base extraction electrode 18 and the n+ type emitter layer 14b, an Al layer is deposited on the n+ type collector extraction region 34 and the p+ type base extraction electrode 18. A collector electrode 20, a base electrode 22, and an emitter electrode 24 are formed on the n+ type emitter layer 14b, respectively. As described above, according to the third embodiment, the p+ type base layer 1
The 0b width is basically determined by double diffusion of B impurities and As impurities from the polycrystalline silicon layer 9 in the lateral direction, and therefore can be controlled to be sufficiently small. however,
Although the horizontal thickness of the sidewall 26a formed on the sidewall of the silicon oxide film 8b is determined by the need to draw out the contact from the p+ type base layer 10b, the thickness of the sidewall 26a formed on the sidewall of the silicon oxide film 8b is still limited. alike,
The width of the p+ type base layer 10b can be controlled to 100 nm or less.

Furthermore, unlike the first and second embodiments, it is possible to easily form the p+ type base extraction electrode 18 having good ohmic contact with the p+ type base layer 10b and having a desired size. The same is true. Furthermore, in this embodiment, the interface between the p+ type base layer 10b and the n+ type emitter layer 14b is formed in the single crystal silicon layer, but most of the n+ type emitter layer 14b is doped with impurities at a high concentration. Since it is made of a polycrystalline silicon layer, it also has the effect of increasing the operating speed, and can contribute to further speeding up.

[0032]

As described above, according to the present invention, the width of the base layer sandwiched between the collector layer and the emitter layer is defined by the horizontal thickness of the sidewall formed on the sidewall of the oxide film. It can be controlled to 100 nm or less. Further, since only the surface of the p+ type base layer is exposed and the base electrode is deposited thereon, ohmic contact with the base layer is good, and a base electrode of a desired size can be easily formed.

As a result, even in the SOI-structured lateral bipolar transistor, the base width can be reduced, and a base electrode drawn out from the reduced base can be easily formed, so that high speed performance can be improved. Therefore, it is possible to realize BiCMOS in which a MOS transistor and a bipolar transistor are mounted together on an SOI substrate.

[Brief explanation of the drawing]

FIG. 1 is a process diagram (part 1) for explaining a method for manufacturing a lateral bipolar transistor having an SOI structure according to a first embodiment of the present invention.

FIG. 2 is a process diagram (part 2) for explaining the method for manufacturing the SOI-structured lateral bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a process diagram (part 1) for explaining a method for manufacturing a lateral bipolar transistor with an SOI structure according to a second embodiment of the present invention.

FIG. 4 is a process diagram (part 2) for explaining a method of manufacturing a lateral bipolar transistor having an SOI structure according to a second embodiment of the present invention.

FIG. 5 is a process diagram (part 1) for explaining a method of manufacturing a lateral bipolar transistor having an SOI structure according to a third embodiment of the present invention.

FIG. 6 is a process diagram (part 2) for explaining a method for manufacturing a lateral bipolar transistor having an SOI structure according to a third embodiment of the present invention.

FIG. 7 is a process diagram (Part 3) for explaining a method for manufacturing a lateral bipolar transistor having an SOI structure according to a third embodiment of the present invention.

[Explanation of symbols]

2...Insulating substrate 4...N-type collector layer 6...Silicon nitride film 8, 8a, 8b...Silicon oxide film 9...Polycrystalline silicon layer 10, 10a, 10b...P+ type base layer 12...Side wall 14, 14a, 14b ...n+ type emitter layer 16, 16
a, 16b, 16c...thermal oxide film 18...p+ type base extraction electrode 20 collector electrode 22...base electrode 24...emitter electrode 26, 26a...side wall 28...silicon nitride film 30...resist 32...interlayer insulating film 34...n+ type Collector drawer area

Claims (3)

[Claims] 1. Forming a collector layer made of a first conductivity type semiconductor layer on an insulating substrate, forming a nitride film and an oxide film in order on the collector layer, and shaping the oxide film into a predetermined shape. After patterning, a step of introducing a second conductivity type impurity into the collector layer through the nitride film by ion implantation using the oxide film as a mask to form a base layer; After forming a sidewall made of a polycrystalline silicon layer and selectively etching and removing the nitride film, impurities of the first conductivity type are implanted into the oxide film and the sidewall by ion implantation using the oxide film and the sidewall as a mask. a step of introducing the oxide into the base layer to form an emitter layer; a step of etching away the sidewalls and then forming a thermal oxide film on the emitter layer by selective oxidation using the nitride film as a mask; selectively etching away the nitride film on the base layer using the film and the thermal oxide film as a mask, and then forming a base electrode on the exposed base layer. Production method. 2. Forming a collector layer made of a first conductivity type semiconductor layer on an insulating substrate, forming an oxide film on the collector layer, and patterning the oxide film into a predetermined shape. , a step of forming a sidewall made of a nitride film on a side surface of the oxide film, and an ion implantation using the oxide film and the sidewall as a mask, introduce impurities of a first conductivity type into the collector layer to form an emitter layer. forming a thermal oxide film on the emitter layer by selective oxidation using the nitride film and the oxide film as masks; and selecting the sidewalls using the oxide film and the thermal oxide film as masks. and a step of introducing impurities of a first conductivity type into the collector layer in contact with the emitter layer to form a base layer by ion implantation using the oxide film and the thermal oxide film as masks. . A method of manufacturing a semiconductor device, comprising the steps of: forming a base electrode on the base layer. 3. Forming a collector layer made of a first conductivity type semiconductor layer on an insulating substrate, forming an oxide film on the collector layer, and patterning the oxide film into a predetermined shape. , forming a sidewall made of a nitride film on the side surface of the oxide film, and introducing silicon into the collector layer to make it amorphous by ion implantation using the oxide film and the sidewall as a mask, and then by annealing. After forming a polycrystalline layer and introducing impurities of the second conductivity type into the polycrystalline layer by ion implantation using the oxide film and the sidewalls as masks, the impurity is introduced laterally until it reaches under the oxide film. a step of forming a base layer by diffusion; a step of introducing an impurity of a first conductivity type into the polycrystalline layer by ion implantation using the oxide film and the sidewall as a mask to form an emitter layer; forming a thermal oxide film on the emitter layer by selective oxidation using the oxide film and the sidewall as a mask, and selectively etching and removing the sidewall using the oxide film and the thermal oxide film as a mask; ,
A method for manufacturing a semiconductor device, comprising the step of forming a base electrode on the exposed base layer.