JPH043457A - Formation of wiring for active layer laminated element - Google Patents

Abstract

PURPOSE:To simplify and shorten manufacturing steps by forming contact holes for forming vertical wirings having different depths of holes, depositing a silicon thin film on the entire surface by an LPCVD method, anisotropically etching until the film except the sidewall of the hole is removed, and selectively growing tungsten by CVD. CONSTITUTION:Contact holes for forming vertical wirings having 1.5mum of a hole size are formed. A contact hole having 1.6mum of a depth at a position of a source 4 of a lower layer transistor, a contact hole having 0.7mum of a depth at a position of a gate wiring 5a, and the last contact hole having 0.5mum of depth at a position of a source 8 of an upper layer transistor are sequentially formed. Then, a silicon thin film 15 having 0.1mum of thickness is deposited on the entire surface by an LPCVD. Thereafter, the film 15 is anisotropically etched, and the film 15 except the sidewall of the hole is removed. Subsequently, tungsten is grown by CVD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an active layer stacked device formed by stacking active layers, and particularly relates to a wiring forming method.

[Conventional technology]

Conventionally, wiring for an element in which two active layers are laminated has been formed as follows. FIGS. 2(a) to 2(e) are cross-sectional views schematically showing a method for forming wiring of an active multilayer device manufactured by a conventional technique in the order of steps.

First, a drain 3 . Source 4. After forming a lower transistor consisting of a gate 5° and a gate wiring 5a, an oxide film 6, which is a first insulating film, is formed over the entire surface. Next, a planarizing agent is applied, and the surface of the oxide film 6 is planarized by constant-speed etching back of the planarizing agent and the oxide film 6, and then a single crystal silicon film and a polycrystalline silicon film are formed on the oxide M6. Then, using these films, train 7, source 8° gate 9
．． Then, an upper layer transistor consisting of a gate wiring 9a is formed, and an oxide film 10, which is a second insulating film, is formed on the entire surface. As a result, a device having the shape shown in FIG. 2(a) is obtained.

Note that since contact holes cannot be formed in these portions of the gates 9.5 of the upper and lower transistors, the oxide film 6.5 is formed from the gate 9.5. Contact holes are formed on gate wiring 9a and gate wiring 5a extending on element isolation oxide film 2. Furthermore, these gate wiring 9a and gate wiring 5a may be used as independent wiring.

Next, as shown in FIG. 2(b), contact holes for forming vertical wiring are formed in the oxide films 10 and 6 on the source 4 of the lower transistor by an exposure process using a photoresist and a dry etching process. .

Next, tungsten is deposited in this contact hole by CVD.
tungsten to form columnar tungsten 11. After that, a nitride film 12 is formed on the entire surface, and the columnar tungsten 11
The purpose of this overlying nitride film 12 is to prevent the columnar tungsten 11 from being etched during acid treatment during the subsequent photoresist treatment step for forming contact holes. Next, as shown in Figure 2(c),
A contact hole for forming a vertical wiring is formed in the oxide film 10.6 on the gate wiring 5a by an exposure process using a photoresist and a dry etching process.

Next, CVD of tungsten is applied in this contact hole.
The columnar tungsten 11a is formed by embedding using the D method.

Thereafter, a nitride film 13 is formed on the entire surface to cover the columnar tungsten lla. Next, as shown in FIG. 2(d), contact holes for forming vertical interconnections are formed in the oxide film 10 on the source 8 of the upper layer transistor by an exposure process using a photoresist and a dry etching process.

Subsequently, tungsten is buried in this contact hole by the CVD method to form columnar tungsten 11b. Finally, as shown in FIG. 2(e), the nitride film 13.
12 is removed by etching, and columnar tungsten 11. ll
After exposing a and llb, aluminum was deposited and patterned to form the wiring 14.

[Problem to be solved by the invention]

In the conventional example, source 4.5. is used for convenience. and gate wiring 5a
We have explained the formation of three types of contact holes for the drain 3 of the lower layer transistor in the conventional multilayer device.
．． The source 4, the gate wiring 5a of the lower transistor,
Drain 7, source 8 of the upper layer transistor. Three types of contact holes are formed and the columnar tungsten 11. It is necessary to form lla and llb separately. For this reason, the manufacturing process becomes long and problems with device performance increase accordingly.

[Means to solve the problem]

The wiring formation method for an active layer stacked element of the present invention includes the steps of forming vertical wiring of an active layer stacked element formed by stacking active layers.
Contact holes for forming vertical wiring with different hole depths are formed by etching several times, and a silicon thin film is applied over the entire surface using LPC.
The method includes the steps of depositing by VD method, performing anisotropic etching until the silicon thin film other than the side walls of the contact hole is removed, and burying tungsten in the contact hole by selective tungsten CVD growth.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are schematic cross-sectional views in the order of manufacturing steps for explaining one embodiment of the present invention. In this embodiment, the first. A silicon oxide film was used as the second insulating film.

First, a film with a thickness of 0.00 mm is deposited on a silicon substrate 1 by the LOCO3 method.
After forming the element isolation oxide film 2 with a thickness of 8 μm, a gate 5 made of polycrystalline silicon with a thickness of 0.5 μm is formed via the gate oxide film. Then, a gate 5a made of polycrystalline silicon with a film thickness of 0.5 μm is formed extending from the gate 5 (or as an independent wiring) on the element isolation oxide film 2, and then impurities are introduced to connect the drain 3 and the gate 5a. A source 4 is formed and a lower layer transistor is formed.

Next, a 12 μm thick oxide film 6 made of a silicon oxide film, which is a first insulating film, is formed on the entire surface. After that, the surface of the oxide film 6 is flattened by spin coating a polystyrene solution and isostatic processing and quenching of the polystyrene and silicon oxide films, and the thickness of the oxide film 6 is reduced to 0.2 μm over the contact formation position of the gate wiring 5a. so that it becomes

Next, a film thickness of 0 is applied to the upper layer transistor formation region on the oxide film 6.
．． After depositing a 5 μm polycrystalline silicon film and converting it into a single crystal silicon film using a method such as laser annealing, a gate made of polycrystalline silicon with a thickness of 0.5 μm is placed on top of this via a gate oxide film. At the same time, a gate wiring 9a made of polycrystalline silicon with a film thickness of 0.5 μm (to be extended from the gate 9 or to serve as an independent wiring) is formed on the oxide film 6, and then the above-mentioned single crystal Impurities are introduced into the silicon film thus formed to form a drain 7 and a source 8, thereby forming an upper layer transistor.

Subsequently, an oxide film 10 made of a silicon oxide film and having a thickness of 0.5 μm, which is a second insulating film, is deposited on the entire surface to obtain the structure shown in FIG. 1(a).

Next, a contact hole for forming vertical interconnections with a hole size of 1.5 μm is formed. First, the depth of the source 4 (or drain 3) of the lower layer transistor is 16 μm.
The first contact hole has a depth of 0.7 μm at the position of the gate wiring 5a (of the lower layer transistor), and after M, the contact hole has a depth of 0.7 μm at the position of the source 8 (or drain 7, or gate wiring 9a) of the upper layer transistor. 5μ
Contact holes of m are sequentially formed by an exposure process using a photoresist and a dry etching process.
Process it into the shape shown in Figure (b).

After that, as shown in Figure 1(c), the film thickness is 0 over the entire surface.
．． A 1 μm silicon thin film 15 is deposited by LPCVD.

Next, as shown in FIG. 1(d), the silicon thin film 15 is anisotropically etched to remove the silicon thin film 15 other than the side walls of the contact hole.

Next, CVD growth of tungsten is performed in an environment at a temperature of 300'C using a mixed gas of WF6 and SiH4 at a mixing ratio of 1:1 with H2 as a carrier gas. Under these conditions, tungsten does not grow on the silicon oxide film, does not erode the silicon film, and is deposited only where the silicon film was present. Therefore, the deposition of tungsten in the contact hole is caused by the thin silicon film 15 on the side wall of the contact hole. Growth progresses by using the bottom silicon film and silicon substrate as generation nuclei.

Columnar tungsten 17.17a in contact hole,
The film thickness is set so that the silicon thin film 15 disappears due to erosion when the contact hole 17b is formed, and the thickness of the silicon film at the bottom of the contact hole and the depth of the junction between the source 4 and the drain 3 are set to be sufficient. By doing so, even if the depths of the contact holes are different, the columnar tungsten 17.17a, 17b can be formed in all the contact holes at the same time, as shown in FIG. 1(e).

Finally, as shown in FIG. 1(f), aluminum is deposited and patterned to form wiring 14.

Note that although silicon oxide films are used as the first and second insulating films in this embodiment, other types of insulating films may be used.

Further, although this embodiment deals with three types of contact holes having different depths, the present invention can be applied even if the number of types of contact holes having different depths increases.

〔Effect of the invention〕

As explained above, in the present invention, columnar tungsten in contact holes with different depths can be formed by tungsten CVD only once, so the manufacturing process can be simplified and shortened, and as a result, the length of the manufacturing process can be reduced. This effectively functions to reduce defects in device performance that increase with the increase in performance.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are schematic cross-sectional views in the order of manufacturing steps for explaining one embodiment of the present invention, and FIGS. 2(a) to (e)
) are schematic cross-sectional views in the order of manufacturing steps showing a conventional method for forming an active layer stacked device. 1... Silicon substrate, 2... Element isolation oxide film, 37
...Drain, 4.8...Source, 5,9...Gate, 5a, 9a...Gate wiring, 6.10...Oxide film, 11, lla, llb, 17.17a, 17b −
・Columnar tungsten, 12.13...Nitride film, 14.
... Wiring, 15... Silicon thin film.

Claims (1)

[Claims] In forming vertical wiring in an active layer stacked device formed by stacking active layers, contact holes for forming vertical wiring with different hole depths are formed by etching several times, and a silicon thin film is formed over the entire surface. LPC
a step of depositing by a VD method; a step of performing anisotropic etching on the silicon thin film until the silicon thin film other than the sidewall of the contact hole is removed; and a step of performing selective CVD growth of tungsten to deposit tungsten in the contact hole. 1. A method for forming wiring for an active multilayer element, comprising the step of embedding.