JPH04337657A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04337657A
JPH04337657A JP3109163A JP10916391A JPH04337657A JP H04337657 A JPH04337657 A JP H04337657A JP 3109163 A JP3109163 A JP 3109163A JP 10916391 A JP10916391 A JP 10916391A JP H04337657 A JPH04337657 A JP H04337657A
Authority
JP
Japan
Prior art keywords
plating layer
plating
lead frame
layer
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3109163A
Other languages
Japanese (ja)
Inventor
Ryoichi Koizumi
小 泉 良 一
Osamu Yoshioka
吉 岡  修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP3109163A priority Critical patent/JPH04337657A/en
Publication of JPH04337657A publication Critical patent/JPH04337657A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable heat resistance of a surface treatment film to be improved by providing an Ni plating layer on an entire surface of a lead frame, a Pd plating layer at an inner-lead part and an outer-lead portion at its upper layer, and further an Au plating layer at a the inner-lead part and the outer-lead part at its upper layer. CONSTITUTION:An Ni plating layer 9 is provided on an entire surface of a lead frame 1. The Ni plating layer 9 is provided for preventing diffusion and corrosion. A Pd or Pd alloy plating layer 15 is provided on an upper layer of the Ni plating layer 9. This Pd or Pd alloy plating layer 15 is provided at an inner-lead part 5 and an outer-lead part 3. An Au plating layer 16 is provided on the Pd or Pd alloy plating layer 15. This Au plating layer 16 is provided at the inner-lead part 5 and the outer-lead part 3, thus enabling heat resistance at the time of assembly of semiconductor to be improved at a low cost.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置用リードフ
レームに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to lead frames for semiconductor devices.

【0002】0002

【従来の技術】半導体装置用リードフレームは、図4に
示すように一般には半導体チップ載置部7、インナーリ
ード部5、アウターリード部3、外枠部2などからなる
2. Description of the Related Art A lead frame for a semiconductor device generally includes a semiconductor chip mounting portion 7, an inner lead portion 5, an outer lead portion 3, an outer frame portion 2, etc., as shown in FIG.

【0003】半導体パッケージの製造方法は、図5に示
すように半導体チップ載置部7上に半導体チップ13を
ボンディングした後、半導体チップの電極部とインナー
リード部5の先端部6のAgめっき層10をAuなどの
極細線(Auワイヤ)12でワイヤボンディング(W/
B)する。この後、モールド樹脂14でモールドされる
。さらに、半導体パッケージをプリント基板上に取り付
ける際の装着性を良くするために、リードフレームの外
枠部2を切った後、アウターリード部3を含む部分には
んだめっき層(Sm−Pb合金めっき層)11を設けて
完成品とする。
As shown in FIG. 5, the method for manufacturing a semiconductor package involves bonding a semiconductor chip 13 onto a semiconductor chip mounting portion 7, and then depositing an Ag plating layer on the electrode portion of the semiconductor chip and the tip portion 6 of the inner lead portion 5. 10 is wire bonded (W/
B) Do. After that, it is molded with mold resin 14. Furthermore, in order to improve the ease of mounting the semiconductor package on a printed circuit board, after cutting the outer frame part 2 of the lead frame, a solder plating layer (Sm-Pb alloy plating layer) is applied to the part including the outer lead part 3. ) 11 to make a finished product.

【0004】しかし、このようなプロセスでは、組立後
にアウターリード部をディップする溶融めっき時の20
0℃を超える加熱のため、熱衝撃を受け、レジンモール
ドにクラックが発生する場合がある。また、この方法は
生産性も悪くコスト高となる。さらに、溶融めっき時に
使用するフラックスにより半導体パッケージやアウター
リード部などが汚染され、半導体の信頼性を低下させる
原因になっている。このような問題を解決するために、
近年、リードフレームの段階で、予めW/B性、はんだ
付け性の良いパラジウム(Pd)を表面処理膜として設
ける技術が検討されている。
However, in such a process, the outer lead portion is dipped for 20 seconds during hot-dip plating after assembly.
Due to heating above 0°C, cracks may occur in the resin mold due to thermal shock. Furthermore, this method has poor productivity and is high in cost. Furthermore, the flux used during hot-dip plating contaminates the semiconductor package, outer leads, etc., causing a reduction in the reliability of the semiconductor. In order to solve such problems,
In recent years, a technique has been studied in which palladium (Pd), which has good W/B properties and solderability, is provided as a surface treatment film in advance at the lead frame stage.

【0005】[0005]

【発明が解決しようとする課題】半導体組立後のアウタ
ーリード部にはんだめっき層を設ける方法では、溶融め
っき時の加熱による熱衝撃、レジンモールドのクラック
発生、フラックス使用による半導体パッケージやアウタ
ーリード部の汚染など耐湿性の低下が避けられなかった
。さらに半導体製造メーカーが半導体を出荷するまでに
かかる時間の大半をこの完成品めっき工程が占めるため
、製品の短納期化の障害となっていた。また、半導体組
立工程における生産性の向上を考えた場合、完成品めっ
きは、外注に頼るため、ラインの一貫自動化に対処する
ことができず、人件費の削減、コスト低減等において問
題となる点が多かった。
[Problems to be Solved by the Invention] In the method of providing a solder plating layer on the outer lead portion after semiconductor assembly, there are problems such as thermal shock due to heating during hot-dip plating, cracking of the resin mold, and damage to the semiconductor package and outer lead portion due to the use of flux. Decrease in moisture resistance due to contamination was unavoidable. Furthermore, the finished product plating process takes up most of the time it takes for semiconductor manufacturers to ship semiconductors, which has been an obstacle to shortening product delivery times. In addition, when considering the improvement of productivity in the semiconductor assembly process, finished product plating relies on outsourcing, which makes it impossible to deal with integrated automation of the line, which poses problems in terms of reducing labor costs and costs. There were many.

【0006】あらかじめ、リードフレーム最表面にPd
めっき層を設けたリードフレームは、一色でW/B性お
よびはんだ付け性が良いため、めっき工程も簡略化でき
る。そのため、最近では、Agめっきおよびはんだめっ
きを予め設けたリードフレームに代わって注目される技
術となっている。しかしPdの値段が高いことから、薄
くめっきを行なわなければならず、Pdめっき膜自体に
ピンホールが多くあり、半導体組立時の300℃近辺の
加熱後、下地金属およびPd自身の酸化が起こり、W/
B性、はんだ付け性等のめっき膜特性が低下するという
問題があった。
[0006] In advance, Pd is applied to the outermost surface of the lead frame.
Since the lead frame provided with the plating layer has good W/B properties and solderability because of its single color, the plating process can also be simplified. Therefore, recently, it has become a technology that is attracting attention as an alternative to lead frames that are pre-plated with Ag plating and solder plating. However, due to the high price of Pd, it must be plated thinly, and the Pd plating film itself has many pinholes, and after heating to around 300 degrees Celsius during semiconductor assembly, oxidation of the base metal and Pd itself occurs. W/
There was a problem that the properties of the plating film, such as B properties and solderability, deteriorated.

【0007】本発明は、表面処理膜の耐熱性を大幅に向
上させ、優れた特性を得ることを可能とし、さらに、P
d一層のときよりも安い価格で、高品質の表面処理膜が
得られる半導体装置用リードフレームを提供することを
目的としている。
[0007] The present invention makes it possible to significantly improve the heat resistance of the surface-treated film and obtain excellent properties.
The purpose of the present invention is to provide a lead frame for a semiconductor device that can provide a high-quality surface treatment film at a lower price than when using a single layer.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に本発明によれば、インナーリード部およびアウターリ
ード部を有する半導体装置用のリードフレームであって
、前記リードフレームの全面にNi系めっき層を有し、
その上層の少なくともインナーリード部およびアウター
リード部にPdまたはPd合金めっき層を有し、さらに
その上層の少なくともインナーリード部およびアウター
リード部にAuめっき層を有することを特徴とする半導
体装置用リードフレームが提供される。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a lead frame for a semiconductor device having an inner lead portion and an outer lead portion, wherein the entire surface of the lead frame is coated with Ni-based plating. has a layer,
A lead frame for a semiconductor device, which has a Pd or Pd alloy plating layer on at least the inner lead portion and the outer lead portion of the upper layer, and further has an Au plating layer on at least the inner lead portion and the outer lead portion of the upper layer. is provided.

【0009】以下に本発明をさらに詳細に説明する。The present invention will be explained in more detail below.

【0010】図1は、本発明の一実施例を示す半導体装
置用リードフレームを用いたパッケージの断面図である
。本発明のリードフレームの形状は図4に示すものと同
様であって、インナーリード部5およびアウターリード
部3を有する。
FIG. 1 is a sectional view of a package using a lead frame for a semiconductor device showing one embodiment of the present invention. The shape of the lead frame of the present invention is similar to that shown in FIG. 4, and has an inner lead part 5 and an outer lead part 3.

【0011】本発明は、前記図4に示す形状のリードフ
レーム1の全面にNi系めっき層9を有し、その上層に
PdまたはPd合金めっき層15を、さらにその上層に
Auめっき層を有する。
[0011] The present invention has a Ni-based plating layer 9 on the entire surface of the lead frame 1 having the shape shown in FIG. .

【0012】前記リードフレーム材としては、一般にC
u合金またはFe合金を挙げることができるが、これに
限るものではない。前記Ni系めっき層9は、拡散防止
および耐食性向上のために設けるもので、一般に無光沢
または光沢めっきがワット浴を用いて行なわれ、層厚は
0.1〜5μm 程度でよい。前記層厚は5μm 超で
もよいが10μm 以上になると曲げ加工時にクラック
発生の恐れがある。
The lead frame material is generally made of C.
Examples include, but are not limited to, u alloys and Fe alloys. The Ni-based plating layer 9 is provided to prevent diffusion and improve corrosion resistance. Generally, matte or glossy plating is performed using a Watt bath, and the layer thickness may be about 0.1 to 5 μm. The layer thickness may be more than 5 μm, but if it is more than 10 μm, there is a risk of cracks occurring during bending.

【0013】前記Ni系めっき層9の上層にはPdまた
はPd合金めっき層15が設けられる。このPdまたは
Pd合金めっき層15は少なくともインナーリード部5
およびアウターリード部3に設け、W/B性、はんだ付
け性を付与するが高価であるから層厚を余り厚くしない
方が有利で、0.01μm 以上であればよい。このP
dまたはPd合金めっきは公知の方法で設けることがで
きる。
A Pd or Pd alloy plating layer 15 is provided on the Ni-based plating layer 9 . This Pd or Pd alloy plating layer 15 is applied to at least the inner lead portion 5.
It is provided in the outer lead portion 3 to impart W/B properties and solderability, but since it is expensive, it is advantageous not to make the layer thick too much, and it is sufficient if it is 0.01 μm or more. This P
d or Pd alloy plating can be provided by a known method.

【0014】本発明では、前記PdまたはPd合金めつ
き層15の上にAuめっき層16を設ける。このAuめ
っき層16は少なくともインナーリード部5およびアウ
ターリード部3に設ける。これにより低コストで半導体
組立時の耐熱性を大幅に向上することができる。Auめ
っき層16の厚さは0.01μm 以上あれば半導体組
立後も優れたW/B性、はんだ付け性を保つことができ
る。
In the present invention, an Au plating layer 16 is provided on the Pd or Pd alloy plating layer 15. This Au plating layer 16 is provided at least on the inner lead portion 5 and the outer lead portion 3. This makes it possible to significantly improve heat resistance during semiconductor assembly at low cost. If the thickness of the Au plating layer 16 is 0.01 μm or more, excellent W/B properties and solderability can be maintained even after semiconductor assembly.

【0015】[0015]

【実施例】以下に本発明を実施例に基づき具体的に説明
する。
EXAMPLES The present invention will be specifically explained below based on examples.

【0016】(実施例1)Cu合金リードフレーム全面
に、無光沢Niめっきを0.5μm 設けた。その後リ
ードフレームのインナーリード部とアウターリード部に
それぞれPdめっきを0.05μm 行なった。さらに
、その上層にAuめっきを0.02μm 行なった。な
お、各めっき厚は蛍光X線膜厚計により測定した。めっ
条件は、以下のとおりである。   無光沢Niめっき(ワット浴)     NiSO4 ・6H2 O    250g/
l    温度        55℃    NiC
l2 ・6H2 O      50g/l    電
流密度    4A/dm2     H3 BO3 
                50g/l    
アノード    Ni板  Pdめっき液:パラデック
スHS(田中貴金属工業(株)製)    金属Pd濃
度    10g/l      電流密度    1
A/dm2     温        度    6
0℃          アノード    白金めっき
チンタン板  Auめっき液:テンペレックス702(
田中貴金属工業(株)製)    金属Au濃度   
     15g/l    温度         
       70℃    電流密度       
   0.5A/dm2     アノード     
     白金めっきチタン板
(Example 1) Matte Ni plating was provided on the entire surface of a Cu alloy lead frame to a thickness of 0.5 μm. Thereafter, Pd plating was applied to the inner lead portion and outer lead portion of the lead frame to a thickness of 0.05 μm, respectively. Furthermore, Au plating was performed on the upper layer to a thickness of 0.02 μm. Note that each plating thickness was measured using a fluorescent X-ray film thickness meter. The plating conditions are as follows. Matte Ni plating (Wat bath) NiSO4 ・6H2 O 250g/
l Temperature 55℃ NiC
l2 ・6H2 O 50g/l Current density 4A/dm2 H3 BO3
50g/l
Anode Ni plate Pd plating solution: Paradex HS (manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) Metal Pd concentration 10 g/l Current density 1
A/dm2 temperature 6
0℃ Anode Platinum plated tin plate Au plating solution: Temperex 702 (
(manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) Metallic Au concentration
15g/l temperature
70℃ current density
0.5A/dm2 anode
Platinum plated titanium plate

【0017】次に、比較
のために、上記実施例1のPdめっきまで行なったもの
を用いた。このときPdめっき厚は、それぞれ0.05
μm (比較例1)および0.5μm(比較例2)とし
た(表1参照)。
Next, for comparison, the same sample as in Example 1 which had been subjected to Pd plating was used. At this time, the Pd plating thickness was 0.05
μm (Comparative Example 1) and 0.5 μm (Comparative Example 2) (see Table 1).

【0018】(実施例2)Fe合金リードフレーム全面
に光沢Niめっきを0.5μm 設けた後、Pd−Ni
めっきを0.1μm 行ない、さらにAuめっきを0.
02μm 行なった。各めっき厚は蛍光X線膜厚計によ
り測定した。なお、めっき条件は以下のとおりである。   光沢Niめっき(ワット浴)     NiSO4 ・6H2 O    250g/
l    温度        50℃    NiC
l2 ・6H2 O      51g/l    電
流密度    4A/dm2     H3 BO3 
                50g/l    
アノード    Ni板    #61(2次光沢剤)
        5ml/l(荘原ユージライト社製)
    #63(1次光沢剤)      10ml/
l(荘原ユージライト社製)  Pd−Niめっき液     バルニック816             
   温度        30℃      (NE
ケムキャット社製)    金属Pd濃度    10
g/l      電流密度      1A/dm2
     金属Ni濃度      6g/l    
  アノード    白金めっきチタン板  Auめっ
き液     オウロベルUP−24           
 電流密度      1A/dm2       (
日本リーロナール社製)    金属Au濃度    
  8g/l      アノード    白金めっき
チタン板    温度            70℃
(Example 2) After providing 0.5 μm of bright Ni plating on the entire surface of the Fe alloy lead frame, Pd-Ni
Plating is performed to a thickness of 0.1 μm, and further Au plating is applied to a thickness of 0.1 μm.
02 μm. Each plating thickness was measured using a fluorescent X-ray film thickness meter. In addition, the plating conditions are as follows. Bright Ni plating (Wat bath) NiSO4 ・6H2 O 250g/
l Temperature 50℃ NiC
l2 ・6H2 O 51g/l Current density 4A/dm2 H3 BO3
50g/l
Anode Ni plate #61 (secondary brightener)
5ml/l (manufactured by Shobara Yugilite)
#63 (primary brightener) 10ml/
l (manufactured by Shobara Yugilite Co., Ltd.) Pd-Ni plating solution Balnic 816
Temperature 30℃ (NE
(manufactured by Chemcat) Metallic Pd concentration 10
g/l Current density 1A/dm2
Metallic Ni concentration 6g/l
Anode Platinum-plated titanium plate Au plating solution Ourobel UP-24
Current density 1A/dm2 (
(manufactured by Nippon Leeronal Co., Ltd.) Metallic Au concentration
8g/l Anode Platinum-plated titanium plate Temperature 70℃

【0019】次に、比較のために、上記実施例2のPd
−Niめっきまで行なったものを用いた。このときPd
−Niめっき厚は、それぞれ0.1μm (比較例3)
および1.0μm (比較例4)とした(表2参照)。 また、比較例5として実施例2のPd−Niめっきを設
けず、Niめっき上に直接Auめっきを0.02μm 
設けたものを用いた。なお、表1、2の各層番号を図2
に示した。
Next, for comparison, the Pd of Example 2
-The one that had been subjected to Ni plating was used. At this time Pd
-Ni plating thickness is 0.1 μm (Comparative Example 3)
and 1.0 μm (Comparative Example 4) (see Table 2). In addition, as Comparative Example 5, the Pd-Ni plating of Example 2 was not provided, and Au plating was directly applied to a thickness of 0.02 μm on the Ni plating.
I used what was provided. The layer numbers in Tables 1 and 2 are shown in Figure 2.
It was shown to.

【0020】このようにして得た本発明リードフレーム
と比較例1〜5の特性比較を行なった。比較項目は、半
導体組立時のペレット付け工程の熱履歴を模擬した30
0℃×30秒加熱後のW/B試験およびはんだぬれ性試
験である。W/B試験は、全ショット数に対するAu線
の圧着数の割合をW/B圧着率として表わした。はんだ
ぬれ性試験は、タムラ製作所製のデジタルソルダーグラ
フを用い、230±5℃に保った共晶はんだ浴に試料を
浸漬し、ゼロクロッシングタイム(はんだぬれ時間)を
測定してその時間(S)で表わした。なお、この時25
wt%WWロジンフラックスを使用した。結果を表3に
示す。また、特性を満たすために最低限必要なAuおよ
びPdめっきを設けた際のめっき薬品代の比較を表4に
示す。表4中のA、B、C、Dはメーカーを示し、めっ
き薬品代合計はDの値を1として比率で示した。さらに
、実施例1および比較例2のはんだぬれ性については、
300〜450℃の範囲で温度を25℃ずつ変化させ、
30秒加熱を行なった試料について、はんだぬれ時間を
測定した。結果を図3に示す。
The characteristics of the lead frame of the present invention thus obtained and Comparative Examples 1 to 5 were compared. The comparison items are 30 samples that simulate the thermal history of the pellet attaching process during semiconductor assembly.
These are a W/B test and a solderability test after heating at 0° C. for 30 seconds. In the W/B test, the ratio of the number of Au wires crimped to the total number of shots was expressed as the W/B crimping rate. The solder wettability test uses a digital solder graph manufactured by Tamura Seisakusho, immerses the sample in a eutectic solder bath kept at 230 ± 5 degrees Celsius, measures the zero crossing time (solder wetting time), and calculates the time (S). It was expressed as In addition, at this time 25
wt% WW rosin flux was used. The results are shown in Table 3. Further, Table 4 shows a comparison of plating chemical costs when providing the minimum necessary Au and Pd plating to satisfy the characteristics. A, B, C, and D in Table 4 indicate manufacturers, and the total plating chemical costs are expressed as a ratio, with the value of D being 1. Furthermore, regarding the solder wettability of Example 1 and Comparative Example 2,
The temperature was varied by 25°C in the range of 300 to 450°C,
The solder wetting time was measured for the sample heated for 30 seconds. The results are shown in Figure 3.

【0021】[0021]

【0022】[0022]

【0023】[0023]

【0024】[0024]

【0025】表3より、本発明リードフレームは、30
0℃×30秒加熱後のW/B圧着率が100%と優れて
いた。しかし、比較例1〜5はW/B圧着率が全て0%
となり、W/B性の低下が見られた。また、はんだぬれ
性については、本発明リードフレームは300℃×30
秒加熱後も、ゼロクロッシングタイムが1秒以内と良好
であるのに対し、比較例は、ゼロクロッシングタイムの
値が増大し、はんだぬれ性が劣化した。また、図3より
、実施例1は425℃×30秒の加熱後もはんだぬれ性
が良好なのに対し、比較例2は300℃超の加熱でぬれ
性が低下した。以上より、Pdの上層にAuめっきを薄
く設けることにより、耐熱性が100℃以上も向上する
ことが分かった。
From Table 3, the lead frame of the present invention has 30
The W/B compression bonding rate after heating at 0° C. for 30 seconds was 100%, which was excellent. However, in Comparative Examples 1 to 5, the W/B crimping rate was all 0%.
Therefore, a decrease in W/B properties was observed. In addition, regarding solder wettability, the lead frame of the present invention
Even after heating for seconds, the zero crossing time was good, being within 1 second, whereas in the comparative example, the value of the zero crossing time increased and the solderability deteriorated. Further, from FIG. 3, Example 1 had good solder wettability even after heating at 425° C. for 30 seconds, whereas Comparative Example 2 had poor solder wettability when heated at over 300° C. From the above, it was found that heat resistance was improved by 100° C. or more by providing a thin Au plating on the Pd layer.

【0026】[0026]

【発明の効果】本発明は以上説明したように構成されて
いるので、本発明によれば、リードフレーム表面処理膜
の耐熱性を大幅に向上させることが可能となり、半導体
組立後も安定したW/B性、はんだ付け性が得られた。 またPd上にAuを設ける2層構造により、Pdのみで
特性を満たす場合に比べめっき薬品代が総合的に安くな
るメリットがある。
[Effects of the Invention] Since the present invention is configured as described above, it is possible to significantly improve the heat resistance of the lead frame surface treatment film, and to maintain stable W even after semiconductor assembly. /B properties and solderability were obtained. Furthermore, the two-layer structure in which Au is provided on Pd has the advantage that the cost of plating chemicals is lower overall than when the characteristics are satisfied only with Pd.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例を示す半導体装置用リードフ
レームを用いたパッケージの断面図である。
FIG. 1 is a cross-sectional view of a package using a lead frame for a semiconductor device showing one embodiment of the present invention.

【図2】実施例リードフレームの各層番号を示す断面図
である。
FIG. 2 is a cross-sectional view showing each layer number of the example lead frame.

【図3】各加熱温度とゼロクロッシングタイムとの関係
を示すグラフである。
FIG. 3 is a graph showing the relationship between each heating temperature and zero crossing time.

【図4】従来のリードフレームの一例を示す平面図であ
る。
FIG. 4 is a plan view showing an example of a conventional lead frame.

【図5】従来の半導体パッケージの一例を示す断面図で
ある。
FIG. 5 is a cross-sectional view showing an example of a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

1  リードフレーム 2  外枠部 3  アウターリード部 4  ダムバー 5  インナーリード部 6  インナーリード部の先端部 7  半導体チップ載置部 8  パイロットホール 9  Ni系めっき層 10  Agめっき層 11  Sn−Pb合金めっき層 12  Auワイヤ 13  半導体チップ 14  モールド樹脂 15  PdまたはPd合金めっき層 16  Auめっき層 17  リードフレーム材 1 Lead frame 2 Outer frame part 3 Outer lead part 4 Dam bar 5 Inner lead part 6 Tip of inner lead part 7 Semiconductor chip mounting part 8 Pilot hole 9 Ni-based plating layer 10 Ag plating layer 11 Sn-Pb alloy plating layer 12 Au wire 13 Semiconductor chip 14 Mold resin 15 Pd or Pd alloy plating layer 16 Au plating layer 17 Lead frame material

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  インナーリード部およびアウターリー
ド部を有する半導体装置用のリードフレームであって、
前記リードフレームの全面にNi系めっき層を有し、そ
の上層の少なくともインナーリード部およびアウターリ
ード部にPdまたはPd合金めっき層を有し、さらにそ
の上層の少なくともインナーリード部およびアウターリ
ード部にAuめっき層を有することを特徴とする半導体
装置用リードフレーム。
1. A lead frame for a semiconductor device having an inner lead portion and an outer lead portion, the lead frame comprising:
The lead frame has a Ni plating layer on the entire surface, a Pd or Pd alloy plating layer on at least the inner lead portion and the outer lead portion of the upper layer, and an Au plating layer on at least the inner lead portion and the outer lead portion of the upper layer. A lead frame for a semiconductor device characterized by having a plating layer.
JP3109163A 1991-05-14 1991-05-14 Lead frame for semiconductor device Pending JPH04337657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3109163A JPH04337657A (en) 1991-05-14 1991-05-14 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3109163A JPH04337657A (en) 1991-05-14 1991-05-14 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH04337657A true JPH04337657A (en) 1992-11-25

Family

ID=14503248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3109163A Pending JPH04337657A (en) 1991-05-14 1991-05-14 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH04337657A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232493A (en) * 1995-12-20 1997-09-05 Seiichi Serizawa Lead frame
WO1998035382A1 (en) * 1997-02-10 1998-08-13 Matsushita Electronics Corporation Resin sealed semiconductor device and method for manufacturing the same
DE19741921A1 (en) * 1997-09-23 1999-02-25 Siemens Ag Carrier element for semiconductor chip card data type carrier
JP2000133845A (en) * 1998-10-23 2000-05-12 Rohm Co Ltd Semiconductor light-emitting element
US6126885A (en) * 1997-06-27 2000-10-03 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device
JP2005314749A (en) * 2004-04-28 2005-11-10 Shinei Hitec:Kk Electronic component and surface treatment method therefor
JP2006083409A (en) * 2004-09-14 2006-03-30 Shinei Hitec:Kk Ferro-alloy electronic part and surface treatment method therefor
JP2006083410A (en) * 2004-09-14 2006-03-30 Shinei Hitec:Kk Method for manufacturing electronic part
JP2007217798A (en) * 2007-05-23 2007-08-30 Shinei Hitec:Kk Surface treatment method for connection terminal for connector
US7329944B2 (en) 2005-03-25 2008-02-12 Shinko Electric Industries Co., Ltd. Leadframe for semiconductor device
US7408248B2 (en) 2004-05-27 2008-08-05 Shinko Electric Industries Co., Ltd. Lead frame for semiconductor device
US8283759B2 (en) 2005-10-20 2012-10-09 Panasonic Corporation Lead frame having outer leads coated with a four layer plating
JP2014123760A (en) * 2014-02-17 2014-07-03 Mitsui High Tec Inc Lead frame

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232493A (en) * 1995-12-20 1997-09-05 Seiichi Serizawa Lead frame
WO1998035382A1 (en) * 1997-02-10 1998-08-13 Matsushita Electronics Corporation Resin sealed semiconductor device and method for manufacturing the same
US6291274B1 (en) 1997-02-10 2001-09-18 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device and method for manufacturing the same
US6126885A (en) * 1997-06-27 2000-10-03 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device
US6258314B1 (en) 1997-06-27 2001-07-10 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device
DE19741921A1 (en) * 1997-09-23 1999-02-25 Siemens Ag Carrier element for semiconductor chip card data type carrier
JP2000133845A (en) * 1998-10-23 2000-05-12 Rohm Co Ltd Semiconductor light-emitting element
US7233072B2 (en) 2004-04-28 2007-06-19 Shinei Hi-Tech Co., Ltd. Electronic part and surface treatment method of the same
JP2005314749A (en) * 2004-04-28 2005-11-10 Shinei Hitec:Kk Electronic component and surface treatment method therefor
US7408248B2 (en) 2004-05-27 2008-08-05 Shinko Electric Industries Co., Ltd. Lead frame for semiconductor device
JP2006083409A (en) * 2004-09-14 2006-03-30 Shinei Hitec:Kk Ferro-alloy electronic part and surface treatment method therefor
JP2006083410A (en) * 2004-09-14 2006-03-30 Shinei Hitec:Kk Method for manufacturing electronic part
US7329944B2 (en) 2005-03-25 2008-02-12 Shinko Electric Industries Co., Ltd. Leadframe for semiconductor device
US8283759B2 (en) 2005-10-20 2012-10-09 Panasonic Corporation Lead frame having outer leads coated with a four layer plating
JP2007217798A (en) * 2007-05-23 2007-08-30 Shinei Hitec:Kk Surface treatment method for connection terminal for connector
JP2014123760A (en) * 2014-02-17 2014-07-03 Mitsui High Tec Inc Lead frame

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