JPH04284021A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the delay of timing to switch an output voltage level in the case of switching an input voltage level. CONSTITUTION:A P channel transistor 5 is connected between a P channel transistor 1 and an N channel transistor 3, and a P channel transistor 6 is connected between a P channel transistor 2 and an N channel transistor 4. For example, when the potential of an input terminal IN is changed from the low level to the high level, the transistor 3 is turned on, and a connecting point A is turned to a ground potential. At such a time, the potential of the connecting point A is not made high by the ON resistance of the transistor 5 although the transistor 1 is still turned on, and the transistor 2 can be immediately turned on. Thus, a connecting point B can be turned to the high level, and the transistor 1 can be turned off.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit called a level shift circuit, which converts the voltage of an input signal from a low voltage to a high voltage and outputs the converted voltage.

0002

2. Description of the Related Art FIG. 4 is a circuit diagram showing the configuration of a level shift circuit 20 as a conventional example. Level shift circuit 20
are P-channel transistors 21 and 22, N-channel transistors 23 and 24, and an inverter (inversion) circuit 2.
7. Input terminal in is connected to the gate of N-channel transistor 23 and the gate of N-channel transistor 24 via inverter circuit 27, respectively. An input voltage whose voltage range is from the ground potential GND to the potential VL is input to the input terminal in.

The N-channel transistor 23 has a source connected to the ground potential GND and a drain connected to P via a connection point a.
They are connected to the drains of channel transistors 21, respectively. Further, the N-channel transistor 24 has a source connected to the ground potential GND, and a drain connected to the drain of the P-channel transistor 22 via a connection point b. P-channel transistor 21 has a source connected to power supply potential VH and a gate connected to connection point b. Further, the P-channel transistor 22 has its source connected to the power supply voltage VH, and its gate connected to the connection point a. The output terminal out is connected to the connection point b, and therefore the potential of the connection point b is output as the potential of the output voltage.

In the level shift circuit 20 having such a configuration, when the input terminal in is at the potential VL, the N-channel transistor 23 is turned on, and the N-channel transistor 24 is turned on.
is turned off, and the connection point a becomes the ground potential GND. This turns on P-channel transistor 22. Therefore, the potential at the connection point b becomes VH, and the P-channel transistor 21 is turned off. Here, the output terminal ou
t is the potential VH.

[0005] Furthermore, the input terminal in is connected to the ground potential GND.
When , the N-channel transistor 24 is turned on and the N-channel transistor 24 is turned on.
The channel transistor 23 is turned off, and the connection point b becomes the ground potential GND. This turns on P-channel transistor 21. Therefore, the connection point a becomes the potential VH, and the P-channel transistor 22 is turned off. Here, the potential of the output terminal out is the ground potential GND
It is. In this way, an input level of a low voltage (potential VL) can be converted to an output level of a high voltage (potential VH).

[0006]

FIG. 5 is a timing chart showing the operation of the level shift circuit 20. Figure 4
In the level shift circuit 20 shown in FIG. 1, immediately after the potential of the input signal changes from the ground potential GND to the potential VL, the N-channel transistor 23 switches from off to on, and the N-channel transistor 24 switches from on to off. Channel transistor 21 remains on, so the potential at connection point a is determined by the on-resistances (resistance values during on-operation) of P-channel transistor 21 and N-channel transistor 23. If the potential at the connection point a at this time is high, it may be impossible to turn on the P-channel transistor 22, or there will be a delay in the timing at which it is turned on.

In order to eliminate such malfunctions or timing delays, the on-resistance of the N-channel transistor 23 must be made sufficiently smaller than the on-resistance of the P-channel transistor 21. Similarly, the on-resistance of the N-channel transistor 24 must also be made sufficiently smaller than the on-resistance of the P-channel transistor 22.

However, when such a level shift circuit 20 is employed in an LSI (Large Scale Integrated Circuit), the size of the N-channel transistors 23 and 24 needs to be larger than the size of the P-channel transistors 21 and 22. Therefore, a problem arises in that the area occupied on the LSI chip increases.

FIG. 6 is a circuit diagram showing the configuration of another conventional level shift circuit 20a. The level shift circuit 20a is constructed by adding P-channel transistors 25 and 26 to the level shift circuit 20 of FIG. 4 to prevent the potential at the connection point a from becoming high, thereby preventing the above-mentioned malfunctions and timing delays. are doing.

The P-channel transistor 25 has a drain connected to the connection point a, a source connected to the drain of the P-channel transistor 21, and a gate connected to the input terminal in.
An input voltage is given from P-channel transistor 26 has a drain connected to connection point b, a source connected to the drain of P-channel transistor 22, and a gate provided with the output of inverter circuit 27.

In the level shift circuit 20a, when the input voltage changes from the ground potential GND to the potential VL, the N-channel transistor 23 is turned on and the P-channel transistor 25 is turned off. This prevents the potential at the connection point a from becoming high.

However, if the potential difference between potential VL and potential VH is large, or if the input voltage level is lower than potential VL,
If it is even lower than P-channel transistor 25
is not turned off, and as a result, the potential at the connection point a becomes high, causing malfunctions and delays in switching timing, as in the case of the level shift circuit 20 described above.

Therefore, when level shift circuit 20a shown in FIG. 6 is employed in an LSI, it is necessary to make the size of N-channel transistors 23 and 24 larger than other transistors. Therefore, as in the case of the level shift circuit 20 described above, a problem arises in that the area occupied by the N-channel transistors 23 and 24 on the LSI chip increases.

An object of the present invention is to provide an output circuit that can reduce the delay in switching timing of the output voltage potential when the input voltage potential changes, and also reduce the size of the transistor. be.

[0015]

[Means for Solving the Problems] The present invention provides a first N-channel transistor to which a positive potential input voltage is applied to the gate, and a second N-channel transistor to which the opposite phase of the input voltage is applied to the gate. , respectively the first and second
is connected between the ground potential and a predetermined potential via a P-channel transistor, a first connection point where the first N-channel transistor and the first P-channel transistor are connected is connected to the gate of the second P-channel transistor, In an output circuit, a second connection point between the channel transistor and the second P-channel transistor is connected to the gate of the first P-channel transistor, and the potential at the second connection point is output as an output voltage. , a third P-channel transistor is connected between the first connection point, a gate of the third P-channel transistor is connected to the first connection point, and a third P-channel transistor is connected between the second P-channel transistor and the second connection point. The output circuit is characterized in that a fourth P-channel transistor is connected, and a gate of the fourth P-channel transistor is connected to a second connection point.

Further, the present invention is characterized in that, when the input voltage is a negative potential, each of the N-channel transistors is replaced with a P-channel transistor, and each of the P-channel transistors is replaced with an N-channel transistor.

[0017]

According to the present invention, when the input voltage is at a high level, the first N-channel transistor is turned on, the second N-channel transistor is turned off, and the first connection point is at ground potential. As a result, the second P-channel transistor is turned on, and the fourth P-channel transistor is also turned on, so that the second connection point has a predetermined potential (high level). Therefore, the first P-channel transistor is turned off, and a predetermined potential is output as the output voltage.

Further, when the input voltage is at ground potential (low level), the first N-channel transistor is turned off, the second N-channel transistor is turned on, and the second connection point is at ground potential. As a result, the first P-channel transistor is turned on, and the third P-channel transistor is also turned on, so that the first connection point becomes a high level and the second P-channel transistor is turned off. Therefore, the ground potential, which is the potential at the second connection point, is output as the output voltage.

[0019] Here, assume that the input voltage has just changed from the ground potential to a high level. The first N-channel transistor is switched from off to on, and the second N-channel transistor is switched from on to off. At this time, the first
Even though the P-channel transistor is still on,
By interposing the third P-channel transistor, the potential at the first connection point does not rise, and the second P-channel transistor can be turned on immediately. This makes it possible to set the potential at the second connection point to a high level, turn off the first P-channel transistor, and output a predetermined potential (potential at the second connection point) as an output voltage.

Next, assume that the input voltage is changed from high level to ground potential. The first N-channel transistor is switched from on to off, and the second N-channel transistor is switched from off to on. At this time, the second P
Although the channel transistor still remains on, due to the interposition of the fourth P-channel transistor, the potential at the second connection point does not rise and the first P-channel transistor can be turned off immediately. As a result, the potential of the first connection point is set to the ground potential, and the potential of the second connection point is set to the ground potential.
It is possible to turn off the channel transistor and output the ground potential (the potential at the second connection point) as the output voltage.

Furthermore, in the above output circuit, when the input voltage is a negative potential, each N-channel transistor is
A similar operation can be achieved by replacing each P-channel transistor with an N-channel transistor.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing the configuration of a level shift circuit 10 which is an embodiment of the present invention. The level shift circuit 10 includes P channel transistors 1, 2, 5, 6,
N-channel transistors 3 and 4 and inverter (inversion)
The circuit 7 is configured to include a circuit 7. Input terminal IN is connected to the gate of N-channel transistor 3 and the gate of N-channel transistor 4 via inverter circuit 7, respectively. An input voltage whose voltage range is from the ground potential GND to the potential VL is input to the input terminal IN.

N-channel transistor 3 has a source connected to ground potential GND, and a drain connected to the drain of P-channel transistor 5 via connection point A. The gate and drain of P-channel transistor 5 are connected at connection point A, and the source is connected to the drain of the P-channel transistor. The source of P-channel transistor 1 is connected to power supply potential VH. Connection point A
is connected to the gate of P-channel transistor 2.

N-channel transistor 4 has a source connected to ground potential GND, and a drain connected to the drain of P-channel transistor 6 via connection point B. P-channel transistor 6 has its gate and drain connected at connection point B, and its source is connected to the drain of P-channel transistor 2. P-channel transistor 2 has a source connected to power supply potential VH. Connection point B is connected to the gate of P-channel transistor 1 and also to output terminal OUT.

When the input terminal IN is at the potential VL, the N-channel transistor 3 is turned on, the N-channel transistor 4 is turned off, and the connection point A becomes the ground potential GND. As a result, the P-channel transistor 2 is turned on, and the P-channel transistor 6 is also turned on, so that the connection point B becomes the potential VH, and the P-channel transistor 1 is turned off. Therefore, the potential VH, which is the potential of the connection point B, is output from the output terminal OUT.

When the input terminal IN is at the ground potential GND, the N-channel transistor 3 is turned off, the N-channel transistor 4 is turned on, and the connection point B is at the ground potential GND. As a result, P-channel transistor 1 is turned on, and P-channel transistor 5 is also turned on, so that connection point A becomes potential VH, and P-channel transistor 2 is turned off. Therefore, the output terminal OUT is connected to the ground potential GN, which is the potential of the connection point B.
D is output.

FIG. 2 is a timing chart showing the operation of the level shift circuit 10. Referring to FIG. 2, first, the operation immediately after the input voltage changes from the ground potential GND to the potential VL will be described. N-channel transistor 3 is switched from off to on, and N-channel transistor 4 is switched from on to off. At this time, although P-channel transistor 1 remains on, the potential at connection point A does not increase due to the on-resistance of P-channel transistor 5, and P-channel transistor 2 can be immediately turned on. Thereby, it is possible to set the connection point B to the potential VH, turn off the P-channel transistor 1, and output the potential VH as the output voltage from the output terminal OUT.

Next, the operation immediately after the input voltage changes from the potential VL to the ground potential GND will be described. N-channel transistor 3 is switched from on to off, and N-channel transistor 4 is switched from off to on. At this time,
Although P-channel transistor 2 remains on, the potential at connection point B does not increase due to the on-resistance of P-channel transistor 6, and P-channel transistor 1
can be turned on immediately. Thereby, it is possible to set the connection point A to the potential VH, turn off the P-channel transistor 2, and output the ground potential GND as the output voltage from the output terminal OUT.

As described above, according to this embodiment, the delay in the switching timing of the output voltage level at the time of switching the input voltage level can be made smaller than in the prior art. Furthermore, when the level shift circuit 10 is incorporated into an LSI, for example, there is no need to make the size of the N-channel transistors 3 and 4 larger than the size of other transistors as in the conventional case, and the circuit can be made smaller.
This allows the area occupied by the circuit on the LSI chip to be reduced.

FIG. 3 is a circuit diagram showing the configuration of a level shift circuit 10a which is another embodiment of the present invention. In the level shift circuit 10a, both the input voltage and the output voltage are set to negative potentials, and the P channel transistor and the N channel transistor of the level shift circuit 10 shown in FIG. 1 are replaced. The level shift circuit 10a also has the same effect as the level shift circuit 10 described above.

[0031]

As described above, according to the present invention, the delay in the switching timing of the output voltage level at the time of switching the input voltage level can be made smaller than in the prior art. Furthermore, when such an output circuit is used in an LSI, for example, it is no longer necessary to make the first and second N-channel transistors larger than the other transistors as in the past, and the circuit can be made smaller. be able to.

[Brief explanation of the drawing]

FIG. 1: A level shift circuit 10 which is an embodiment of the present invention.
FIG.

2 is a timing chart showing the operation of the level shift circuit 10 shown in FIG. 1. FIG.

FIG. 3: Level shift circuit 1 which is another embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of 0a.

FIG. 4 is a circuit diagram showing the configuration of a level shift circuit 20 as a conventional example.

FIG. 5 is a timing chart showing the operation of the level shift circuit 20.

FIG. 6 is a circuit diagram showing the configuration of a conventional level shift circuit 20a.

[Explanation of symbols]

1, 2, 5, 6 P channel transistor 3, 4
N-channel transistor 7 Inverter circuit 10, 10a Level shift circuit A, B Connection point IN Input terminal OUT Output terminal

Claims (2)

[Claims] 1. A first N-channel transistor to which a positive potential input voltage is applied to the gate, and a second N-channel transistor to which the opposite phase of the input voltage is applied to the gate, respectively. Connected between the ground potential and a predetermined potential via a P-channel transistor,
A first connection point where the first N-channel transistor and the first P-channel transistor are connected is connected to the gate of the second P-channel transistor, and a second connection point where the second N-channel transistor and the second P-channel transistor are connected is connected to the gate of the second P-channel transistor. In the output circuit that is connected to the gate of the first P-channel transistor and outputs the potential of the second connection point as an output voltage, a third P-channel transistor is connected between the first P-channel transistor and the first connection point. ,
A gate of the third P-channel transistor is connected to the first connection point, a fourth P-channel transistor is connected between the second P-channel transistor and the second connection point, and the fourth P-channel transistor is connected to the first connection point.
An output circuit characterized in that a gate of a P-channel transistor is connected to a second connection point. [Claim 2] When the input voltage is a negative potential,
2. The output circuit according to claim 1, wherein each of the N-channel transistors is replaced with a P-channel transistor, and each of the P-channel transistors is replaced with an N-channel transistor.