JPH04280228A - Thin film field effect type transistor driving liquid crystal display element array and driving method thereof - Google Patents

Abstract

PURPOSE:To prevent the short circuit between electrodes due to a pin hole in a gate insulating film by further using a high resistance semiconductor layer other than the gate insulating film as the inter-layer insulating film of an accu mulation capacitor. CONSTITUTION:A chromium film is formed on a glass base plate 11 and patterned, whereby a gate line 1(N), a gate electrode 2(M, N) and an accumulation capacitor 12 consisting of chromium are formed. A silicon nitride film as a gate insulating film 7, an amorphous silicon hydride film 8, and an amorphous silicon hydride film 9 doped with phosphorous are successively formed. The amorphous silicon hydride film 8 and the amorphous silicone film 9 are patterned to form lands in the crossing point of the gate line 1 and an accumulation capacitor line 12N with a source line 3(M) on the gate electrode 2, and further in the superposed part of a picture element electrode 6(M, N) with the accumulation capacitor 12(N). An ITO film which is a transparent electrode is formed and then patterned into the picture element electrode 6(M, N).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film field effect transistor driven liquid crystal display element array.

0002

2. Description of the Related Art In a thin film field effect transistor driven liquid crystal display device, a thin film field effect transistor is used as a switching element. FIG. 6 shows a conventional display element array using hydrogenated amorphous silicon thin film field effect transistors as switching elements. FIG. 6(a) is a plan view, and FIG. 6(b) is a sectional view taken along the line AA in FIG. 6(a). FIG. 7 shows an equivalent circuit of one pixel. Furthermore, a timing chart of drive waveforms is shown in FIG.

In FIG. 6, 1(N-1), 1(N)...
, (N=1,2,...) are gate lines, 2(M,N), (M
=1,2,...,N=1,2,...) is the gate electrode, 3(M
-1), 3 (M), ..., (M = 1, 2, ...) are source lines, 4 is a source electrode, 5 is a drain electrode, 6 (M, N) is a pixel electrode, 7 is a gate insulating film, 8 is a high-resistance amorphous silicon film, 9 is an amorphous silicon film doped with phosphorus, 10 is a surface protection film, 11 is a glass substrate, and 12N is a storage capacitor line. In Figure 7, T(M,N)
1 is a thin film field effect transistor, and 14 is a liquid crystal.
Pixel liquid crystal capacitor, Cst is storage capacitor, Cg
d is the parasitic capacitance between the gate and drain of the thin film field effect transistor, which is generated from the channel capacitance and the overlap between the gate electrode and the drain electrode. 15 is a counter electrode arranged with the liquid crystal in between. In an actual liquid crystal display element array, the equivalent circuit shown in FIG. 7 is arranged in a matrix. In FIG. 8, Vgn is the nth gate line 1
(N), Vsm is the signal applied to the M-th source line, and Vdmn is the pixel electrode 6 (M, N
), and Vc is the potential of the counter electrode 15.

The structure of a conventional thin film field effect transistor-driven liquid crystal display element array will be explained by showing the manufacturing process with reference to FIG. First, gate lines 1 (N), N=1, 2, . . . , gate electrodes 2 (M, N) and storage capacitor lines 12N made of chromium are formed on a glass substrate 11. Next, a gate insulating film 7 made of silicon nitride,
An amorphous silicon film 8 and a phosphorus-doped amorphous silicon film 9 are successively formed to form a gate electrode 2 (M,
N) Upper, gate line 1 (N) and storage capacitor line 12N
An island made of an amorphous silicon film 8 and a phosphorous-doped amorphous silicon film 9 is formed at the intersection of the source line 3 (M) and the source line 3 (M). And indium-tin oxide (I
A pixel electrode 6 (M, N) made of (TO) is formed. Furthermore, using chromium, the source line 3 (M), the source electrode 4
, and a drain electrode 5 are formed. Following this process,
By removing the phosphorous-doped amorphous silicon film 9 between the source electrode 4 and drain electrode 5, the thin film field effect transistor is completed. Finally, by forming a surface protection film 10 made of silicon nitride, a conventional thin film field effect transistor driven liquid crystal display element array is completed.

Next, the operation of this display element array will be explained using FIGS. 7 and 8. First, in the first field of the video signal, a signal voltage corresponding to the brightness of each display cell is supplied from the source line 3 (M), and when a scanning pulse Vgn is input to the gate line 1 (N), a thin film field effect type Transistor T (M, N) turns on, and the signal voltage is applied to liquid crystal capacitor 1.
4 and is written to the storage capacitor Cst. In this case, it is assumed that the potential of the signal voltage is higher than the potential Vc of the common electrode. The storage capacitor Cst serves to compensate for the potential drop caused by discharge of charges due to the internal resistance of the liquid crystal capacitor 14. Thin film field effect transistor T (M, N
) is turned off, the written voltage is held until the voltage is written in the next second field. In the second field of the video signal, the source line 3 is connected as in the first field.
(M) is written into the liquid crystal capacitor 14 and the storage capacitor Cst when a scanning pulse is input to the gate line 1 (N). Note that in the second field, the potential of the signal voltage is lower than the potential Vc of the common electrode. When the thin film field effect transistor T(M,N) is turned off, the written voltage is held until the voltage is written in the next field. In this way, a voltage is applied to and driven the liquid crystal using the liquid crystal capacitor and the storage capacitor, and the transmitted light intensity is modulated to display an image. The reason why the polarity of the voltage to be written is reversed for each field and the liquid crystal is driven with alternating current is to prevent deterioration of the liquid crystal material.

[0006]

As described above, since the storage capacitor has the function of preventing charges from discharging inside the liquid crystal capacitor, it is desirable to have as large a capacity as possible. To achieve this, it is necessary to increase the width of the storage capacitor wiring to increase the overlapping area with the pixel electrode. However, when the overlapping area increases, the pixel electrode and the storage capacitor line are likely to be short-circuited due to dust or pinholes in the gate insulating film, resulting in pixel defects. Since the rate of occurrence of this defect is proportional to the overlap area, for example, in a display element array having a storage capacitor three times the size, a problem arises in that short circuits between the pixel electrode and the storage capacitor line occur three times as often. Furthermore, when the scanning pulse applied to the gate line is turned off, a punch-through phenomenon occurs due to the parasitic capacitance Cgd between the gate and drain in the thin film field effect transistor, and the potential Vdmn of the drain electrode, that is, the pixel electrode, shifts to the negative side. shift. The magnitude of this shift ΔVlc is calculated using equation (1).

[0007]

Here, Cgd is the parasitic capacitance between the gate and drain, Clc is the capacitance of the liquid crystal capacitor, Cst is the capacitance of the storage capacitor, and ΔVg is the amplitude of the scanning pulse. The problem here is that the capacitances of Cgd and Clc change depending on the voltage. Regarding Cgd,
When the thin film field effect transistor is on, it consists of about 1/2 of the channel capacitance and the capacitance of the overlapping part of the gate electrode and drain electrode, but when the thin film field effect transistor is off, the scanning pulse is below the threshold voltage. Therefore, Cgd is composed only of the capacitance at the overlapping portion of the gate electrode and the source electrode. In equation (1), the larger the gate potential is with respect to the drain potential, the larger ΔVlc becomes. As for Clc, the capacitance value is not constant because the liquid crystal has a dielectric constant that differs depending on the applied potential (has dielectric anisotropy).

As described above, since Cgd and Clc change, the shift amount ΔVlc shown in equation (1) changes variously depending on the applied voltage. It is impossible to set the potential to the optimum value. As a result, a direct current potential is applied to the liquid crystal, causing flickering and burn-in after displaying the same screen for a long period of time, impairing image quality and further accelerating deterioration of the liquid crystal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display element array having a structure that prevents short circuits in storage capacitor sections, and a driving method that eliminates flickering and burn-in phenomena.

[0011]

[Means for Solving the Problems] A thin-film field effect transistor-driven liquid crystal display element array of the present invention includes a plurality of gate lines arranged parallel to each other in a predetermined direction on an insulating substrate;
A plurality of source lines arranged in a direction intersecting the gate line, a thin film field effect transistor arranged corresponding to each intersection position of the gate line and the source line, and a drain of the thin film field effect transistor. The storage capacitor line has a connected pixel electrode, and a storage capacitor line that is arranged parallel to the gate line and has a portion that overlaps a part of the pixel electrode with a gate insulating film and a high-resistance semiconductor layer interposed therebetween.

Further, the method for driving a thin film field effect transistor driven liquid crystal display element array of the present invention includes a plurality of gate lines arranged parallel to each other in a predetermined direction on an insulating substrate, and a plurality of gate lines arranged in a direction crossing the gate lines. a plurality of source lines, a thin film field effect transistor disposed corresponding to each intersection of the gate line and the source line, a pixel electrode connected to the drain of the thin film field effect transistor, and a pixel electrode connected to the drain of the thin film field effect transistor; a storage capacitor consisting of a storage capacitor line arranged parallel to the line and a cover electrode that overlaps the storage capacitor line and is connected to the pixel electrode with a gate insulating film and a high-resistance semiconductor layer therebetween;
N of the thin-film field-effect transistor-driven liquid crystal display element array in which the capacitance value of the storage capacitor is equal to the parasitic capacitance between the gate and drain of the thin-film field-effect transistor;
A correction pulse having a polarity opposite to that of the scanning pulse applied to the Nth gate line and having a delay not exceeding one horizontal scanning line time is applied to the storage capacitor line connected to the Nth gate line.

[0013]

[Operation] By using a high-resistance semiconductor layer in addition to the gate insulating film as the interlayer insulating film of the storage capacitor, it becomes at least a double insulating film, so dust generated during the process and pins in the gate insulating film can be removed. Short circuits between electrodes due to holes can be prevented.

Furthermore, by setting the size of the storage capacitor to be the same as the parasitic capacitance Cgd of the thin film field effect transistor, and applying a correction pulse having the same amplitude and opposite polarity to the scanning pulse as the potential of the storage capacitor line, The shift in pixel electrode potential due to the punch-through phenomenon can be canceled out. A change ΔVlcd in the pixel electrode potential due to a pulse applied to the storage capacitor line is expressed by equation (2).

[0015]

Note that ΔVst is the amplitude of the correction pulse applied to the storage capacitor line. Therefore, if Cst
=Cgd, ΔVgn=ΔVstn, then ΔVlc=Δ
Vlcd is established. A storage capacitor has a gate insulating film and a semiconductor layer sandwiched between a pixel electrode and a storage capacitor line, and has the same structure as the parasitic capacitance of a thin film field effect transistor. When the potential of the storage capacitor line is higher than the potential of the pixel electrode and the threshold voltage, this corresponds to a state where the scanning pulse is higher than the threshold voltage in the thin film field effect transistor and a channel is formed, and the storage capacitor line When the potential of the pixel electrode is lower than the potential of the pixel electrode and the threshold voltage, the scanning pulse becomes lower than the threshold voltage in the thin film field effect transistor.
This corresponds to the channel disappearing and turning off. Therefore, assuming ΔVg=ΔVst, Cst=Cgd holds true in any state.

[0017]

[Embodiment] FIG. 1(a) is a plan view showing one embodiment of the thin-film field effect transistor-driven liquid crystal display element array of the present invention, and FIG. 1(b) is a cross-sectional view taken along the line A-A in FIG. 1(a). It is. 1(N-1), 1N... (N=1, 2,...) are gate lines,
2(M,N), (M=1,2,...,N=1,2,...,)
is the gate electrode, 3(M-1), 3M,... is the source line, 4
is a source electrode, 5 is a drain electrode, 6 (M, N) is a pixel electrode, 7 is a gate insulating film, 8 is a hydrogenated amorphous silicon film with high resistance, 9 is a hydrogenated amorphous silicon film doped with phosphorus, 10 11 is a glass substrate, and 12N is a storage capacitor line.

The structure of the thin-film field-effect transistor-driven image display element array of this embodiment will be explained by describing a specific manufacturing method. First, a chromium film of 0.1 μm is formed on a glass substrate 11 by sputtering, and patterned to form a gate line 1 made of chromium.
(N), . . . , gate electrodes 2 (M, N), . . . and storage capacitor lines 12 are formed. Next, as the gate insulating film 7, a silicon nitride film of 0.3 μm thickness, a hydrogenated amorphous silicon film 8 of 0.2 μm thickness, and a phosphorous-doped hydrogenated amorphous silicon film 9 of 0.04 μm thickness were sequentially formed by plasma chemical vapor deposition. To form a film. Next, a hydrogenated amorphous silicon film 8 and a phosphorous-doped amorphous silicon film 9 are formed.
on the gate electrode 2 (M, N), the gate line 1 (N), the storage capacitor line 12N and the source line 3.
An island is formed at the intersection with (M) and also at the overlap between the pixel electrode 6 (M, N) and the storage capacitor line 12 (N). Then, by a sputtering method, a transparent conductive film of I
After forming a 0.05 μm TO film, the pixel electrode 6 (M, N)
pattern. Further, a 0.4 μm thick chromium film is formed by sputtering, and then patterned to form a source line 3 (M), a source electrode 4, and a drain electrode 5. Following this step, the source electrode 4
By removing the phosphorous-doped amorphous silicon film 9 between the drain electrode 5 and the drain electrode 5, the thin film field effect transistor is completed. Finally, by forming a surface protection film 10 made of silicon nitride, a thin film field effect transistor driven liquid crystal display element array is completed.

As described above, according to the thin-film field-effect transistor-driven liquid crystal display element array having the structure of the present invention, in the storage capacitor section, a gate insulating film, an amorphous silicon semiconductor film, and a phosphorus-doped amorphous silicon film are formed between the electrodes. Since three layers of membrane are inserted, short circuits between electrodes due to dust or pinholes can be prevented. Actually, a liquid crystal display device having this structure and having a diagonal size of 10 inches and driven by a thin film field effect transistor was manufactured. Number of pixels is 40 vertically
0, width 1920, and the overlapping area of the storage capacitor portion is the same as the conventional one. Conventionally, there were 10 or more short circuits in the storage capacitor section, but in the thin film field effect transistor driven liquid crystal display element array having the structure of the present invention, the number of short circuits was 3 or less.

Next, an embodiment of the method for driving a thin film field effect transistor driven liquid crystal display element array according to the present invention will be described. FIG. 2(a) is a plan view of a liquid crystal display element array suitable for driving in one embodiment of the driving method of the present invention.
2(b) is a sectional view taken along line AA in FIG. 2(a), and FIG. 2(c) is a sectional view taken along line BB in FIG. 2(a).

In the figure, 1 (N-1), 1 (N) are gate lines, 2 (M, N) are gate electrodes, 3 (M-1), 3
(M) is a source line, 4 is a source electrode, 5 is a drain electrode, 6 (M, N) is a pixel electrode, 7 is a gate insulating film, 8 is an amorphous silicon film, 9 is an amorphous silicon film doped with phosphorus, 10 is a surface protective film, 11 is a glass substrate, 12N is a storage capacitor wire, and 13 (M, N) is a cover electrode.

First, the structure of a thin film field effect transistor driven liquid crystal display element array used in the driving method of this embodiment will be explained. The difference from the liquid crystal display element array of the above embodiment is that a cover electrode 13 (M, N) is added, and the width, length, and structure of the overlap with the storage capacitor line 12 are different from the gate electrode of the thin film field effect transistor. 2. It is made the same as the overlapping part of the drain electrode 5. Figure 2(b), Figure 2(c)
), when the thin film field effect transistor is cut at the center, the structure on the drain electrode side is the same as the structure of the storage capacitor section. Therefore, Cst=C
It can be gd.

FIG. 3 is an equivalent circuit diagram of one pixel, and FIG. 4 is a timing chart for explaining the driving method. T(M
, N) is a thin film field effect transistor, 14 is a one-pixel liquid crystal capacitor made of liquid crystal, Cst is a storage capacitor, and Cgd is a parasitic capacitance between the gate and drain of the thin film field effect transistor, including the channel capacitance and the gate electrode. and occurs from the overlap of the drain electrodes. Reference numeral 15 indicates a counter electrode arranged with the liquid crystal interposed therebetween, and reference numeral 12N indicates a storage capacitor line 6 (M,N) which indicates a pixel electrode. Further Cstp
is the additional storage capacitor. Although it is necessary for explaining the embodiment described later, it is unrelated to the present embodiment. In an actual liquid crystal display element array, the equivalent circuit shown in FIG. 3 is arranged in a matrix. In FIG. 4, Vgn is a scanning pulse applied to the Nth gate line 1 (N), Vstn is a correction pulse applied to the storage capacitor line, and Vsm is a signal applied to the mth source line 3 (M). The voltage, Vdn, is the potential of the pixel electrode. The correction pulse Vstn has the same amplitude as the scanning pulse Vgn, opposite polarity, and has a delay of less than one horizontal scanning line time (1H). Also, the potential V of the counter electrode
c is the center voltage of the amplitude of the signal voltage Vs.

An embodiment of the driving method according to the present invention will be described with reference to FIGS. 3 and 4. First, in the first field of the video signal, a signal voltage corresponding to the brightness of each display cell is supplied from the source line 3 (M), and the gate line 1 (N
), the thin film field effect transistor T(M,N) is turned on, and the signal voltage is written to the liquid crystal capacitor 14 and the storage capacitor Cst (
The potential is Vdn in FIG. 4). In the first field, it is assumed that the potential of the signal voltage is higher than the potential Vc of the common electrode. During this writing, the correction pulse Vstn applied to the storage capacitor line 12 (N) swings in the opposite direction to the scanning pulse. When the scanning pulse Vgn turns off (goes down), the parasitic capacitance Cgd causes the magnitude Δ shown in the above equation (1) to increase.
The pixel potential Vdn is shifted by Vlc.

However, since the correction pulse Vstn rises immediately after the scanning pulse Vgn is turned off, the pixel potential V
dn is shifted again. Here, Cst=Cgd
, ΔVgn=ΔVstn, so ΔVlc=ΔVlcd
holds true. That is, when the scanning pulse Vgn is off,
The shift received by the potential Vdn of the pixel electrode is caused by the correction pulse V
When stn rises, it is canceled and returns to the original state. Thereafter, the potential Vdn of the pixel electrode decreases somewhat due to the resistance within the liquid crystal capacitor, but is maintained until the next voltage is written in the second field. In the second field of the video signal, the source line 3 is connected as in the first field.
(M) is written into the liquid crystal capacitor 14 and the storage capacitor Cst when a scanning pulse is input to the gate line 1 (N). Note that in the second field, the potential of the signal voltage is lower than the potential Vc of the common electrode. As with the first field, in the middle of writing,
Correction pulse Vstn applied to storage capacitor line 12
swings in the opposite direction to the scanning pulse. When the scanning pulse Vgn turns off (goes down), the equation (
1) The pixel potential Vdn is increased by the magnitude ΔVlc shown in
is shifted. However, immediately after the scanning pulse Vgn turns off, the correction pulse Vstn rises, so the pixel potential Vdn is shifted again by ΔVlcd, which is the magnitude shown by equation (2), and returns to the original state as in the first field. . Thereafter, the potential Vdn of the pixel electrode decreases somewhat due to the resistance within the liquid crystal capacitor, but is maintained until a voltage is written in the next field.

According to the driving method for correcting the shift due to parasitic capacitance as described above, it is possible to prevent as much as possible from applying an asymmetrical voltage or DC voltage to the liquid crystal.

A thin film field effect transistor liquid crystal display device having a diagonal size of 10 inches and having the storage capacitor structure described in this example was fabricated. Number of pixels is 400 vertically and 1 horizontally
It was set at 920. When a liquid crystal panel was driven by the driving method of the present invention, no flickering phenomenon or burn-in phenomenon after displaying the same screen for a long time was observed.

Another structural example of an element array to which the driving method according to the present invention can be applied is shown in FIG. In this structure example, in order to increase the capacitance value of the storage capacitor, an additional storage capacitor electrode 16 is formed on the N-1st gate line 1 (N-1), and the additional storage capacitor Cst
p (Figure 3). In FIG. 3, the broken line portion is the additional storage capacitor Cstp. This additional storage capacitor Cstp improves the charge retention rate in the capacitor system of the liquid crystal capacitor 14 and the storage capacitor Cst, thereby ensuring the voltage applied to the liquid crystal.

In the above description, a hydrogenated amorphous silicon film is used as the high-resistance semiconductor layer, but other semiconductors such as a non-doped polycrystalline silicon film can also be used. When a hydrogenated amorphous silicon film is used, the correction pulse is generated in an external integrated circuit and input to the storage capacitor wiring, requiring multi-terminal connections. but,
If a polycrystalline silicon film is used, the correction pulse generation circuit can be formed on the same glass substrate, which is advantageous in terms of terminal connections compared to the case where a hydrogenated amorphous silicon film is used. Furthermore, although chromium is used as the wiring material, other metals such as aluminum, tantalum, molybdenum, titanium, etc. can also be used. Further, although silicon nitride is used for the gate insulating film and the surface protection film, other insulating films such as silicon dioxide can also be used.

[0030]

As described above, according to the thin-film field-effect transistor-driven liquid crystal display element array of the present invention, short circuits between electrodes in the storage capacitor section are reduced, and manufacturing yield is improved. Furthermore, according to the driving method of the present invention, it is possible to display high-quality images without flickering or burn-in phenomena.

[Brief explanation of the drawing]

FIG. 1 is a plan view (FIG. 1(a)) and a cross-sectional view (FIG. 1(b)) showing one embodiment of a thin-film field-effect transistor-driven liquid crystal display element array according to the present invention.

FIG. 2 is a diagram showing an example of the structure of a liquid crystal display element array suitable for applying one embodiment of the method for driving a thin film field effect transistor-driven liquid crystal display element array of the present invention. Figure 2 (a
) is a plan view, FIG. 2(b) is a sectional view taken along line AA in FIG. 2(a), and FIG. 2(c) is a sectional view taken along line BB in FIG. 2(a).

FIG. 3 is an equivalent circuit diagram of the liquid crystal display element array shown in FIG. 2;

FIG. 4 is a timing chart used to explain one embodiment of a method for driving a liquid crystal display element array according to the present invention.

FIG. 5 is a plan view showing another structural example suitable for applying the method for driving a liquid crystal display element array of the present invention.

[Fig. 6] A plan view showing a conventional liquid crystal display element array (Fig. 6)
(a)) and a cross-sectional view (FIG. 6(b)).

FIG. 7 is an equivalent circuit diagram of a conventional liquid crystal display element array.

FIG. 8 is a timing chart used to explain the operation of a conventional liquid crystal display element array.

[Explanation of symbols]

1 (N-1), 1 (N) Gate line 2 (M, N)
Gate electrode 3 (M-1), 1 (M) Source line 4 Source electrode 5 Drain electrode 6 (M, N) Pixel electrode 7 Gate insulating film 8 Hydrogenated amorphous silicon film 9 Phosphorus-doped hydrogenated amorphous silicon film 10
Surface protective film 11 Glass substrate 12 (N) Storage capacitor wire 13 (M, N) Cover electrode 14 Liquid crystal capacitor 15 Counter electrode 16 Additional storage capacitor electrode

Claims (2)

[Claims] 1. A plurality of gate lines arranged parallel to each other in a predetermined direction on an insulating substrate, a plurality of source lines arranged in a direction intersecting the gate lines, and each intersection of the gate line and the source line. A gate insulator is provided between thin film field effect transistors arranged corresponding to respective positions, a pixel electrode connected to the drain of the thin film field effect transistor, and a part of the pixel electrode arranged parallel to the gate line. 1. A thin-film field-effect transistor-driven liquid crystal display element array, comprising a storage capacitor line and a storage capacitor line having an overlapping portion with a high-resistance semiconductor layer interposed therebetween. 2. A plurality of gate lines arranged parallel to each other in a predetermined direction on an insulating substrate, a plurality of source lines arranged in a direction intersecting the gate lines, and each intersection of the gate line and the source line. Thin film field effect transistors arranged corresponding to positions, a pixel electrode connected to the drain of the thin film field effect transistor, a storage capacitor line arranged parallel to the gate line, and a gate insulating film in between. a storage capacitor consisting of a cover electrode overlapping the storage capacitor line and connected to the pixel electrode via a high-resistance semiconductor layer, the capacitance of the storage capacitor being equal to the gate of the thin film field effect transistor;
A correction pulse having a polarity opposite to the scanning pulse applied to the Nth gate line of the thin-film field effect transistor-driven liquid crystal display element array equal to the parasitic capacitance between the drains and having a delay not exceeding one horizontal scanning line time. A method for driving a thin film field effect transistor driven liquid crystal display element array, characterized in that a voltage is applied to the storage capacitor line connected to the Nth gate line.