JPH04206932A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04206932A JPH04206932A JP33934790A JP33934790A JPH04206932A JP H04206932 A JPH04206932 A JP H04206932A JP 33934790 A JP33934790 A JP 33934790A JP 33934790 A JP33934790 A JP 33934790A JP H04206932 A JPH04206932 A JP H04206932A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- region
- substrate
- gettering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005247 gettering Methods 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 37
- 229910052710 silicon Inorganic materials 0.000 abstract description 37
- 239000010703 silicon Substances 0.000 abstract description 37
- 230000000694 effects Effects 0.000 abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 13
- 239000010408 film Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置及びその製造方法に関し、特にシリ
コン基板を用いる半導体装置の製造方法において、出発
材料である舎シリコン基板の前処理方法及びシリコン基
板構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, in a method for manufacturing a semiconductor device using a silicon substrate, a pretreatment method for a silicon substrate, which is a starting material, and a method for manufacturing a silicon substrate. This relates to the substrate structure.
第2図は例えば月刊Sem1conductor Wo
rld 1987、1(p、 88)に示された従来の
半導体装置の製造の一工程を示す断面図であり、図にお
いて、1はシリコン基板、6はこのシリコン基板lの裏
面に堆積された多結晶シリコン膜である。Figure 2 is an example of the monthly Sem1conductor Wo.
rld 1987, 1 (p, 88). It is a crystalline silicon film.
次に作用について説明する。Next, the effect will be explained.
シリコン基板1の表面に半導体素子を形成する工程にお
いて、シリコン基板lの裏面に堆積された多結晶シリコ
ン膜6の粒界に発生する歪場や格子不整合による歪場か
ゲッタリング源となり、半導体装置の製造工程での汚染
で導入される重金属不純物やNa不純物をシリコン基板
1の表面に形成される素子活性領域から除去、ゲッタす
る。In the process of forming a semiconductor element on the surface of the silicon substrate 1, the strain field generated at the grain boundaries of the polycrystalline silicon film 6 deposited on the back surface of the silicon substrate 1 or the strain field due to lattice mismatch becomes a gettering source, and the semiconductor Heavy metal impurities and Na impurities introduced as a result of contamination during the manufacturing process of the device are removed and gettered from the element active region formed on the surface of the silicon substrate 1.
従来の半導体装置は以上のように構成されているので、
ゲッタリング源がシリコン基板の裏面にあり、表面の活
性領域から距離があり、ゲッタリング効果が小さいとい
う問題点があった。さらに半導体装置の製造工程におい
て、裏面の多結晶シリコン膜が酸化とエツチングにより
しだいに薄くなり、ゲッタリング効果の持続性に問題が
あった。Conventional semiconductor devices are configured as described above, so
The problem is that the gettering source is located on the back surface of the silicon substrate and is far away from the active region on the front surface, resulting in a small gettering effect. Furthermore, in the manufacturing process of semiconductor devices, the polycrystalline silicon film on the back side gradually becomes thinner due to oxidation and etching, which poses a problem in the sustainability of the gettering effect.
この発明は上記のような問題点を解消するためになされ
たもので、素子の活性領域とゲッタリング源を近接させ
ることによりゲッタリング効果を向上させるとともに、
ゲッタリング源である多結晶シリコン膜の薄膜化を防ぎ
、ゲッタリング効果の持続力を高めることのできる半導
体装置とその製造方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it improves the gettering effect by bringing the active region of the device and the gettering source close to each other.
The present invention aims to provide a semiconductor device and a method for manufacturing the same that can prevent a polycrystalline silicon film that is a gettering source from becoming thinner and increase the sustainability of the gettering effect.
本発明に係る半導体装置は、同一シリコン基板表面上に
ゲッタリング源である多結晶シリコン層と、素子形成領
域となる単結晶シリコン層とを有するものである。A semiconductor device according to the present invention has a polycrystalline silicon layer serving as a gettering source and a single crystal silicon layer serving as an element formation region on the same silicon substrate surface.
また、本発明に係る半導体装置の製造方法は、シリコン
基板表面に選択的にイオン注入を行い非晶質化する工程
と、該選択的にイオン注入された基板表面にシリコンを
CVD法等により結晶成長させる工程とを含むものであ
る。Further, the method for manufacturing a semiconductor device according to the present invention includes a step of selectively implanting ions into the surface of a silicon substrate to make it amorphous, and crystallizing silicon on the selectively ion-implanted surface of the substrate by a CVD method or the like. The method includes a step of growing.
この発明における半導体装置は、多結晶シリコン層と単
結晶シリコン層とを同一基板表面上に有し、多結晶シリ
コン層がゲッタリンク源となり、単結晶シリコン層が素
子形成領域となるため、ゲッタリンク源と素子形成領域
が近接してゲッタリング効果が向上し、また多結晶シリ
コン層の製造工程における薄膜化を防いでゲッタリング
効果の持続性か高められる。The semiconductor device according to the present invention has a polycrystalline silicon layer and a single-crystalline silicon layer on the same substrate surface, the polycrystalline silicon layer serves as a getter link source, and the single-crystalline silicon layer serves as an element formation region. The gettering effect is improved because the source and the element formation region are close to each other, and the sustainability of the gettering effect is increased by preventing thinning of the polycrystalline silicon layer during the manufacturing process.
また、この発明における半導体装置の製造方法は、シリ
コン基板上に選択的にイオン注入を行って非晶質層とし
、その後基板上に基板と同一のシリコンを結晶成長させ
たので、前記非晶質層」二にはゲッタリンク源となる多
結晶層、イオン注入を行っていない部分には単結晶層を
得られる。Further, in the method for manufacturing a semiconductor device according to the present invention, ions are selectively implanted onto a silicon substrate to form an amorphous layer, and then the same silicon as the substrate is crystal-grown on the substrate, so that the amorphous layer is formed on the silicon substrate. A polycrystalline layer serving as a getter link source is obtained as layer 2, and a single crystalline layer is obtained in the portion where ions are not implanted.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例を示す半導体装置の製造工程
を示す概略図である。図において、1はシリコン基板、
2はシリコン基板1」二のマスク、3はマスク2により
選択的に注入されるイオン、4は注入イオン3により非
晶質化された層、5は化学気相成長法(Chemica
l Vapor Deposition:CVD)によ
り成長したシリコン単結晶(エピタキシャル層)、6は
CVDにより成長したシリコン多結晶層、7は非晶質層
4が結晶回復する際に残された結晶欠陥層、8は素子分
離の酸化膜、9はゲート電極、10はソース/ドレイン
領域、11は層間絶縁膜、12は配線層である。FIG. 1 is a schematic diagram showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a silicon substrate,
2 is a mask for the silicon substrate 1'', 3 is an ion implanted selectively by the mask 2, 4 is a layer made amorphous by the implanted ions 3, and 5 is a chemical vapor deposition method (Chemical vapor deposition method).
1 is a silicon single crystal (epitaxial layer) grown by Vapor Deposition (CVD), 6 is a silicon polycrystalline layer grown by CVD, 7 is a crystal defect layer left when the amorphous layer 4 recovers the crystal, and 8 is a An oxide film for element isolation, 9 a gate electrode, 10 a source/drain region, 11 an interlayer insulating film, and 12 a wiring layer.
第1図(a)において、シリコン基板1にマスク2をパ
ターニングして選択的にAr+イオン3を150 k
e V、 I x 10 I6atoms/ci注入
する。注入された領域4は非晶質化される。次に第1図
(b)に示すように、マスク2を除去した後、CVD法
により、850’Cてシリコンを厚さ約500nm成長
させる。イオン3か注入されていない領域では、シリコ
ンはエピタキシャル成長し単結晶N5となる。イオン3
が注入された領域では、非晶質層4の上にシリコンが堆
積されるため多結晶層6となる。非晶質層4はCVDの
際、結晶回復するが、多結晶層6の下に深さ250nm
におよぶ高密度の結晶欠陥層7を発生させる。上記のよ
うに形成された半導体基板を用いて、第1図(C)に示
すように、単結晶領域5はその上に素子分離酸化膜8゜
ゲート電極9.ソース/ドレイン領域10.層間絶縁膜
II及び配線層12などを形成し、半導体素子の活性領
域として使用する。多結晶領域6は単結晶半導体基板を
使用しない領域、例えばスクライブライン、ワイヤボン
ドのパッド及び広い素子分離領域などとして配置する。In FIG. 1(a), a mask 2 is patterned on a silicon substrate 1 and Ar+ ions 3 are selectively injected at 150 k
e V, I x 10 I6 atoms/ci injection. The implanted region 4 becomes amorphous. Next, as shown in FIG. 1(b), after removing the mask 2, silicon is grown to a thickness of about 500 nm at 850'C by CVD. In the region where no ion 3 is implanted, silicon grows epitaxially and becomes single crystal N5. ion 3
In the region where silicon is implanted, silicon is deposited on the amorphous layer 4, resulting in a polycrystalline layer 6. The amorphous layer 4 undergoes crystalline recovery during CVD, but a depth of 250 nm is formed under the polycrystalline layer 6.
A high-density crystal defect layer 7 is generated. Using the semiconductor substrate formed as described above, as shown in FIG. Source/drain region 10. An interlayer insulating film II, a wiring layer 12, and the like are formed and used as an active region of a semiconductor element. The polycrystalline region 6 is arranged as a region where the single crystal semiconductor substrate is not used, such as a scribe line, a wire bond pad, and a wide element isolation region.
このように本実施例においては、シリコン基板表面を選
択的にイオン注入により非晶質層とし、該シリコン基板
上にシリコンを結晶成長させることにより、非晶質層部
分には多結晶層を、そうでない部分には単結晶層を形成
したので、同一シリコン基板表面上に多結晶層と単結晶
層の両方を得られる。また、その同一基板表面上の多結
晶層と単結晶層とを各々ゲッタリング源、素子活性領域
として用いるので、ゲッタリング源と素子活性領域か近
接しゲッタリング効果を上げることができるとともに、
製造工程での多結晶シリコン膜の薄膜化を防いでゲッタ
リング効果の持続性を高めることかできる。In this example, the surface of the silicon substrate is selectively made into an amorphous layer by ion implantation, and silicon is crystal-grown on the silicon substrate, so that a polycrystalline layer is formed in the amorphous layer portion. Since a single crystal layer was formed in the other parts, both a polycrystalline layer and a single crystal layer can be obtained on the same silicon substrate surface. In addition, since the polycrystalline layer and the single crystal layer on the same substrate surface are used as a gettering source and an element active region, respectively, the gettering source and the element active region are brought close to each other, and the gettering effect can be increased.
It is possible to prevent the polycrystalline silicon film from becoming thinner during the manufacturing process and increase the sustainability of the gettering effect.
なお、」−記実施例ではAr”イオン3について示した
か、半導体装置の性能の面で問題を与えないイオンであ
ればいかなるイオン種でもよい。またイオン注入条件お
よびシリコン成長条件についても、単結晶領域5と多結
晶領域6とを同一基板l上に形成されるものであればい
かなる条件でもよい。Note that in the example described above, Ar'' ion 3 is shown, but any ion species may be used as long as it does not cause any problems in terms of the performance of the semiconductor device. Also, regarding the ion implantation conditions and silicon growth conditions, single crystal Any conditions may be used as long as the region 5 and the polycrystalline region 6 are formed on the same substrate l.
また、イオン3はなんらかの薄膜を通して注入してもよ
い。これにより多結晶領域6の状態や結晶欠陥層7の状
態を変えることができる。Alternatively, the ions 3 may be implanted through some kind of thin film. Thereby, the state of the polycrystalline region 6 and the state of the crystal defect layer 7 can be changed.
上記実施例ではマスク2を用いたイオン注入により選択
的に非晶質層4を形成したか、イオンビームの走査によ
り非晶質層4を形成してもよい。In the above embodiment, the amorphous layer 4 was selectively formed by ion implantation using the mask 2, or it may be formed by scanning an ion beam.
また電子、中性粒子、電磁波(光)、及び固体粒子など
を用いて単結晶領域5と多結晶領域6を形成してもよい
。Furthermore, the single crystal region 5 and the polycrystal region 6 may be formed using electrons, neutral particles, electromagnetic waves (light), solid particles, or the like.
上記実施例ではシリコン基板1について説明したが、G
eなと他の単体半導体基板及びGaAsなと化合物半導
体基板に適用してもよい。In the above embodiment, the silicon substrate 1 was explained, but G
The present invention may be applied to other single semiconductor substrates such as e, and compound semiconductor substrates such as GaAs.
また上記実施例を従来のゲッタリング手法と併用すれば
、より強いゲッタリング効果を期待することができる。Further, if the above embodiment is used in combination with a conventional gettering method, a stronger gettering effect can be expected.
以」二のように本発明によれば、従来の半導体装置にお
けるゲッタリング源が半導体基板の裏面、または基板の
深い内部にあったのに対して、ゲッタリング源である多
結晶層と結晶欠陥層を基板表面に形成し、素子形成領域
に隣接させたことにより、ゲッタリング効果が向上し、
素子が形成される単結晶層において、素子の電気特性に
悪影響を与える不純物と結晶欠陥が低減され、素子の電
気特性が極めて良好になる。従って、電気特性を著しく
向上させることかできるとともに、素子の歩留まりを飛
躍的に向上させることができる効果がある。As described above, according to the present invention, the gettering source in the conventional semiconductor device was located on the back surface of the semiconductor substrate or deep inside the substrate, whereas the gettering source is located in the polycrystalline layer and crystal defects, which are the gettering sources. By forming the layer on the substrate surface and adjacent to the element formation area, the gettering effect is improved.
In the single crystal layer in which the device is formed, impurities and crystal defects that adversely affect the electrical characteristics of the device are reduced, resulting in extremely good electrical characteristics of the device. Therefore, the electrical characteristics can be significantly improved, and the yield of the device can be dramatically improved.
また、本発明によれば、シリコン基板表面上に選択的に
イオン注入した後、シリコンを結晶成長させるようにし
たので、素子形成領域となる単結晶層と、ゲッタリング
源となる多結晶層とを同一基板表面上に形成できる効果
がある。Further, according to the present invention, silicon is grown as a crystal after selectively implanting ions onto the surface of the silicon substrate, so that a single crystal layer that becomes an element formation region and a polycrystalline layer that becomes a gettering source are formed. This has the advantage that both can be formed on the same substrate surface.
第1図はこの発明の一実施例による半導体装置の製造工
程を示す断面の概略図、第2図は従来の半導体装置の製
造の一工程を示す断面の概略図である。
図において、1はシリコン基板、2はマスク、3は注入
イオン、4は非晶質層、5は単結晶層(エピタキシャル
層)、6は多結晶層、7は結晶欠陥層、8は素子分離酸
化膜、9はゲート電極、IOはソース/ドレイン領域、
11は層間絶縁膜、12は配線層である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view showing a process of manufacturing a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is a mask, 3 is implanted ions, 4 is an amorphous layer, 5 is a single crystal layer (epitaxial layer), 6 is a polycrystalline layer, 7 is a crystal defect layer, and 8 is element isolation oxide film, 9 is a gate electrode, IO is a source/drain region,
11 is an interlayer insulating film, and 12 is a wiring layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
晶領域と、ゲッタリング源となる多結晶領域とを有する
ことを特徴とする半導体装置。(2)半導体装置の製造
方法において、 半導体基板上の表面層を選択的に非晶質化する工程と、 前記半導体基板と同一材料の半導体層を基板全面に結晶
成長させる工程とを備えたことを特徴とする半導体装置
の製造方法。(1) A semiconductor device characterized by having a single crystal region serving as a semiconductor element formation region and a polycrystalline region serving as a gettering source on the same semiconductor substrate surface. (2) A method for manufacturing a semiconductor device, comprising a step of selectively amorphizing a surface layer on a semiconductor substrate, and a step of growing crystals of a semiconductor layer made of the same material as the semiconductor substrate over the entire surface of the substrate. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33934790A JPH04206932A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33934790A JPH04206932A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04206932A true JPH04206932A (en) | 1992-07-28 |
Family
ID=18326593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33934790A Pending JPH04206932A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04206932A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5734195A (en) * | 1993-03-30 | 1998-03-31 | Sony Corporation | Semiconductor wafer for epitaxially grown devices having a sub-surface getter region |
JP2000323484A (en) * | 1999-05-07 | 2000-11-24 | Mitsubishi Electric Corp | Semiconductor device and semiconductor memory |
US6372611B1 (en) | 1997-01-24 | 2002-04-16 | Nec Corporation | Semiconductor manufacturing method including gettering of metal impurities |
JP2005129559A (en) * | 2003-10-21 | 2005-05-19 | Oki Electric Ind Co Ltd | Method for removing impurity in semiconductor wafer and semiconductor device |
EP1533847A1 (en) * | 2002-06-26 | 2005-05-25 | Nikon Corporation | Solid imaging device |
US7470944B2 (en) | 2002-06-26 | 2008-12-30 | Nikon Corporation | Solid-state image sensor |
-
1990
- 1990-11-30 JP JP33934790A patent/JPH04206932A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5734195A (en) * | 1993-03-30 | 1998-03-31 | Sony Corporation | Semiconductor wafer for epitaxially grown devices having a sub-surface getter region |
US5874348A (en) * | 1993-03-30 | 1999-02-23 | Sony Corporation | Semiconductor wafer and method of manufacturing same |
US6140213A (en) * | 1993-03-30 | 2000-10-31 | Sony Corporation | Semiconductor wafer and method of manufacturing same |
US6372611B1 (en) | 1997-01-24 | 2002-04-16 | Nec Corporation | Semiconductor manufacturing method including gettering of metal impurities |
JP2000323484A (en) * | 1999-05-07 | 2000-11-24 | Mitsubishi Electric Corp | Semiconductor device and semiconductor memory |
EP1533847A1 (en) * | 2002-06-26 | 2005-05-25 | Nikon Corporation | Solid imaging device |
EP1533847A4 (en) * | 2002-06-26 | 2007-02-21 | Nikon Corp | Solid imaging device |
US7470944B2 (en) | 2002-06-26 | 2008-12-30 | Nikon Corporation | Solid-state image sensor |
JP2005129559A (en) * | 2003-10-21 | 2005-05-19 | Oki Electric Ind Co Ltd | Method for removing impurity in semiconductor wafer and semiconductor device |
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