JPH04196813A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a large delay amount with a high resolution by preparing a coarse delay amount which decides the main frame of the desired delay amount based on an input signal, and preparing residual fine delay amounts by a conventional delay equipment. CONSTITUTION:When the input signal is inputted to a coarse delay part 10, an arbitrary oscillator 2 starts the oscillation by a prescribed frequency, and the oscillate output is inputted to a 1/n frequency divider 3, and divided into a prescribed value. The divided signal is compared with a set value by a comparator 4, and when the divided signal is equal to the set value, a coarse delay output is outputted from the comparator 4. The timing in which this coarse delay output is outputted is turned into the delay amount D of the main frame of the desired delay amount. The coarse delay output is inputted to a fine delay part 20, a fine delay (d) set in the fine delay part 20 is added to the coarse delay output, and a signal having a final delay amount T is outputted from this fine delay part 20. Thus, the large delay amount of the delay signal having the high resolution can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a delay circuit that arbitrarily delays a pulse signal.
In particular, the present invention relates to a delay circuit that can easily realize a large amount of delay while maintaining high resolution.

[Prior Art] Delay circuits that delay input signals are used in a variety of fields. In particular, a delay device called a programmable delay is used in a pulse delay circuit that arbitrarily delays a pulse signal. This uses a very short delay time as a unit of resolution, and uses this unit as a step so that a delay time several tens of times larger than the unit delay time can be obtained arbitrarily and with high resolution. Since this type of delay device usually has a coil as its main element, it is larger than electronic components such as ICs, takes up a relatively large space when mounted on a circuit board, and is expensive.

For example, there is currently a device that can program a maximum delay amount of 32 ns in 64 ways (6-bit configuration) in 0.5 ns increments, but there is no device that can realize a delay as large as several 100 ns with a single device.

For this reason, conventionally, for example, when the period is about 500 pS,
If you want to delay an input signal with a pulse width of lS by about 400 pS with a resolution of 500 pS, connect 13 programmable delays in series with a maximum delay of 32 ns as described above, and set 12 of them to the maximum delay time of 32 ns. The method used was to use one for the delay amount and use the remaining one for fine adjustment.

[Problems to be Solved by the Invention] As described above, there is currently no delay circuit that can provide a large amount of delay and high resolution. For this reason, either a delay method using multiple delay devices such as a programmable full delay was adopted, or if the second delay method was adopted, there were the following drawbacks.

(1) When trying to obtain high resolution with a large amount of delay,
Since we have no choice but to rely on delay devices that provide high resolution, the entire amount of delay must be covered by the series connection of delay devices.
Since the maximum amount of delay that can be obtained per unit is small, a large number of delay devices are required, which takes up a large amount of space and is very expensive.

(2) When reducing the amount of delay, this can be done by simply changing the pit signal of the program, but when increasing the amount of delay, it is necessary to further increase the number of delay devices.

(3) It is difficult to easily obtain an arbitrary amount of delay with high resolution.

An object of the present invention is to form, based on an input signal, a coarse adjustment delay amount that determines a general outline of a desired delay amount, and to form the remaining fine adjustment delay amount using an existing delay device. It is an object of the present invention to overcome the drawbacks and provide a delay circuit which has a simple structure and can obtain an arbitrary amount of delay with high resolution.

[Means for Solving the Problems] The delay circuit of the present invention has a fine delay amount that determines the resolution of the desired delay amount, and has a fine delay section that has a small delay amount but high resolution, and a fine adjustment delay section that determines the resolution of the desired delay amount. Of these, it receives the coarse adjustment delay amount which is the large amount of delay, and the delay amount can be set to be larger than the delay amount that can be produced by the fine adjustment delay section, and it is equipped with a coarse adjustment delay section whose resolution is not so high. . It is preferable that the fine adjustment delay section has a variable delay amount, but it may have a fixed delay amount.

This coarse adjustment delay section receives an input signal or tri-power, and when this input signal is input, it oscillates and outputs an output with a period corresponding to the delay amount of the fine adjustment delay section. Comparison of a frequency divider that divides the frequency to obtain a delay amount and outputs a divided output, and a frequency divider that compares the divided output of this frequency divider with a setting value corresponding to the coarse delay amount and outputs a coarse delay output. It consists of a container.

Any amount of delay can be obtained by changing the frequency division value of the frequency divider and the set value of the comparator.

Then, by adding the fine delay amount of the fine delay section to the coarse delay output of the coarse delay section, a large delay amount can be obtained with high resolution.

Here, it is desirable that the period of the output from the oscillator corresponding to the delay amount of the fine delay section has a frequency close to the maximum delay amount that the fine delay section can output. This is because if the delay amount is larger than the maximum delay amount, there is a possibility that the desired delay amount cannot be covered, and if it is smaller than the maximum delay amount, an even higher frequency division will be required.

Further, in order to frequency divide the output of the oscillator so as to obtain a rough adjustment delay amount corresponding to a desired delay amount, the oscillation output may be counted.

[Operation] When an input signal enters the coarse adjustment delay section, the oscillator starts oscillating at a predetermined frequency, and the oscillation output enters the frequency divider and is divided into a predetermined value. The frequency-divided signal is compared with a set value by a comparator, and when it becomes equal to the set value, a rough adjustment delay output is output from the comparator. The timing at which this rough adjustment delay output is output becomes the approximate delay amount of the desired delay amount. The coarse adjustment delay output enters a fine adjustment delay section, where a set fine adjustment delay is added, and a signal with the final amount of delay is output. Since the fine delay finally added has high resolution, the delayed signal has a large delay amount and high resolution.

oral example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the delay circuit of the present invention, and the delay circuit includes a coarse adjustment delay unit 10 that obtains a rough delay amount of a desired delay amount.
and a fine adjustment delay section 20 that accurately adjusts the desired amount of delay.

The coarse adjustment delay section 10 is composed of a waveform converter 1, an arbitrary oscillator 2, a frequency divider 3, and a comparator 4.

The waveform converter 1 narrows the pulse width of the input signal by differentiating the input pulse signal, and outputs a trigger force that can reliably trigger the arbitrary oscillator 2 at the next stage. The waveform converter 1 may be omitted if direct triggering is possible. The input pulse signal may have a repetitive waveform or a single waveform.

The arbitrary oscillator 2 oscillates in response to the trigger output from the waveform converter 1. The oscillation frequency can be set arbitrarily, and here it is set to a cycle equal to the maximum delay amount of delay device 5, which will be described later.

Specifically, the arbitrary oscillator 2 can be configured with an oscillator using a delay line or a monostable multivibrator, or if relatively high delay accuracy is required, a more accurate and stable delay line can be used. An oscillator with a

The frequency divider 3 divides the frequency of the oscillation output of the arbitrary oscillator 20 to 1/n to provide m frequency-divided outputs. It can be configured as a counter; for example, if it is configured as 4 bits, the frequency can be divided by a maximum of 1/16. The amount of delay can be adjusted by changing the bit configuration and frequency division value.

Comparator 4: Compares the m-hit frequency division output of the frequency divider 3 and the m-bit setting value, and outputs a comparison output when they match. The set value is set to a rough adjustment delay amount close to the desired delay amount within the range of m hits. By changing this value, the amount of delay can be changed arbitrarily within the range of frequency division. The coarse adjustment delay amount is the maximum value that is an integral multiple of the maximum delay amount of the delay device 5 and does not exceed the desired delay amount. It is called "coarse adjustment" because it indicates the general range of the desired amount of delay.

The fine adjustment delay unit 20 is composed of a delay unit 5 and a waveform repair unit 6.

The delay device 5 adds a fine delay amount to delay the coarse delay output from the comparator 4 by an additional ζ. The fine adjustment delay amount is the delay amount within the delay range that can be output by the delay device 5, and is the delay amount added to the coarse adjustment delay amount in order to obtain the desired delay fi. As described above, the delay unit 5 is a programmable delay that can arbitrarily output a delay time several tens of times larger than a unit delay time and can provide high resolution.

The amount of delay can be set arbitrarily by combining the utl and p hit signals. Here, block programming is performed to obtain the remaining delay amount obtained by subtracting the rough adjustment delay amount from the desired delay amount.

The waveform restorer 6 returns the delayed output output from the delay device δ to the same pulse width as the original input pulse signal, and outputs a final delayed output. Note that this waveform repair device 6 is provided as necessary.

Now, the operation of the circuit with the above configuration will be explained using FIG. 2.

When the input pulse signal (FIG. 2(a)) enters the coarse adjustment delay unit 10, it is differentiated by the waveform converter 1 and converted into a trigger output (FIG. 2(b)). The arbitrary oscillator 2 starts oscillating at a predetermined period set in advance by the trigger output.
), the oscillation output is divided into a predetermined value by the frequency divider 3 (Fig. 2 (d). The divided signal is compared with the set value by the comparator 4, and when it becomes equal to the set value A coarse adjustment delay output is output from the comparator 4 (Fig. 2 (e)).The timing at which this coarse adjustment delay output is output determines the approximate delay amount of the desired delay amount.The coarse adjustment delay output is output from the fine adjustment delay section. 20, the fine adjustment delay d set here is added (FIG. 2(f)), the signal is repaired by the waveform repairer 6, and a signal with the final delay amount T is output (FIG. 2(f)). (d)) Since the fine adjustment delay finally added has high resolution, the delayed signal has a large delay amount and high resolution.

Note that when the coarse adjustment delay output of the comparator 4 is output, this signal is applied to the arbitrary oscillator 2 and the frequency divider 3 as a stop signal to stop oscillation and frequency division. This is to reset the circuit and prevent malfunction.

In this way, the input signal can be delayed by the maximum number of bits of the comparator. In addition, design changes are easy because any delay amount can be obtained by adjusting the frequency division value of the frequency divider and the set value of the comparator. Note that since the circuit-specific delay amount is known in advance, the influence of the circuit delay can be eliminated by designing a delay that takes this into account.

Next: A specific example will be described in which an input signal with a pulse width of 50 ns is delayed by 400 ns. As the delay device 5, the previously described programmable delay with a resolution of 0.5 ns and a maximum delay amount of 32 nS is used. The oscillation frequency of the arbitrary oscillator 2 is set to 32 ns, which is the same as the maximum delay amount of the delay device 5, the frequency division value of the frequency divider 3 is set to 1/16 of the 4-bit configuration, and the comparator 4 is 4-bit configured.゛The setting value is 12. Also, the delay value of the programmable delay is 16ns (C), 5ns x 32)
Set to . As a result, the following relationship is obtained: associated delay amount = coarse adjustment delay amount 384 ns + fine adjustment delay amount 16n 5 = 400 ns. That is, a large delay of 400 nS can be obtained with 500 ps resolution.

As described above, when using the delay circuit according to the present invention, when realizing a large amount of delay with high resolution, only one delay device takes up space, unlike conventional devices that require many delay devices connected in series. This makes it possible to greatly simplify the structure.

Further, since the amount of delay can be adjusted arbitrarily, it is possible to provide versatility, and in that case, the coarse adjustment delay section and the fine adjustment delay section can be hybridized and provided as one delay circuit. In particular, when the arbitrary oscillator is configured with a monostable multivibrator, the rough adjustment delay section can be integrated into an IC, which is extremely effective in reducing size and cost. Also, 1
Even if the delay is set to a large value of 00 μs or 1000 μs, a high resolution of 0°5 ns can always be obtained. In theory, infinite delays are possible by changing the number of bits or settings of the frequency divider and comparator.

Note that the present invention can arbitrarily and significantly delay not only repetitive waveforms but also single waveforms.

Further, in the embodiment, the delay device is placed at the later stage, but the delay device may be placed at the earlier stage. Especially L for color TV.
Near testers that measure SI and the like require a large delay in order to generate timing pulses, so applying the present invention to such measurement circuits has great merits.

[Effects of the Invention] According to the present invention, a coarse adjustment delay section that determines a general range of the desired delay amount is formed based on the input signal, and the remaining fine adjustment delay sections are formed using existing delay devices. Therefore, although the structure is simple, a large amount of delay can be obtained arbitrarily and with high resolution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the delay circuit of the present invention,
FIG. 2 is a timing waveform diagram of the block diagram shown in FIG. 1. 2... Arbitrary oscillator, 3... Frequency divider, 4... Comparator, 5... Delay unit, 10... Coarse adjustment delay unit, 20...
Fine delay section.

Claims (1)

[Scope of Claims] A fine adjustment delay section capable of fine adjustment to a desired amount of delay and having high resolution, and a coarse adjustment delay section capable of coarse adjustment to a desired amount of delay and having low resolution; The delay section includes an oscillator that oscillates in response to an input signal and outputs an output with a period corresponding to the delay amount of the fine adjustment delay section, and an oscillator that divides the output of this oscillator so as to obtain a coarse adjustment delay amount that corresponds to the desired delay amount. It consists of a frequency divider that outputs a frequency divided output, and a comparator that compares the divided output of this frequency divider with a set value corresponding to the coarse adjustment delay amount and outputs a coarse adjustment delay output. A delay circuit characterized in that the fine delay amount of the fine delay section is added to the coarse delay output of the coarse delay section.