JPH04120912A - Multichannel digital/analog converter and test method for the converter - Google Patents

Abstract

PURPOSE:To shorten time for testing a D/A converter by providing a switchboard circuit for connecting or disconnecting a potential line group and nodes in the respective steps of a 2<n>R type radder resistance circuit. CONSTITUTION:A power supply voltage VDD is supplied to the gate terminals of NMOS transistors T10-T13, and the transistors T10-T13 are turned on. Next, digital signals are inputted to complementary signal lines D10, D10, D11 and D11, potential lines S1-S4 in a potential line group S are successively selected and it is tested whether an analog signal divided by a radder resistance circuit 3 is normally outputted or not. When it is confirmed by this test that a test pattern signal X is normally outputted from an output line 4 of a decoder D2, it can be confirmed that the decoder D2 is normally operated. Thus, the operation test of the decoder D2 by turning off the transistors T10-T13 after executing the DC measurement of a decoder D1 can be executed by the test pattern signal X, and time can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding a multi-channel digital-to-analog converter, D/A
In order to shorten the test time of the converter, a 2nR type ladder resistor circuit that divides the external voltage and the above-mentioned 2.
A potential line group consisting of a plurality of potential lines provided corresponding to the nodes of each stage of the nR type ladder resistance circuit, and a plurality of potential line groups connected in parallel to the potential line group and each having one output line. a selection circuit, and each selection circuit selects one of the potential lines from the potential line group based on an n-bit digital input signal and connects it to the output line of the selection circuit. The digital-to-analog converter is configured to include a switching circuit for connecting or disconnecting the potential line group and the nodes of each stage of the 2nR type ladder resistance circuit.

[Industrial Application Field] The present invention relates to a multi-channel digital-to-analog converter (hereinafter referred to as a D/A converter).

In recent years, the information handled by various devices and systems has increasingly become digital, but the content that is ultimately controlled remains analog. For example, in televisions, videos, etc., color, sound, brightness, etc. are used as analog signals, and in industrial robots in the FA field, etc., arm angle, movable distance, etc. are used as analog signals. Accordingly, various A converters have been developed, but as the number of bits and channels increases, it has become more complicated to test the operation of D/A converters.

[Prior Art] Conventionally, the configurations of ladder resistors built into D/A converters can be roughly classified into two types: R-2nR type and 2nR type. The R-2nR method requires one ladder resistor for each channel, and therefore, in the case of multiple channels, for example, N channels, N R-2nR ladder resistors are required. On the other hand, in the 2nR system, N-channel D
/A converter requires only one 2nR ladder resistor. Therefore, when a plurality of R2nR2nR channels are used, a large decoder area is required, and a 2nR type D/A converter is more efficient because it requires a smaller chip area when used.

Here, FIG. 4 shows a D/A converter constructed using the 2nR method. Two channel decoders D1 and D2 constituting a decoder group F are provided on the chip. or,
High potential side and low potential side reference voltage V ref+,
A ladder resistance circuit 3 consisting of four stages of resistors R1 to R4 to which V ref- is applied is provided, and each of the resistors R1 to R4
The applied voltage can be divided into four by R4.

Potential lines 81 to S4 are connected to each node N1 to N4 of the ladder resistance circuit 3, and a potential line group S is configured by these. This potential line group S is connected to each of the decoders D1 and D2.

Further, the decoder D1 has a 2-bit complementary signal line D10.
．． r510. D11. Continuity lines A1 to A4 are connected to correspond to the potential lines 81 to S4.

The conduction line A1 includes an NMOS transistor Tl.
, T2 are connected in series, the gate terminal of the NMO3I-transistor Tl is connected to the complementary signal line DIO, and the gate terminal of the NMOS transistor T2 is connected to the complementary signal line Dll.

NMOS transistors T3 and T4 are connected in series to the conduction line A2, and NMOS transistors T3 and T4 are connected in series to the complementary signal line 1510.
3) The gate terminal of transistor T3 is connected to complementary signal line Dll.
The gate terminal of the NMOS transistor T4 is connected to the gate terminal of the NMOS transistor T4.

Further, the conduction line A3 is connected to an NMOS transistor T5. T
6 are connected in series, and the complementary signal line DIO is connected to the complementary signal line DIO.
The gate terminal of the OS transistor T5 is connected to the complementary signal line r5.
11 is connected to the gate terminal of the NMOS transistor T6.

Further, the conduction line A4 includes an NMOS transistor Tl,
The gate terminal of the NMOS transistor T1 is connected to the complementary signal line r510, and the gate terminal of the NMOS transistor T8 is connected to the complementary signal line 1)11. Further, the conduction lines A1 to A4 are connected to the output line 4, respectively.

The configuration of the decoder D2 is the same as that of the decoder D1, so the same number will be given and the explanation will be omitted.
2 complementary signal line D20. l520. D21°r52
1 is different from the complementary signal line DIO, lN10°Dll, 1511 of the decoder DI.

This result, each complementary signal line D 10. r510; D
11. Dill, D20. r520. D21. 'r5
NMOS transistor T based on the 21 note signal
1 to T8 are controlled to select the conduction lines A1 to A4, and one potential line 81 to S4 among the potential lines 81 to S4 is connected to the output line 4.
connected to. Then, the resistance R1 of the ladder resistance circuit 3 ~
The voltage divided by R4 is output from the output line 4.

[Problems to be Solved by the Invention] However, when a D/A converter with N channels using a 2nR ladder resistor is shipped, it is necessary to test whether it operates normally. Therefore, it is necessary to measure 2" (n is the number of bits) voltages for each channel, and measurements for N channels. As a result,
In the above-mentioned 2-bit, 2-channel D/A converter, 22×2=8 DC measurements are performed.

However, for example, in the case of a 10-bit IO channel, 2
"xlO = 10,240 voltage measurements must be performed. Therefore, in the case of multiple bits and multiple channels, there is a problem that the number of tests to be performed increases and the test time becomes extremely long.

The present invention has been made in order to solve the above problems, and its purpose is to provide a D/A converter and its inspection method that can shorten the test time of the D/A converter. .

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a 2nR type ladder resistance circuit that divides an external voltage, and a plurality of 2nR type ladder resistance circuits provided corresponding to nodes at each stage of the 2nR type ladder resistance circuit. It consists of a potential line group consisting of potential lines, and a plurality of selection circuits each connected in parallel to the potential line group and each having one output line, and each selection circuit receives an n-bit digital human input signal. In the multi-channel digital-to-analog converter, any one of the potential lines from the potential line group is selected and connected to the output line of the selection circuit based on the potential line group and the 2nR type rata resistor. The configuration includes a switching circuit for connecting or disconnecting nodes at each stage of the circuit.

[Operation] Therefore, according to the present invention, the nodes of each stage of the 2nR type ladder resistance circuit that divides the external voltage by the switching circuit can be disconnected from and connected to the potential line group.

Then, with the switching circuit connecting the nodes of each stage of the 2nR type ladder resistance circuit and the potential line group, a digital signal is input to the reference selection circuit, and one potential line from the potential line group is sequentially selected. do. Then, the potential line is connected to the output line, and the voltage divided by the 2nR type ladder resistance circuit is output to the output line.

Thereafter, a digital signal for selecting the same potential line is input to the reference selection circuit and another selection circuit to be tested with the nodes of each stage of the ladder resistance circuit and the potential line group separated by the switching circuit. If a test signal is input from the output line of the reference selection circuit and a test signal is output from the output line of another selection circuit, it is possible to test whether the other selection circuits operate normally.

Also, with the notes of each stage of the 2nR type ladder resistance circuit and the potential line group separated by the switching circuit, a digital signal for selecting the same potential line between each selection circuit is input to the selection circuit, and one If a test signal is input from the output line of a selection circuit and a test signal is output from the output line of another selection circuit, it can be confirmed that the same potential line has been selected.

[Embodiment] An embodiment of a multi-channel D/A converter embodying the present invention will be described below with reference to FIG. Incidentally, the same components as those in the conventional example are given the same numbers and the explanation thereof will be omitted.

As shown in FIG. 1, between the potential lines 31-84 and each node N1 to N4 of the 2nR type ladder resistance circuit 3, the potential line group S and the nodes N1 to N4 are connected or disconnected (NMO3).
Transistors TIO to T13 are connected, and the gate terminal of each NMOS transistor TIO to T13 is connected to a power supply voltage VD.
T) is supplied.

Therefore, the power supply voltage VDD is
When supplied to the gate terminals of O~T13, NMO8I-
The transistors TIO to T14 are turned on, and the nodes N1 to N4 of the 2nR type ladder resistance circuit 3 are connected to the conduction lines A1 to A4 of the decoders D1 and D2 via the potential lines 81 to S4. Moreover, each NMOS transistor T10 to T13
When power supply voltage VDD is no longer supplied to the gate terminal of
NMOS transistors TIO~T13 are turned off and 2nR
Each node N1 to N4 of the type ladder resistance circuit 3 and each potential line 8
1 to S4 are separated.

The operation and testing method of the 2-bit, 2-channel D/A converter configured as described above will be explained.

A DC measurement to test whether the decoder DI operates normally is performed in the following procedure. First, the power supply voltage VDD is supplied to the gate terminals of the NMOS transistors TIO to T13 to turn on the NMOS transistors TIO to T13. Next, complementary signal line D10, ? )10. Dll,
By inputting a digital signal to 1511, among the potential line group S,
One potential line 81 to S4 is sequentially selected and tested to see if the analog signal voltage-divided by the ladder resistance circuit 3 is normally output.

In other words, complementary signal lines DIO and Dll are at H level, Dlo
, When inputting an L level digital signal to Drll,
NMOS transistors Tl and T2 turn on and conduction line A1
becomes conductive, and potential line Sl is selected. Therefore, the potential of the node N1 in the ladder resistance circuit 3 is output to the output line 4 via the potential line S1 and the conduction line A1.

Here, after confirming that the potential of the node N1 is normally output from the output line 4, an H level digital signal is input to the complementary signal line 1510°Dll, and an L level digital signal is input to DIO, I511. T4 is turned on, conductive line A2 becomes conductive, and potential line S2 is selected. As a result, node N2 in ladder resistance circuit 3
The potential is output to the output line 4 via the potential line S2 and the conduction line A2. Then, it is confirmed that the potential of the node N2 is normally outputted from the output line 4.

Then, the complementary signal line DIO, T511 is set at H level.
When an L level digital signal is input to DiLO, Dll, NMO8I-transistor T5. T6 is turned on, conductive line A3 becomes conductive, and potential line S3 is selected. Therefore, the potential of node N3 in ladder resistance circuit 3 is output to output line 4 via potential line S3 and conduction line A3. Then, it is confirmed that the potential of the node N3 is normally outputted from the output line 4.

Furthermore, complementary signal lines Dto and I'll are set to H level, D
When inputting an L level digital signal to 10° Dll,
NMO8) transistor T7. T8 turns on and conduction line A4
becomes conductive, and potential line S4 is selected.

Therefore, the potential of node N4 in ladder resistance circuit 3 is output to output line 4 via potential line S4 and conduction line A4. Then, it is confirmed that the potential of the node N4 is normally outputted from the output line 4.

As a result, it can be confirmed by DC measurement that the decoder Dl is normal. After that, further decoder D2
When testing whether or not the NMOS transistors operate normally, the power supply voltage VDD supplied to the gate terminals of the NMOS transistors T10 to T14 is stopped. Then, ladder resistance circuit 3
The nodes N1 to N4 are separated from the potential lines 81 to S4, and the potentials of the nodes N1 to N4 in the ladder resistance circuit 3 are no longer supplied to the potential lines 81 to S4.

In this state, for example, complementary signal lines DIO and Dll.

D20. D2H;:HL/to/L/, complementary signal line r5
10. T511°I)20. An L level digital signal is input to r521 to select the common conduction line A1 in decoders D1 and D2, that is, to make it conductive.

When the test pattern signal X shown in FIG.
A test pattern signal X is outputted from the output line 4 of. Therefore, the test pattern signal X input from the output line 4 of the decoder D2 to the output line 4 of the decoder DI
Check that the is output correctly.

Similarly, complementary signal lines DIO and DIO of decoders D1 and D2,
U310. Dll, r511. D20. 'r5
20. D21. A digital signal is input to D21, a common conduction line A2 to A4 is selected, a test pattern signal X is input from the output line 4 of the decoder D1, and a test pattern signal Confirm that the test pattern signal X is output normally.

If it is confirmed through this test that the test pattern signal X is normally output from the output line 4 of the decoder D2, it can be confirmed that the decoder D2 operates normally.

As a result, after performing the DC measurement of decoder D1, the NMO
The operation test of the decoder D2, which is performed by turning off the S transistors TIO to T13, can be performed using the test turn signal X. Therefore, normally DC measurement requires several tens of milliseconds each time, but a test using test pattern signal X can be sufficiently measured in as little as 2 microseconds.

By the way, let's take a 10-bit, 10-channel D/A converter as an example. The time required for conventional DC measurement is 2" x 50 m5 x 10 = 512 seconds, assuming that one DC measurement time is 50 ms, for example.

The time required in the D/A converter of the present invention is (2”x50ms) + (210x9x2μ5) = 51.2 seconds.

As a result, it can be seen that time is involved only in the time required for DC measurement, and the measurement time using the test pattern signal X is on the micro order, and therefore hardly any time is involved.

Therefore, unlike the conventional method, the time can be significantly shortened. In particular, in the case of a multi-bit, multi-channel D/A converter, the number of tests is increased, so the effect becomes greater.

Furthermore, since this is the final test before shipping to determine whether or not the decoder group F operates normally, the NMOS transistors T10 to T1 are tested after confirming that the decoder group F operates normally.
The external power supply VDD is supplied to the gate terminal of No. 4, and the NMOS transistors T10 to T13 are kept turned on.

In this embodiment, a 2-bit, 2-channel D/A converter is used, but next, we will discuss a 2-bit, multi-channel D/A converter.
The side tilting embodied in the A converter will be explained. It should be noted that the configuration within the decoder group F is the same as in the previous embodiment, so
The explanation will be omitted.

As shown in FIG. 3, a plurality of decoders D1, D2, D3
......Dn-1, Dn constitute a decoder group F, and each decoder D1, D2, D3...Dn-
1 and Dn are connected in parallel to potential lines 81 to S4.

Next, when testing whether or not the decoder group F operates normally, the NMOS transistors TIO to T13 are turned on and the DC measurement of the decoder D1 is performed, as in the previous embodiment. After confirming that the decoder D1 operates normally, when the NMOS transistors TIO to T13 are turned off, each node Nl to N4 of the ladder resistance circuit 3 is disconnected from the potential line 5l-84. , the potential divided by the ladder resistance circuit 3 is no longer supplied to the decoder group F.

First, when testing whether the decoder D2 operates normally, the auxiliary signal lines DIO, r51
0. Dll, Dll, D20. D20
．． D21. A digital signal is input to 1521, and common conduction lines A1 to A4 are selected one by one.

Then, the test pattern signal X shown in FIG. 2 is input from the output line 4 of the decoder DI, and it is checked whether the test pattern signal X is output from the output line 4 of the decoder D2. After confirming that the test pattern signal X is normally output from the output line 4 of the decoder D2, the next decoder D3 is tested. Then, tests are performed up to the last decoder Dn to test whether the decoder group F operates normally,
When normal operation is confirmed, NMO8) supplies external voltage VDD to the gate terminals of transistors TIO to T13, turns on NMOS transistors TIO to T13, and enables shipping. As a result, measuring the test pattern signal X can take less time than conventional DC measurement.

Incidentally, the decoders D2, D3, . . . D3. A digital signal is input to select potential lines 81 to S4 common to all -Dn. From this state, the test pattern signal X is input to the output line 4 of the decoder D1, and the other decoders D2, D3...Dn
By confirming that the test pattern signal X is output from the output line 4 of the decoder group F, it is possible to test the decoder group F all at once.

In addition, the ladder resistance circuit 3 is connected from the output of the decoder D1.
NM without conducting a test in which the analog signal of
OS transistors Tl0-TI3 are turned off, and decoder group F is connected in series.

In this state, a set of decoders D1 and D2 is configured, and a digital signal for selecting the same potential lines 81 to s4 from the potential line group S is input to the decoders D1 and D2. Then, the test pattern signal X is output from the output line 4 of the decoder Dl.
By inputting , and confirming that the test pattern signal X is output from the output line 4 of the decoder D2, it is possible to confirm whether the decoder D2 is operating normally.

Similarly, one set of decoders D3. D4...1
A pair of decoders Dn-1 and Dn is configured and a test is performed between them. By this method, the test time can be further shortened compared to the above embodiment.

In the present invention, all the switching transistors are composed of NMOS transistors, but in addition to this, PMOS transistors are used.
It is also possible to configure the switching transistor with a MOS transistor, a CMOS transistor, and a bipolar transistor.

[Effects of the Invention] As detailed above, the present invention has the excellent effect of shortening the inspection time of the D/A converter and allowing efficient shipping.

[Brief explanation of the drawing]

Fig. 1 is an electrical circuit diagram of a D/A converter embodying the present invention, Fig. 2 is a waveform diagram of a test signal, Fig. 3 is a separate block configuration diagram of the present invention, and Fig. 4 is a conventional D/A converter. FIG. 2 is an electrical circuit diagram of a D/A converter. In the figure, 3 is a 2nR type ladder resistance circuit, 4 is an output line, D1 and D2 are decoders as selection circuits, S is a potential line group, 81 to S4 are potential lines, N1 to N4 are nodes, and T10 to T14 are opening/closing. NMO8) Transistor as a circuit, V ref+, V ref- are reference voltages as external voltages.

Claims (1)

[Claims] 1. Dividing external voltage (Vref+, Vref-) 2.
^nR type ladder resistance circuit (3) and each stage node of the 2^nR type ladder resistance circuit (3) (
A plurality of potential lines (S1 to N4) provided corresponding to
-S4) and the potential line group (S4).
) and each has one output line (4), and each selection circuit (D1, D2) receives an n-bit digital input signal. A multi-channel digital device which selects any one potential line (S1 to S4) from the potential line group (S) based on the selected potential line group (S) and connects it to the output line (4) of the selection circuit (D1, D2). In the analog converter, the potential line group (S) and the 2^nR type ladder resistance circuit (
3) A multi-channel digital-to-analog converter characterized in that a switching circuit (T10 to T14) is provided for connecting or disconnecting the nodes (N1 to N4) of each stage. 2. A 2^nR type ladder resistance circuit that divides the external voltage,
A potential line group consisting of a plurality of potential lines provided corresponding to nodes of each stage of the 2^nR type ladder resistance circuit, and connected in parallel to the potential line group, each having one output line. a plurality of selection circuits, the potential line group and the second selection circuit;
It consists of a switching circuit for connecting or disconnecting the nodes of each stage of the nR type ladder resistance circuit, and each selection circuit selects one of the potential lines from the potential line group based on an n-bit digital signal. In a multi-channel digital-to-analog converter that selects and connects to the output line of the selection circuit, the potential line group and each node of the 2^nR type ladder resistance circuit are connected in the switching circuit to select the selection circuit. One of the circuit groups that serves as a standard
One selection circuit is made to sequentially select each potential line connected to each node of the ladder resistance circuit based on a digital signal, and after inspecting the selection circuit and the ladder resistance circuit, the opening/closing circuit is inspected. The potential line group and each node of the ladder resistance circuit are separated in a circuit, and another selection circuit is connected in series with the reference selection circuit, and each selection circuit selects the same potential line based on a digital signal. 1. A method for testing a multi-channel digital-to-analog converter, the method comprising detecting whether or not the converter has been tested. 3. A 2^nR type ladder resistance circuit that divides the external voltage,
A potential line group consisting of a plurality of potential lines provided corresponding to nodes of each stage of the 2^nR type ladder resistance circuit, and connected in parallel to the potential line group, each having one output line. a plurality of selection circuits, the potential line group and the second selection circuit;
It consists of a switching circuit for connecting or disconnecting the nodes of each stage of the nR type ladder resistance circuit, and each selection circuit selects one of the potential lines from the potential line group based on an n-bit digital signal. In a multi-channel digital-to-analog converter that selects and connects to the output line of the selection circuit, a digital signal is input to the selection circuit to determine whether the same potential line is selected between each selection circuit. 1. A method for testing a multi-channel digital-to-analog converter, characterized in that the test method comprises: