JPH023182A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To improve operating speed by respectively providing a memory array part and a peripheral circuit part to control operation in separated semiconductor areas on the main surface of a semiconductor substrate and erasing memory information en bloc with an erasing signal. CONSTITUTION:A memory array MA is formed to include memory cells MS11-MS22, for which storing information can be electrically erased, to be provided on the semiconductor area of the main surface of the semiconductor substrate in a matrix shape. On the other separated semiconductor area of the semiconductor substrates, X decoders XD1 and XD2, Y decoders YD1 and YD2, writing circuits WA1 and WA2, an erasing circuit ERS and the peripheral circuit such as a control circuit CRL, etc., are formed. Then, the memory array MA is formed in a well area as a substrate gate and the cell information of the whole array MA are erased en bloc by the erasing signal to be based on a chip selecting signal and an operation control signal. The storing circuit device of the high operating speed can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit device, and more particularly to a semiconductor memory circuit device using a semiconductor nonvolatile memory element capable of storing and erasing stored information.

2. Description of the Related Art As a semiconductor nonvolatile memory element, an insulated gate electric field (hereinafter referred to as blank space) effect transistor is known, which utilizes a trap in a gate insulating film or a floating gate. In this type of insulated gate field effect transistor, due to the tunnel effect,
Alternatively, when charges are injected into the trap or floating gate in the gate insulating film by hot carriers generated by avalanche breakdown, the threshold voltage changes from one stable value to the other stable value. The state of one of the threshold voltages is made to correspond, for example, to a binary signal of 0, and the state of the other threshold voltage is made to correspond to a binary signal of 1.

The above charges can be removed by an appropriate method.

Therefore, the above type of insulated gate field effect transistor has the advantage of being usable as a nonvolatile memory element in which stored information can be written and erased.

A plurality of the semiconductor nonvolatile memory elements described above are arranged regularly on, for example, a semiconductor substrate, and are selected for reading or writing stored information.

The above-mentioned semiconductor nonvolatile memory element requires a high-voltage, high-level signal that reaches several times the signal level when writing, for example, compared to the signal level required for reading stored information.

However, since the signal level may be limited by the characteristics of the circuit elements, the semiconductor memory circuit device requires a circuit device specifically designed for the above-mentioned high level signals.

In addition, since the overall configuration of semiconductor memory circuit devices becomes complicated due to the use of circuit devices that process the above-mentioned high-level signals, it is necessary to prevent the semiconductor substrate used from increasing in size and to ensure that performance such as operating speed is not impaired. must be considered as such.

On the other hand, although such semiconductor circuit devices are required to be realized mainly using insulated gate field effect transistors, they are also required to partially use bipolar transistors to improve the circuit configuration and functionality. It is required to realize a circuit device as a so-called semiconductor integrated circuit device formed on a single semiconductor substrate. It is necessary to improve the efficiency of the manufacturing process for such a semiconductor integrated circuit device, and it is therefore required to realize the above-mentioned electronic circuit with a simple manufacturing process.

Therefore, one object of the present invention is to provide a semiconductor memory circuit device that uses a semiconductor nonvolatile memory element and has a high operating speed.

Another object of the present invention is to provide a semiconductor memory circuit device that uses semiconductor nonvolatile memory elements and can be miniaturized.

Another object of the present invention is to provide a semiconductor memory circuit device in which individual circuit devices are arranged at desired positions on a semiconductor substrate.

Another object of the present invention is to provide a novel semiconductor memory circuit device using a semiconductor nonvolatile memory element that can electrically write and erase stored information, such as an insulated gate field effect transistor that utilizes traps in a gate insulating film. It is about providing.

Another object of the present invention is to provide a semiconductor memory circuit device having a structure that achieves a semiconductor nonvolatile memory element in which stored information can be electrically written and erased.

Another object of the invention is to provide a circuit device suitable for processing high voltage signals.

Another object of the invention is to provide a circuit device that is less likely to be destroyed.

Another object of the invention is to provide a novel circuit device including a bipolar transistor and an insulated gate field effect transistor.

Still another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device for realizing the various electronic circuit devices described above.

The various objects and configurations of the present invention described above will become clear from the following detailed description and accompanying drawings.

Hereinafter, this invention will be explained in detail based on examples.

Although not particularly limited, in the following examples, an extremely thin silicon oxide film (
An insulated gate field effect transistor (hereinafter referred to as MNOS) having a two-layer structure of gate insulation formed on the oxide film Ω and the oxide film Ω is used. This MN
With respect to the OS, not only storage information can be written but also erased electrically.

FIG. 12 shows a cross-sectional view of the MNOS.

In the figure, an n-type source region 2 and a drain region 3 are formed on the surface of a p-type silicon region 10 to be separated from each other. A gate electrode made of n-type polycrystalline silicon is formed via a gate insulating film made of a silicon oxide film 4 and a silicon oxide film 5 having a thickness of 500 Å. The p-type silicon region 1 constitutes the basic gate region of the MNOS.

In the erased state or in the state where the memory information is not loaded, the MNOS game)? If pressure VG vs. drain current ID
The characteristics are, for example, as shown in curve A in Figure 13,
Its threshold voltage is a negative voltage of 4 volts (hereinafter referred to as -4v) K.

In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

In a write operation, the substrate gate 1 has e.g.
A ground potential OV of the circuit is applied, and a high voltage of +25V, for example, is applied to the gate 6.

A low voltage of yOv or a high voltage of +20V is applied to the source region 2 and drain region 3 depending on the information to be written.

Silicon region 1 between source region 2 and drain region 3
A channel 7' is induced on the surface in response to the high positive voltage of the gate 6. The potential of this channel 7 becomes equal to the potentials of the source region 2 and drain region 3.

When a voltage of Ov is applied to the source region 2 and drain region 3 as described above, a high electric field corresponding to the high voltage of the gate 6 acts on the gate insulating film.

As a result, electrons as carriers are injected into the gate insulating film through the channel 7 due to a tunneling phenomenon. MNO
The VG-ID characteristic of S changes from curve A to curve B in FIG. The threshold voltage may vary from the above-mentioned 14V to, for example, +1V.

+20 as above for source region 2 and drain region 3
When V is applied, the potential difference between gate 6 and channel 7 is reduced to a few volts. Such a low potential difference is insufficient to cause electron injection by tunneling. Therefore, the characteristics of MNOS do not change from curve A in FIG.

In a semiconductor memory circuit device, a plurality of MNOSs are coupled to one digit a. In the above write operation, the above voltage is applied to the selected MNOS. yOv for the gate of MNOS that is considered unselected.
A high voltage such as +20V is applied to the source region and drain region.

Erasing of stored information is performed by applying a high electric field to the gate insulating film in the opposite direction to the electric field for writing. A tunneling phenomenon occurs due to this high electric field in the opposite direction, and holes as carriers flow into the gate insulating film. The electrons injected during the writing are neutralized by the holes, and as a result, the characteristics of MNO5 return from curve B in FIG. 13 to curve MA again.

According to this embodiment, instead of applying a negative high voltage to the gate 6 while applying OV to the base gate 1 for the above-mentioned erasing, for example, the gate 6 is applied with 0V as will be clearer from the description below. The structure is such that a positive high voltage such as +25 V is applied to the base gate 1 while applying the voltage. By applying a positive high voltage to the base gate 1 as described above, the circuit configuration for applying a high voltage to the gate 6 can be simplified. In addition, high voltages of the same polarity can be used for writing and erasing.
As a result, the number of external terminals of the semiconductor memory circuit device and the number of power supplies for operating the semiconductor memory circuit device can be reduced.

Since the characteristics of the MNOS are either curve A or curve B in FIG.
This is done by detecting the conduction state between the drains. In order to be able to select one of the plurality of MNOS coupled to one digit H by a single polarity signal, unit storage elements (hereinafter referred to as memory cells) are divided into two types as shown in FIG. As shown in the circuit, the circuit is composed of an MNO8QI and a switch insulated gate field effect transistor (hereinafter referred to as a switch MISFET) Q2 connected in series with the MNO8QI. During readout, the gate voltage of MNO5QI is maintained at OV, and the gate voltage of ~ll5FET for switch is maintained at OV.
The tC pressure is set to a positive voltage such as OV or +5V depending on the selection signal.

FIG. 1 shows a circuit of a semiconductor memory circuit device according to an embodiment.

The memory circuit of this embodiment includes circuits that form relatively low-voltage signals such as an X decoder, Contains.

Although not particularly limited, a low power supply voltage of +5V is supplied to the power supply terminal VCC for the circuit that forms the above-mentioned low voltage signal. Depending on the power supply voltage, the high level of the low voltage signal is set to r+sv, and the low level is set to OV of the ground potential of the y circuit.

A high voltage terminal vPP is provided in the circuit device for circuits such as the write circuit and the erase circuit.This high voltage terminal vPP is connected to the high voltage terminal vPP when the circuit device performs a write operation and an erase operation. A high voltage such as y+25V is supplied. Depending on the above-mentioned high voltage, the high level of the high voltage signal is set to y+25V or +20V, and the low level is set to yOV.

In FIG. 1, Δ(A is a memory array, which includes memory cells MSII to MS22 arranged in a matrix.

The gates of the switch MISI'ETQ2 of the memory cells MSII and MS12 arranged in the same row are as follows.
Commonly connected to the second ward Mori W11, each MNO
The gates of 3QIs are commonly connected to the second word 1-. Similarly K, placed T on the other same line? t memory cell MS21. MS22 switch MISFET and MN
The gates of the OS are respectively connected to the first word side W21. Commonly connected to the second word -W22.

The drains of switch MISFET Q2 of memory cells MSII and MS21 arranged in the same column are connected to disk HB.
tDx, and the source of MNOS is connected to reference potential i
Commonly connected to fl ED 1.

Memory cells MS12 similarly arranged in another same column,
MS22 switch MISFET drain and MN
The OS sources are Digit-D2. They are commonly connected to the reference potential line El)2.

According to this embodiment, since the memory information of the MNOS is erased by applying a positive high voltage to the base gate, the semiconductor region forming the memory cell is It is electrically separated from the semiconductor region forming the peripheral circuit. As will be explained later, the above semiconductor region is composed of, for example, a p-type well region formed on the surface of an n-type semiconductor substrate.

For the above-mentioned erasure, individual memory cells can be formed in independent well regions, or memory cells arranged in the same row or column can be formed in a common well region. Now, the entire memory cells, ie, the memory array MA, are formed in one common well region.

In FIG. 1, the rock WELL is connected to the well region as a common base gate of the memory array MA.

The first words iWW 11 and W 21 are connected to the output terminals of the X decoders XDI and XI)2, respectively,
Second word 1! W12. W22 is a write circuit WAl
, and are connected to the output terminals of WA2.

As shown in the figure, the X decoder ; It consists of enhancement type MISFETs Q4 to Q6 which are connected between two terminals and receive non-inverted outputs or inverted outputs from address buffers BO to 36 at their respective gates, forming a 1N NOR path. , X decoder X1)1
is selected (・When not, outputs a low level signal of approximately Ov to the word neWll by the high level of 100 on at least one of the address input lines aO to a6, and when selected, the address input line i1j All signals at a O to a6 become low level, and M
Outputs a 5V high level signal.

The X decoder XD2 has the same 1111 configuration as the X decoder XDI described above except that the connected address input lines are different.

In FIG. 1, depletion type MISI" and ET such as MISFETQ3 are marked with different symbols from enhancement type MISFETs as shown.

The sweetening circuit WAI is an MI connected directly between the first word line Wll and the output terminal (second word line W12).
SI'ETQ15. MI 5FET connected to Ql6 and +ljJ between the output terminal and the power supply terminal VI'I' to which the voltage of +25V is applied during writing and erasing.
QI9, and MISFETQ17°Ql8 connected in series between the output terminal and the ground terminal. Above M
Is the gate of I5FETQI5 omitted control? nWl
The gate of MISFETQ18 is connected to the read and erase control line vp, and the gate of MISFETQ18 is connected to
And what about the gate of Ql8? It is connected to the If source terminal VCC.

With the control circuit CI'LL having a configuration to be described later, the signal on the write control line Wl is controlled to be ! except for the sweetening operation. 1"OvO low level, and the signal below the control line 7 is set to +5V high level. Therefore, the MIS
FETQ15 is in the off state, whereas MISFE
TQ18 is in the on state. Output terminal (second word 47
W12) is connected to the ground terminal of the circuit via series-connected MISFETs Q17 and Ql8, so that KOV
be made into

In the write operation, a high voltage of +25■ is applied to the power supply terminal VPI', and the MI 5F is applied to the write control side Wl.
To turn on ETQI 5, a high level of y+5V (i is added, and MISFE is applied to control &+vp.
A signal of yOV is applied to turn 'T'Q18 off.

On state of MISFETQ15 above and MISFEi'
Due to the off state of Q18, the signal level of the second word line W12 can be determined according to the signal level of the first word line Wll.

That is, if all of the drive MISFETs Q4 to Q6 of the X decoder XDI are turned off so as to select the first word 1W11, then the
．． Ql 5 and the above driving MIsFETs Q4 to Q6
The current path is not configured.

Therefore, MI 5FETQ19 is connected to the second word line W12.
+25V of the g power supply terminal VPP appears through. That is, in response to x+5V being applied to the selected first word forest, a Jtri pressure of M+25V is applied to the selected word a.

If the first word line Wll is not selected, that is, if at least one of the driving MISFETs Q4 to Q6 of the X decoder XD1 is turned on, MI SI'E'
l'Q1 G, Ql 5 and the above driving MISFET
The output terminal (second word line W12
) is formed to ground the vL current path. As a result, the output terminal is set to yOv.

In the write circuit WAI, the MISFETs Q16 and Ql7, which constantly receive the power supply voltage vCC at their gates, are as follows:
The high voltage signal applied to the second word line W12 is applied to the MISFET.
It is used to prevent being limited by the breakdown of Q15 or Ql8.

That is, for example, if MI 5FETQI 7 is omitted, the second word 1 is connected to the drain D of MTSFETQI 8.
A high voltage (+25V) of W12 will be applied.

Since a low voltage of 3-O■ is applied to the gate of MISFET'Q18 from the control line vp as described above, the depletion layer that should spread to all four sides of the drain junction of MISFET'Q18 is in the vicinity of the gate. will be limited by the low voltage on this gate. As a result, M.I.
The drain junction of SFET Q18 will break down at relatively low voltages.

If MI 5FETQI 7 is provided as shown, MI
The voltage applied to the drain of SFETQ18 is the electric g voltage V
It is clamped to a voltage increased by the threshold 1 direct voltage of MISFE'rQ17 from the CC voltage.

As a result, breakdown of MISFETQ18 is prevented. MISFETQ17 has a relatively high drain breakdown voltage because its gate is connected to the 1((source) vCC.

MI 5FET QI 6 may also be used for the same reason as MISFET Q17 above.

According to this embodiment, well regions as described above are used (14 formations are effectively utilized).

The load MISFET Q19 in the write circuit WAI is a MISFET such as other MISFETs Q15 to Q18.
It is formed in a well region independent from the well region forming the ET. That is, the basic gate of MI 5FET QI 9 is electrically separated from the base gates of other MISFETs by pin! be done.

As shown in the figure, the load MISI'ETQ19 has its base gate and source short-circuited to prevent high voltage from acting on the channel between the base gate and the source and drain.

Regarding the connection shown in the figure, if the body gate is connected to the ground terminal like other MISFETs, the voltage required at the output terminal (second word atwt2) is large, so the voltage of MISFET Q19 due to the body bias effect is ~fIs for threshold 11 voltage increase to handle other low voltages
It becomes significantly larger than an FET. As a result, the voltage supplied to the high voltage terminal VI'P must be significantly larger than the voltage required at the output terminal (second word 1lW12).

On the other hand, in the case of the connection shown in the figure, the voltage of the body gate is equal to the 'tE voltage of the source, so that the increase in the threshold (direct voltage) of MISFET Q19 due to the body bias effect can be virtually ignored. , high voltage terminal ■P
The high voltage supplied to P can be made comparatively smaller.

As described above, by adopting a configuration in which the voltage supplied to the high voltage terminal VPP can be reduced, this high voltage terminal V
It is no longer necessary to make the breakdown voltages of various pn junctions to which PP is connected abnormally high, or various undesirable leakage currents in pn junctions can be reduced. Furthermore, it is possible to prevent undesirable parasitic channels from being induced on the surface of the ghost body due to the electric field from the wiring connected to the high voltage terminal VPP.

The position lines zDx and ED2 for each reference 1 of the memory array MA are as follows.
It is connected to the soiling inhibition circuit IHAI.

In the write inhibit circuit III-IAI, MISFETQ20 and Q21 connected in series between the reference potential 4tjlED1 and the ground terminal constitute a unit switch circuit. MI in this unit switch circuit
5FETQ21 receives a control signal from control circuit CRL via control +lIr. The control signal No. 1g is set to a level of +5 V to turn on the MISFET Q21 during a read operation of stored information, and set to a level of O■ to turn it off during a write operation and an erase operation.

Therefore, the unit switch circuit sets the reference potential line EDI to yOV during the read operation.

KM between the reference potential line EDI and the high voltage signal mIHv
ISFETQ22 is connected. The above-mentioned high voltage signal line I
From lA2, +20 during sweetening operation and erasing operation.
V, and yOV during read operation.
A signal is applied.

Therefore, in the programming operation and erasing operation, when the MISI"ETQ21 of the unit switch circuit is turned off, a high voltage is applied to the base potential line EDI from the high voltage level IHV via the M15FETQ22. applied.

MIS1'ET is connected between the reference potential line FD2 and the ground terminal.
A unit switch circuit similar to the above made up of Q23 and Q24 is connected, and a MISFET Q25 is connected to one line between the reference potential Jj E D 2 and the high voltage signal line I I-TV.

In the above-mentioned write inhibit circuit I HA 1, MISFET Q20.
Since a high voltage as described above is applied to the base fiA potential lines EDI and ED2, Q23 is connected to the above-mentioned input circuit WAI.
MISFETQ16. It is used for the same reason as Q17.

MT5FETQ22. Q25 is the MISFETQ1
9, in order to prevent an increase in the threshold voltage due to the substrate bias effect and to prevent the voltages of the reference potential lines EDI and ED2 from decreasing with respect to the high voltage of the high voltage signal 1IHV, an independent well region is provided. It is formed.

Each digit line D1. of memory array MA. A 1i411c Y gate circuit YGo is connected to D2 and the common disk) KatsucD.

In the Y gate circuit YGO, a MISFET is connected in series between the digit line D1 and the common digit line CD.
QII and Q12 form a unit gate circuit to +1゛, and Y
The digit line D1 and the common disk line Cl) are coupled in accordance with the output of the decoder MDI. Similarly, MT
SI'ETQ13 and Q14 form a unit gate circuit, and this unit gate circuit couples the digit line D2 and the common digit line in response to the output of the Y decoder YD2.

Each digit aD 1 during filling operation and erasing operation
, D2 appears, so the unit switch circuit in the Y gate circuit YGO is a MISFETQ whose gate receives a +5V power supply voltage as shown in the figure.
12. Use Q14.

The Y decoders MDI, YD2 are the X decoders XDI,
Non-inverted signals a7 to al of address signals A7 to AIO, which have a similar configuration to XD2 and are output from address buffers B7 to BIO.

and inverted signals a7 to alo, the respective outputs iY1 . +5V to Y2 when selected
Decode 1 becomes high level and becomes KOV when not selected.
Output a word.

Common digit Fuji CDK connected to Y gate circuit YGO
is connected to the sense circuit IO8 and the data input circuit IOW.

Sense circuit 1. The OS includes a load MISFET Q47 whose gate and source are connected as shown in the figure, and a switch MISFET Q48 whose gate receives a signal from the controlling country t°.
It consists of In the output operation, the signal at the output terminal t is set to a high level of +5V, thereby turning on the switch MISFET Q48.

The output of the sense circuit 10S is connected to the inverter ■14.1
15. NOR circuit NrL3. Nl14 and MISFET
Q/+9. An output buffer circuit 10nK consisting of Q50 is supplied.

In the output buffer circuit IOR, the NOR circuit N113,
One input terminal of each of N114 is the control line C3IK
It is connected. The signal on the control line C31 is set to a low level of OV during a read operation, and set to a high level of +5V during a write and erase operation. The above NOR circuit N1
The other input terminal of NIt4 is connected to the output terminal of inverter IN14, and the other input terminal of NIt4 is connected to the output terminal of inverter INI5 which receives the output of inverter IN14.

Therefore, the NOR circuits Nrt3 and NR4 output signals having opposite phases to each other during the read operation. MISFET Q49 and Q50 connected in series are connected to the above NOR circuit Nl1.
3 and N 114 in a push-pull manner.

If the signal on the control line C31 is at a high level, the NOR circuit N
Both R3 and NR4 output low level signals of OV, and both MISFETs Q49 and Q50 are turned off. The output terminal of the above output cover sofa circuit l0rL is
Connected to input/output terminal PO. MISFET above
In the simultaneous off-state of Q49 and Q50, the output buffer circuit has a significantly higher output impedance and therefore does not limit the input signal applied to the input/output terminal PO.

In the above output buffer circuit I Ort, the power supply terminal ■
The above MISFETQ connected between CC and the output terminal
49 is formed in a well region independent from the well regions of other MISFETs. The well region as a substrate gate is connected to its source. As a result, the increase in threshold voltage due to the substrate bias effect is virtually eliminated, so
The output buffer circuit IOIt is now able to output the high level 1g of the y power supply voltage VCC.

The data input circuit IOW is connected to the input buffer circuit IN16 and the output of the input buffer circuit IN16 as shown in the figure.
MI 5FETQ51 which is controlled and this MISFET
The MI 5FET Q52 is connected between the drain of Q51 and the common digit +1!1lCD, and receives a signal from the control line Wl at its gate.

The anti-soaking voltage generation circuit 111A2 is 5K as shown in the figure.
It is composed of MISFETs Q26 to Q36. The MISFETs Q26 to Q28 constitute a first high-voltage inverter, and upon receiving a low-voltage control signal from the control iJJ W l, output a high-voltage signal to the output terminal, that is, the drain of the MISFET Q27. With the connections shown, the output signal level is yO
It varies from v to vPP. MISFETQ29 to Q31 constitute a second high voltage inverter, and receive the same signal as the first high voltage inverter to
A high voltage signal is output to the drain of SFETQ30. Its output 1 word level is from W+5V (vCC) to v
Changes up to PP. MI SI'ETQ32 or Q3
6 constitutes a high voltage push-pull circuit. Above 1. A second high voltage inverter and a push-pull output circuit receive a control signal.
MISFETQ27°Q30. which is connected between Q28, Q31, Q36 and their respective output terminals and whose gate receives a power supply voltage of +5■. Q35 is
Previous R's MISFET QlG.

Like Q17 etc., it is used to ensure high output voltage of the circuit. Load MISFETQ26 in the first and second high voltage inverters. Q29 has its body gate connected to its respective source to eliminate the drop in output voltage due to the body bias effect, as shown in the figure, and is connected to MISFETs Q33 and Q32 .Q32 of the push-pull output circuit. 41/f is configured to sufficiently drive Q3.

In the above push-pull output circuit, MISF'ETQ
32 is used to limit the voltage applied to the drain of MISFET Q33 when the output of the first high 1B voltage inverter is yov.

That is, when the output of the first high voltage inverter is yOV, the reference potential of the second high voltage inverter is +
Since it is considered to be a low voltage of 5V, it outputs +5■. As a result, +5■ is applied to the gate of MI 5FETQ32, and the drain voltage of MISFET Q33 is limited.
1st. As the output of the second high voltage inverter becomes a high voltage, the output line 1 (V) is brought to a high voltage of +20V, and then the output of the 1st and 2nd high voltage inverters becomes When OvO becomes low level, the output line I II
V is additionally used to control the high heart pressure applied to the source of MISFET Q33. As a result, undesired breakdown of the switched MI 5FET Q330 source and drain junctions is prevented.

The erasing circuit EItS includes MISFETQ40 to Q42.
A push-pull circuit includes MISFETs Q43 to Q46 and a bipolar transistor Q44. The high voltage inverter includes the write inhibit voltage generation circuit I
-It has the same configuration as IA2.

In the above push-pull output circuit, bipolar transistor Q44 and MI 5FET Q43 are connected in parallel,
It is driven by the output of the high voltage inverter. The well region forming the memory array constitutes a heavy capacitive load for the erase circuit, as will be apparent from the structure of the circuit arrangement f/ffi to be explained later. Therefore, the erase circuit E R
S is required to have sufficiently low output impedance characteristics in order to perform a high-speed erase operation. Bipolar transistors can be used in MISF even if they are formed with relatively small dimensions (areas) in semi-solid integrated circuit devices fii'.
Shows sufficiently low operating resistance characteristics compared to ET. Therefore, as shown in the figure, the erase circuit ER8 having the bipolar transistor Q44 as an output transistor drives the well region of the memory array MA at an optically high speed even if it is formed in a small area in a semiconductor integrated circuit device. A structure of a bipolar transistor formed on the same semiconductor substrate as the MISFET,
The manufacturing method will be explained later.

In the erase circuit ErtS, when only the bipolar transistor Q44 is used, the threshold 1 direct voltage (base-emitter voltage) of this bipolar transistor is
For example, since there is 0.6V, MISFETQ40 or Q
The high voltage inverter consisting of 42 V power supply voltage VP
Even if the signal I' is output, the voltage signal output to the output kl is lowered by the threshold of the transistor Q44 +K''4 voltage.

In the illustrated erase circuit ER3, the body gate is integrated with the body gate of the load MISFET Q40 of the high voltage inverter, and the gate is integrated with the body gate of the load MISFET Q40 of the high voltage inverter.
Depletion type MI 5FE connected to the source of 5FETQ40, that is, the output terminal of the high voltage inverter
TQ43 is connected in parallel with the bipolar transistor Q4/l. In the MISFET Q43, the high potential of the substrate gate rises to the S:'TJi source voltage vPP, so there is virtually no increase in the threshold voltage due to the substrate bias effect. Therefore, the high voltage at output #l is rA depending on the MISFET Q43, and the source voltage VI'P
It will be possible to raise it to

The MI 5FET Q430 body gate may be connected to its source, ie the output Ju l, from the connections shown. Even in this case, is the output due to the substrate bias effect? It is possible to prevent the output level of 1 fill from decreasing. However, in this case, due to the structure of the circuit device J, the well region serving as the base gate of MI 5FET Q400 and the well region serving as the base gate of Q43 cannot be shared, and must be separated from each other.

Since the well regions must have a predetermined distance of +o1's5≦, there is a disadvantage that the required area of the semiconductor substrate must be increased.

The control circuit CILL is connected to the inverter INI or ■N12.
, NAND circuit NAI to NA4, NAND circuit NR1,N
112 and serially connected (7) MISFETs Q37 to Q39. This control circuit CRL has an external terminal PG
4'f writing control signal to M, C3 and vpp, respectively;
It receives a chip selection signal, a moss fill-in signal, and an erase signal, and receives an output signal from the write inhibit voltage generation port 'NIIJA2, thereby outputting control signals to acsl, f, wl, wl, and vp.

The signal supplied to the terminal VPP is the write circuit W.
A1. WA2, oath prohibition voltage generation circuit I HA 2
This is a high voltage signal of +25V which is shared as the power supply voltage for the erase circuit ErtS.

The control circuit CRL includes MISFETs Q37 to Q3 as described above so as to control the filling or erasing operation only when the signal at the terminal VPP reaches a predetermined level or higher.
It includes a level shift circuit consisting of 9.

The operation of the semiconductor memory circuit shown in FIG. 1 is shown in FIGS. 2 to 4.
This will be explained as follows using the timing chart shown in the figure. Note that FIG. 2 shows a timing chart of a read operation, and FIG. 3 shows a timing chart of an erase operation. Further, FIG. 4 shows a timing chart of a write operation.

In the read operation, the write control n signal applied to the terminal PGM is set at a low level of yov. Also, the terminal vPP is set to yOVK or left floating, and is almost connected to the drain of MISFET Q39, which receives +5V voltage VCC at the gate. 1′
The OV write and erase control φ1j signal appears.

Due to the low level write control signal at the terminal VPP and the low level pledge and erase signal at the drain of MI 5FETQ39, the signals on the control lines f, Wl and vpK are at high level, and the signal at Wl is at low level. ing.

Therefore, each reference potential line ED1 . ED
2 is a write-inhibited circuit depending on I I-I A I!
1″OVK, each second word 1W12°W22
Similarly, depending on the write circuits WAI and WA2, yov
It is being done.

Although the timing is not particularly limited, for example, at time 10, signals at the address input terminals AO to AIO are set corresponding to the selected memory cell. For example, if the memory cell to be selected is MSll, the output of the X decoder
output becomes high level.

As a result, a MISFET Q is connected between the drain of MNO3QI of memory cell MSII and the common dector) fMcD.
l, QIO, Digit Katsu DI and MIS for switch
A current path is formed through FETQ2. In addition, due to the high level of the signal at the control terminal rK, the common digit line CD and the sense circuit % I OSf) negative MM I S
FET Q47 17) ifqlK current path is formed.

If MNO3QI of memory cell MSII is in the on state as shown in FIG. 13A, then sense circuit IO
The output line of No. 3 is grounded via the current path and MNO3QI. As a result, the output i of the sense circuit IO3 becomes low level.

The MNO3QI of the memory cell his11 is shown in FIG. 13B.
If it is in the off state as shown in the characteristics of the load MI
A current path for the 5FET Q47 is not formed, and as a result, the output 1 of the sense circuit IO3 becomes high level.

At time tl, the chip selection signal at terminal C8 is changed from high level to low level, so that y
At the same time t2, the signal in the control 1cs1 becomes low level. As a result, the output sofa circuit IOR comes to output a signal corresponding to the output level of the sense circuit IO3 from the high output impedance state. For example, if the sense circuit IO3 is outputting a high level signal, the output buffer circuit IOR outputs a high level signal to the output terminal.

When the chip selection signal returns from low level to high level at time t3, the control line C3 changes at the same time t4.
The signal I changes from a low level to a high level, and in response, the output buffer circuit (2) OR returns to a high output impedance state.

For the erase operation, a +25V write and erase signal is applied to the terminal vPP in advance, and a low-level chip selection signal Ov is applied to the terminal C8.

The signal on the control line vpVc is at a high level due to the chip selection signal at the above level, so that the signal on the second word line W12. W22 is set to yov.

As shown in FIG. 3, when the write control signal is set to high level at time tlo, the number and circuit NA correspond to this.
The output of 4 becomes low level. The erase circuit ERS is activated by the low level signal of the NAND circuit NA4.
Since FETQ42 and Q6 are in the off state, the output line l
Outputs +250 high voltage.

As mentioned above, the second word #W12. 1 in W22
Since the voltage g is set to OV, when the well region WELL is brought to a high voltage of +25V by the output of the erase circuit ER8, a high voltage for erasing is applied to the gate insulating film of the MNOS of the memory array.

The positive voltage in the well region is the MNO3QI of the memory cell.
And the source junction and drain junction of the switch MISFET Q2 are biased in the forward direction. Therefore,
Reference potential 11ED1. ED2, Digit I! jlDI
, D2 and the ground terminal of the circuit, the voltage to be applied to the well region will be reduced.

The illustrated circuit operates as follows to prevent the voltage drop in the well region described above.

The signal on the control at+line t' is y at the time tlo above.
At the same time tll, the write control signal becomes low level in response to the write control signal becoming high level.

Write inhibit circuit I by the signal on the control line r
HAI's MISFETQ:'1. Q24 and MISFET Q36 of the write inhibit voltage generation circuit IHA2 are turned off. As a result, each reference potential line E of the memory array
DI and ED2 are substantially floated.

Control mW I! The signal at is at low level in accordance with the low level of the chip selection signal. Therefore, the MISFET Q52 in the data input circuit IOW connected to the common data input circuit (ICD) and iCD is in an off state. On the other hand, MISFETQ48 in the sense circuit IO8 connected to the common digit line CD is turned off by the signal in the control mr.

Due to the floating of the common digit signal CD, each digit line Dt, Dz of the memory array MA becomes floating regardless of the operation of the Y gate YGO.

At time tll, when the signal at the terminal PGM returns to the low level, the output of the erase circuit ER3 also returns to the low level accordingly.

As described above, the erase operation is performed in the chip selected state, whereas the write operation is performed in the chip non-selected state, that is, when the signal at terminal C8 is at a low level. For a write operation, a +25V write and erase signal is applied to the terminal vPP in advance.

At time t20, address signal a is set to select, for example, memory cell MS11.

That is, the first word line W1 is
1 is set to high level, and the line Y is set to high level by the Y decoder MDI.
1 is considered a high level.

At time t21, information to be written is added to terminal PO. If the information to be written is O, the terminal PO is 0■
MI5 of the data input circuit IOW is set accordingly.
FETQ51 is +5V from the input cover sofa circuit lN16.
It receives a high level signal and turns on. If the information to be written is 1, for example +5■, the above MISFET
Q51 is the Ov output from the input cover sofa circuit INI 6.
turns off.

When the write control signal on the terminal PGM becomes high level at time t22, the signal on the control line Y becomes low level at time t23 after a slight delay time caused by inverters INI, IN2 and NOR circuit NR2 in control circuit CRL. As a result, the write inhibit circuit IHA
MISFETQ21. Q24, MISFET Q36 of the write inhibit voltage generation circuit HA2 and MISFET Q48 of the -t=once circuit IO8 are turned off.

At time t24 after a slight delay from time t23, the signal on the control line We becomes low level. In response to the signal from the control 174 W e, the write inhibit voltage generation circuit IHA2 outputs a high voltage of y+20V to the line IHV, and in response, each reference potential line EDI, ED2 of the memory array outputs the above +20V. become.

At the same time as the time t24, the signal on the control line We becomes high level. Accordingly, MI 5FETQ52 of the data input circuit 20W is turned on. At the same time, MIS of write circuits WAI and WA2
FETQ15 is turned on.

Output line IHV of the write inhibit voltage generation circuit IHA2
When the signal on the line IHV becomes a sufficiently high voltage, the control circuit CRL receiving the signal on the line IHV outputs a low level signal on the control line vP at time t25. The above control line vP
The signal at is used as a write start signal, as will be explained next. As described above, by configuring the write start signal to be output after the signal on the line IHV reaches a sufficient write inhibit level, it is possible to prevent information from being accidentally written to unselected memory cells. can.

As mentioned above, since the signal on the control line vP becomes low level, the inset circuit WAI.

MISFET Q18 of WA2 is turned off.

Input circuit WAI selects the first word line Wll! Since the voltage is +5V, a high voltage of r+25V is output to the second word 1W12.

Since the first word line W21 is not selected and is set to approximately Ov, the write circuit WA2 outputs approximately Ov to the second word line W22 accordingly.

MNO3QI in memory cell MSII to be selected is connected to switch MISFET Q2, digit line D1, Y
MISFETQ51 receives the output of input buffer circuit IN16 via MISFETQI2, Qll of gate YGO, common digit 'aCD, and MISFETQ52.
is combined with If the information to be pledged is 1, the ON state of the MISFET Q51 causes the memory cell M to
MNO8QI in SII has its drain and source almost Ov, and its gate (second word reduced W22
) electrons are injected into the gate insulating film. If the information to be imported is O, the above MISFET
Due to the OFF state of Q51, the source and drain of MNO8QI in the memory cell MSII are set to +20V of the write inhibit voltage generation circuit IHA2. Therefore, the electrons mentioned above are not injected. same day)
Since the signal on the second word line W22 is set to approximately Ov as described above, no information is written into the memory cells MS21 in the other row coupled to the line D1.

Since the MISFET QI 3 in the corresponding Y gate YGo is in the OFF state, the other DIGINO) line D2 is increased by +20 by the output of the write inhibit voltage generation circuit IHA2.
maintained at V.

When the survival control signal at terminal PGM becomes low level at time t26, as shown in FIG. 3, the signal at time t27. t28. At t29, the control lines vP, w
The signals at e and r become high level. Correspondingly, the signal on the second word line w12 and the reference potential ff1ED1 also becomes approximately 0.

The semiconductor memory circuit of the present invention can be made relatively large, such as 16 Kbits.

FIG. 5 shows a block diagram of a semiconductor memory circuit using the circuit of FIG. 1.

In FIG. 5, memory array MA includes, for example, 16,384 memory cells arranged in 128 rows by 128 columns. For the memory array MA, 128 memory cell rows are selected by receiving a 7-bit address input signal from address buffers BO to B6.
A decoder XD is provided. In addition, 16 of the memory cell column
Eight Y gates (YGO to YO2) are provided, and these Y gates are connected to the address buffer B7.
It is controlled by a Y decoder YD which receives a 4-bit address input signal from the BIO. Above Y gate Y
Input/output circuits IO to I7 including a sense circuit, an output buffer circuit, and a data input circuit as shown in FIG. 1 are provided corresponding to GO to YO2, respectively. MI5 as shown in FIG. 1 corresponds to each memory cell column.
A write inhibit circuit IHA including FETs Q20 to Q22 and one write inhibit voltage generating circuit is provided, and a write circuit WA is provided corresponding to the memory cell row. Furthermore, a control circuit CRL and an erase circuit ER8 are provided.

Therefore, the semiconductor memory circuit shown in FIG. 5 stores 8 bits of information in 11 bits, that is, 2048 addresses.

As mentioned above, the memory cells are connected to MNOS and switch MI.
The configuration of the X decoder can be simplified by constructing the X decoder with SFET and making the X decoder and the inset circuit independent circuits. Therefore, X
It becomes easy to speed up the selection of word wins by the decoder, and it becomes possible to provide a memory circuit that operates at high speed.

MI 5FETQ22゜Q2 in the tampering prevention circuit
The sources of 5 are connected to the reference potential lines EDI and ED as shown in FIG.
For example, the digit lines D1 and D2 may be connected instead of being connected to the digit lines D1 and D2. Even in the above case, it is possible to supply the write inhibit voltage to the memory array.

However, if we do the above, each digit line D
i, the above MISFETQ22. Floating noises from the junction capacitance of Q25, wiring numbers, etc. are combined, and as a result, when reading and writing stored information, the speed of signal change for each digit is limited, so care must be taken. As shown in Figure 1, MISFETQ22. When Q25 is connected to the reference potential lines EDI and ED2, the signal change speed of digit a can be increased.

Each of the above circuits is created using semiconductor integrated circuit technology.
Formed on one semiconductor substrate.

According to the present invention, each of the circuits described above is formed on a semiconductor substrate in an arrangement that does not limit the circuit characteristics and does not increase the size of the semiconductor substrate used.

FIG. 61 shows a pattern of regions for each circuit and wiring formed on the silicon substrate 1. In FIG. 61, the X decoder XDIJ' is placed at the center of the surface of the substrate 10. The memory array is divided into two, MAL and HA2, one of which MAL is placed on the left side of the X-decoder XD, and the other MA2 is placed on the right side.

A write circuit WAa is arranged on the left side of the memory array MAL, and a slotting circuit WA6 is similarly arranged on the right side of the memory array MA2.

Above the memory array MAL, a Y game) YGa is arranged, and similarly above the memory array MA2, a Y game) YG is arranged.
b is placed. A Y decoder YD is arranged between YGa and YGb, that is, above the X decoder XD.

The above memory array, X decoder, and write circuit.

The area around the Y gate and the X decoder is a wiring region WIR as indicated by dots.

The above memory arrays MAl, M are located across the wiring area WIR.
A write inhibit circuit IHA is provided below each of A2.
a, IHA b are placed.

The input/output circuit IO and the control circuit C are provided on the chest circumference of the surface of the board 10.
RLI and CrtL2. Input buffer circuit AI or A
12 are arranged. Further, bonding terminals P1 to P26 for connecting various input terminals and output terminals to terminals outside the circuit device are arranged around the circuit device.

In order to configure the circuit shown in FIG.
I and HA2 each have a size of 128 rows by 64 rows. Corresponding 17th memory arrays MAI and HA2
- and are simultaneously selected by the X decoder XD. The input line of the X-decoder XD is connected to an input buffer circuit arranged around the substrate 1 via wiring in the wiring area WIH.

Y gates YGa and YGb are simultaneously connected to corresponding memory arrays MAI and M by the output of Y decoder YD.
The A2 digit line is selected. The above YGa, YGb are connected to the input/output circuit 10 via wiring in the wiring region WIR.

The write inhibit circuits IHAa and IHAb are connected to the corresponding memory array MA via wiring in the wiring area WIR.
It is connected to the reference potential line of I and MA2.

As mentioned above, embodiments of the invention use well regions for the memory array and its peripheral circuitry.

FIG. 7 shows a pattern of well regions formed on the surface of the silicon substrate 10, corresponding to the circuit arrangement shown in FIG. FIG. 8 shows a sectional view taken along the line AA in FIG. 7.

In FIGS. 7 and 8, independent P-type well regions 10a and 10b are formed on the surface of an n-type silicon substrate 10 to form a memory array.

Around the well regions 10a and 10b, separated from them, there are an X decoder, a Y decoder, and a Y gate.

Write circuit, write protect circuit, input/output circuit.

A P-type well region 11 is formed for forming peripheral circuits such as an input buffer circuit and a control circuit.

In the upper part of FIG. 7, it is shown in a large size due to space limitations, but the output buffer circuit ■OH in FIG.
In order to form a MISFET that connects the source and the base gate like I5FETQ49, a P-type well region 11a that is separated from the above-mentioned P-type well region 11 and is independent is provided.
to llb are formed.

Similarly, on the left side of the P-type well region 10a and on the right side of the P-type well region 10b, independent P-type well regions 11c or lid and lie or llf is formed. Further, below the page of FIG. 7, in order to form an M[5FET that requires an independent base gate similar to the write inhibit circuit IHAI, write inhibit voltage generation circuit IHA 2, etc. of FIG. 1, P-type well regions 11 each independent from other P-type well regions
g to lih and lli to 11j are formed.

Although not shown in FIGS. 7 and 8, the n-type silicon substrate 1 is exposed at a predetermined portion within the P-type well region 11 in order to form a MISFET to be described later. be done.

According to this embodiment, as described above, the n-type silicon substrate 1
Since the configuration is such that various P-type well regions are formed on the top,
Various effective transistors and other elements for semiconductor memory circuit devices can be formed.

For example, a channel stopper is formed on the surface of the n-type silicon substrate 10 between the plurality of P-type well regions by an impurity ion implantation method or the like, as will be described later. will be used effectively.

That is, for example, FIG. 9 shows the M
1 shows a cross-sectional view of ISFET. In the figure, 11m is a P-type well region, 21 is an n-type channel stopper formed on the surface of the substrate 10 so as to span a part of the well region 11m, and 95.96 is an n''-type source region and drain region. .

63 is a gate insulating film made of silicon oxide; 60 is a gate insulating film made of silicon oxide;
The surface of the substrate 1 and the well region other than the region where elements such as MISFET are formed is coated with [5 thick silicon oxide film, 84 is n
The gate electrode 120 is made of type polycrystalline silicon, and the insulating film 121 is made of, for example, link-licade glass. 1
Reference numerals 22 denote a drain electrode and a source electrode, each made of, for example, vapor-deposited aluminum.

In the blank space of FIG. 9 below, the substantial drain region of the MISFET is constituted by a region 9S for contacting the electrode 121 and a channel stopper 21. The channel stopper 21 is for preventing a parasitic channel from being induced on the surface of the n-type substrate 10, and has a relatively low impurity concentration. Therefore, the portion of the channel stopper 21 extending above the P-type well region 11m has a sufficiently higher resistivity than the region 95 for contacting the electrode 121. The MISFET shown in FIG. 9 has a channel stopper as a part of the drain region as described above, and thus has a large drain breakdown voltage.

Therefore, in the embodiment, the n-type substrate 1 is connected to the high voltage terminal V
PP (see Figure 1) and this high voltage terminal VPP.
The MISFET has the structure shown in FIG. 9, in which the drain is connected to the MISFET.

That is, the write inhibit voltage generation circuit IHA2 in FIG.
depletion type MISFET Q26, Q2 in
9, Q32, depletion type MISFETO19 in write circuit WAI, WA2, depletion type MI 5FETQ40, O4 in erase circuit ER8
3 and the enhancement type MIS in the level shift circuit or voltage divider circuit (Q37 to Q39) in the control circuit CI'LL, and the FET Q37 with the structure shown in FIG.
ISFET.

Note that, in the depletion type MISFET, as will become clearer from later description, the P
It is formed by ion-implanting a P-type impurity, such as boron, into the surface of the type well region 11m.

FIG. 10 shows a cross-sectional view of an npn transistor. In the figure, the n-type substrate 1 is used as the collector region of the transistor, the P-type well region 11n is used as the base region, and the n+-type region 97 is used as the emitter region. The n+ type deposit 97 is formed at the same time as the source region and drain region of the MISFET. Above n
pn) transistors are used in the erase circuit ER8 of FIG.

The above-mentioned MNOS and various MISFETs may have a structure having an aluminum gate, but it is preferable to have a structure having a silicon gate as described above.

Therefore, when explaining in detail the structure of the elements and wiring constituting each of the above circuits using silicon gate technology below, the manufacturing method will first be explained for easier understanding.

Hereinafter, a manufacturing process for forming an MNO8 element, an enhancement type MO8 element, a depletion type MO8 element, and a bipolar transistor on two semiconductor substrates will be described in detail based on FIGS.

(a) n having a (100) crystal plane as the substrate wafer 1
type single crystal, resistivity 8~12Ω (7FI (impurity concentration approx. 5
A silicon (Si) wafer of X I Q 14 cm") is used. The resistivity of this wafer is preferably as large as possible (low impurity concentration) in order to form wells with low impurity concentration with good reproducibility. The EAROM shown here (Electrically Altera
In the example of ble Itead 0nly Memory (electrically rewritable read-only memory), the impurity concentration of the well was set to about 3 x 1 o"cIn'.
l) Using wafers.

As shown in FIG. 11(G), the surface of the silicon wafer 1 is cleaned with an appropriate cleaning solution (O, -H, SO4 solution or HF solution), and then a thermal oxidation method is used to clean the surface of the silicon wafer 1 to about 50 nm.
A silicon oxide film (Si02) 2 is formed, and then C
VD (Chemical Vapor Deposit)
A silicon nitride (S13N4) film 3 is formed to a thickness of about 100 to 140 nm by a chemical vapor deposition (chemical vapor deposition) method. This Si, N4 film formation method was compared using an atmospheric pressure vertical CVD apparatus, an ordinary pressure horizontal CVD apparatus, a low pressure horizontal CVD apparatus, etc., but no particular difference was found. However, the film thickness obtained using a low-pressure CVD apparatus has the best uniformity, and is within ±3% within the wafer, which is convenient for microfabrication. Although there are some differences depending on the method, the appropriate deposition temperature is in the range of 700 to 1000°C.

This result is also the same for the Si and N4 film formations used below.

(2) Next, a photoresist film 4 is formed on this silicon nitride film 3 by photoetching only in areas other than the areas where wells are to be formed (between the wells). In other words, the Si and N4 films are exposed on the surface of the region where the well is to be formed. In this state, the exposed portion of the Si3N4 film is removed by plasma etching, and a SiO2 film 2 is formed on the surface as shown in Figure 11 (■).
expose. After that, using the resist film 4 as a mask, boron (B) ions were injected into the Si substrate in the portion where there was no resist film through the Si film 2 exposed on the surface at an energy of 75 KeV and 3 x 10
Form implanted P-type semiconductor regions 5, 6 with a thickness of 1.5 cm2.

0 After that, after removing the resist film 4, dry (
Well diffusion is performed in dry) oxygen (02). Since boron becomes an acceptor type impurity in Si, a P-type well is formed. As a result of diffusion at 1200°C for 16 hours, the formed P-type wells (10, 11) have a surface concentration of 3
x 10"cm', and the diffusion depth is approximately 6 μm. However, this value is based on the results of measuring the surface sheet resistance using the four-probe method and the diffusion depth using the stain etching method. This value is obtained assuming that the distribution is a Gaussian distribution.The reason why well diffusion is performed in oxygen is to form a uniform well with a low concentration.

At the time when the well diffusion is completed, as shown in FIG.
An oxide film of about 10 μm is beginning to be formed on the surface of the N4 film 3. Therefore, by etching the entire surface with Si02, approximately 50n
By removing m of the SiO2 film f, a thick silicon oxide film 12.13 of approximately 0.8 μm remains on the well surface, and the surface of the Si, N4 film 3 is exposed between the wells.

0 Next, the Si3N film 3 is heated with hot phosphoric acid (H3PO4
) solution, etc., and remove the S io2 film of about 50 nm that was initially formed between the wells (Fig. 11 (Q
14, 15, 16) are exposed. In this state, approximately 50 nm of SiO
A film is formed. In this state, phosphorus (P) ions are implanted into the entire surface at an energy of 125 KeV and a dose of I x 10'' cm-2. In this case, the thick Sio film 12.13 on the well serves as a mask. , phosphorus ions are not implanted into the wells except for the periphery of the well region, and phosphorus ions are implanted between the wells to form N-type semiconductor regions 20, 21, and 22. The well expands laterally from the edge of the Si3N4 film used as a mask during the well diffusion, and there is a difference of about 6 μm at the edge of the Si, N4 film (that is, the edge of the thick S io2 film above the well). In other words, the phosphorus ion implantation layer is formed from the well end to a distance of about 6 μm into the well.In addition, this phosphorus ion implantation layer is When measured after passing through the heat process, the depth was approximately 1 μm.

In this way, conduction between the wells (P type) can be prevented by implanting phosphorus ions between the wells in a self-aligned manner.
．． 22 S A P (Self Al i-gned
P chaunel field ion 1nsp
This layer is called the "layout" layer.

As mentioned above, the p-type well diffusion region is formed by heat treatment in an oxidizing atmosphere using the Si, N4 film as a mask,
By using a thick oxide film formed on the well surface as a mask, N-type impurities are implanted into the surface of the N-type substrate between the wells across each well to form a SAP layer for preventing channel generation between the wells. Ion implantation between wells can be performed without increasing the number of masks, and the well diffusion region and the ion implantation layer between wells can be formed in a self-aligned manner. This technique will hereinafter be referred to as the SAP method.

Thereafter, all of the S i 02 films (12, 13 and 14, 15, 16) formed on the surface of the substrate 81 are removed. In this state, a p-type well region (
10, 11) and n-type (having an impurity concentration higher than the substrate n-type impurity concentration) regions (20, 21, 22) are formed, and furthermore, at the boundary between the two, there is a thickness of about 0.4 to 0.
An unevenness 17 (step) of 5 μm is formed. Using this step, mask alignment for the next photoetching process can be performed.

Next, the so-called LOCO8 (Local 0xi-
A process called oxidation is carried out.

(g) First, as mentioned above, after removing all the SiO□ film on the Si surface, about 50 nm of S
io, the film 24 is formed by a thermal oxidation method. Subsequently, by CVD method, 100 to 140 nm was deposited on this SiO□ film.
A 5isN+ film of m is formed.

Next, by photoetching, a photoresist film is left only in predetermined areas such as areas where active elements will be formed (35, 36, 37° 38, 39, 40 in Figure 11 ■).
). That is, in this state, the photoresist film is removed and the Si and N4 films are exposed on the surface of the portions where it is necessary to form a thick oxide film for isolation between elements. In this state, plasma etching is performed to remove the exposed 5i.
sN, the film was removed and the approximately 50 nm 5 layer previously formed on the surface was removed.
The in2 membrane (24) was exposed. After that, using the resist film as a mask, pass the 5hot film (24) exposed on the surface into the Si substrate where there is no resist film.
Boron (B) ions are implanted with an energy of 75 keys and a total dose of 2×10 cm 2 to form p-type semiconductor layers 41, 42, 43, 44, and 45° 46. At this time, the photomask is designed so that the end of the 5i3N4 film is located in the SAP implant layer at the end of the well where it is necessary to form a high breakdown voltage DMOS. - By doing this, an active region is formed spanning the SAP layer (21) and the well, as shown in FIG. 11 (2). In addition,
This boron/ion implantation is hereinafter referred to as field implantation (F implantation).

[F] Thereafter, after removing the resist film, field oxidation is performed in wet oxygen (02). By performing this oxidation treatment at 1000° C. for about 4 hours, a S r O film (60) of about 0.95 μm is formed on the surface of the Si substrate where the Si and N4 films have been removed. In this state, a portion where a thick field oxide film of approximately 0.95 μm is formed between the wells, for example, the first
Figure 1 [F] The Si surface of 20 contains phosphorus due to SAP and F
There is a mixture of implant-based poro/polymers, and the dosage is 1 x 10" cm for phosphorus and 2 x for boron.
Although a larger amount of boron is implanted at 10 cm 2 , the amount of boron that segregates into S r 02 during field oxidation is greater. In other words, boron in Si is S io, It depletes at the interface with the
Since phosphorus in Si piles up (accumulates) at the interface with SiO2 (see Figures 28 and 29), the surface between the wells will eventually have a large concentration of phosphorus and will not close to the channel stopper. It fulfills the role of ℃. In this way, by sharing the above-mentioned SAP method and the T, OCOS process and making good use of the difference in behavior between phosphorus and boron at the SiOx interface as described above, it is possible to implant phosphorus at the lowest possible concentration without using a masking process. (This is necessary for use as the drain of the high-voltage depletion MO8FET DMO8, which will be described later) and boron implantation, which requires a higher dose (to keep the threshold voltage of the parasitic MO3 (field MO3) high to a certain extent). It becomes possible to develop a process technology that allows the coexistence of phosphorus (necessary matters) and ultimately increases the phosphorus concentration.

Thus, the p-type ion implantation layers 41 to 16 in FIG.
A p-type semiconductor region 5 is formed under a thick oxide film on the substrate surface corresponding to
1 to 56 are formed.

Now, in the state immediately after this field oxidation is performed, as shown in FIG. 11 [F], about 5
Approximately 100 to 140 nm on the 0 nm Si02 film 24
5i3N, film (25-30), and about 2
An oxide film with a thickness of 0 nm is formed, and a 5102 film (60) with a thickness of about 0.95 μm is formed in the field region (
・Ru.

(Q In this state, if the entire surface is etched with Sio2 and the 5in2 film of about 50 nm is removed, a Si film 60 of about 0.9 μm will remain in the field region, and a 5in2 film 24 of 50 nm in thickness will remain in the active region. and 1
00~i40nm Si, N4 film 25~30 remains,
This Si3N4 film is exposed. So I continued to bow,
The Si, N4 films 25 to 30 are coated with hot phosphoric acid (H
Remove using 3PO4) solution or the like.

In this way, the previously formed 5in2 film 24 of about 50 nm remains in the active region, and this 5in2 film 24 remains in the active region.
It is also possible to use the in2 film 24 as the active MISFET gate oxide film, but due to the abnormal region (generally thought to be Si or N4 film) that occurs at the Locos edge, the gate breakdown voltage may be lowered. Therefore, as shown in FIG. 110, this thin oxide film 24 and the 5isN4 film thereon are removed once, and then, for example, after repeating the formation and removal of 5102 of 45 nm,
As shown in FIG. 11H, a S r 02 film (62 to 67) of about 75 nm to be actually used as a gate insulating film is formed at 1000° C. for 110 minutes in dry 02, for example.

0 Furthermore, among MOS transistors, EMOS (
Enhaucement mode MOS: L/
In order to set the threshold voltage (which has a high threshold voltage and the current is practically 0 at the gate voltage Ov), boron ions are implanted into the entire surface through the thin gate insulating films 62 to 67 with an energy of 40 KeV, )-Tardose 2× 101'/
Insert with Crn2 (Fig. 11 (-) 71-76).

Naturally, this boron is not implanted in the field region which has a thick oxide film, and the S under the part of the active region where about 75 nm of SiO□ film is present.
Implanted through the 5102 film onto the i-substrate surface.

(I) Next, since the EAROM described in this example uses an E/D inverter to speed up the peripheral circuit,
In addition to EMO3 mentioned above, DMO8 (De-pleti
It is necessary to form an on mode MOS (one in which the L threshold voltage is low and a current flows at a gate voltage of O). In order to form this 0MO3 in a predetermined part, S i0
After depositing a photoresist film on the two films 60, 62 to 67, the photoresist film on the area where 0MO3 needs to be formed is removed by a photoetching process as shown in FIG. The photoresist film 80 is left and, using this as a mask, phosphorus ions are implanted only in predetermined portions (81), and a threshold voltage of 0MO3 is set. Here, for example, energy 100I (
eV.

Implantation was performed at a dose of 1.2 x 10'2 films/cm2. This also applies to the region of the high voltage DMO8 (11th
Figure (I) 81). In this way, by forming depletion MO8FETs on the boundary surface around the wells created by the self-aligned separation method (SAP) between wells, it is possible to eliminate the need for an increase in the number of photomasks on the same chip, as can be seen from the following explanation. Non-volatile memory element MNO8 and high voltage resistance D
It becomes possible to coexist with MO3.

(Next, after removing the above photoresist film 80,
Sio, polycrystalline silicon (po
A layer of about 0.35 μm and about 580° C. is formed. Regarding the polysi formation method, a normal pressure method and a low pressure method were also compared, and apart from the fact that the latter method was superior in film thickness uniformity, there were no particularly large differences in characteristics. Subsequently, polySi was doped with phosphorus by a diffusion method. The conditions in this case are, for example, 1000℃
Then, P from the source was deposited and diffused on the polySi surface for 20 minutes, and then stretched for another 5 minutes.
The resistance of poly Si was set to about 15Ω/mouth.

After that, after removing the phosphorus glass formed on the polysi surface by etching it with a solution containing HF, etc.
The photoresist is left only in a predetermined area using the photoetching method, and the polysilicon is removed from the area other than the remaining photoresist using the plasma etching method.
A gate electrode and wiring were formed using a first layer of polySi on the N2 film (FIG. 11g) 8j, 84).

Next, using the first polySi layer (83, 84) as a mask, the gate oxide film 62 is selectively etched to partially expose the substrate surface as shown in FIG. 11(J).

■ After this, oxidation is performed at 850°C for 20 minutes in a wet atmosphere, and approximately 40 nm of S is added to the exposed Si substrate surface.
A S t 02 film (85, 86) of about 200 nm is formed on the polySi surface. After this, by etching the entire surface of the SiO□ film and removing approximately 60 nm of the Si film,
About 140 nm of S io2 is left on the ly Si. In order to form a thick oxide film on polySi and a sufficiently thin oxide film on the surface of the Si substrate, it is necessary to add at least 10" of phosphorus to the polySi.
It is important to contain at least m' and to perform the oxidation in a wet atmosphere at a temperature in the range of 600 to 1000°C.

(G) Next, using the SIO2 film 85°86 left on the polySi as a mask (in other words, the SiO2 film in this case
□ prevents etching of the highly doped first layer poly Si), and the exposed Si substrate surface is etched with NH
After light etching with an etching solution containing 3-H,02 and HC4-H,O, a thin oxide film (approximately 2 nm thick) is formed.
Figure 11 σ088) in N2 diluted 02 at 850℃, 12
It is formed by oxidation for 0 minutes, and then a Si, N+ film (90) of about 50 nm is formed by CVD method for 1-minutes. Here, the formed Si and N.

Various film formation methods were compared as mentioned above, but in the end, high-temperature l-I2 annealing, which will be described later, provided satisfactory characteristics in all cases.

After this, polySi is deposited on this 5isN4 film 90.
After depositing a layer (second layer) of about 0.3 μm, it is processed by photoetching to form a second layer (second layer) of polySi.
A gate (FIG. 11, ■91) is formed. Subsequently, using the second layer polysi (91) as a mask, 1×10
16cm'', phosphorus ions are implanted into the silicon substrate at 90 KeV to form N-type semiconductor regions (92 to 100) such as sources and drains, and at the same time, the second layer polys
i91 was also doped with phosphorus. At this time, since the first layer of polysi (83, 84) has already been doped with phosphorus and the crystal grains have increased, phosphorus is implanted into the Si substrate surface under the first layer of polysi by implanting phosphorus ions. However, as mentioned above, the first layer p
On the olysi is a SiO□ film 85. of about 140 nm.
86 and a 5 Q nm Si, N4 film 90, this risk is eliminated.

Next, using the Si3N4 film (90) formed under the second layer polysi 91 as a mask, the second layer polysi 91 is deposited.
After selectively oxidizing lySi (91,84) in a wet atmosphere at 850°C for 10 minutes, this oxide film (10
Using 2) as a mask, Si, N, and films are selectively removed. In other words, the highly doped second polysilicon layer is protected from the 5isN etching solution by the upper oxide film. In this state, the breakdown voltage between the second layer polyS1 gate and the source or drain (gate breakdown voltage) is poor, so after this, oxidation treatment is performed in a wet atmosphere at 850°C for 30 minutes to increase the gate breakdown voltage of the second layer polyS1 gate. In addition, the shape of the edge of the first layer polysi (83, 84) gate has been improved to improve the breakdown voltage. In this state, as shown in FIG. 11(b), the first layer
On the lySi layer 83.84, about 0.3 μm of S r 0
2 films 85 and 86 are made of approximately 0.2 μm of SiO on the second polySi layer 91 and the source and drain n+ diffusion layers.
□Membranes (102, 104 to 112) are formed.

As mentioned above, using a material that can withstand high temperatures such as polysilicon as a gate electrode, MO3
After forming the device, an oxide film is formed on this gate electrode using a low-temperature oxidation method, and a thin 5iO film is formed on the Si substrate (well).
After removing the Z film, a 5in2 film was formed on the substrate, and a Si and N4 film was placed on top of it.
A gate electrode of i is formed, the poly-Si gate surface is oxidized using the Si, N4 film as a mask to form an oxide film, and the Si3N4 film is removed using this oxide film as a mask.
By adopting the method of forming three MNO elements as shown in FIG. M, the eight MNO elements are formed after the MOS, thereby reducing the deterioration of the characteristics of the three MNO elements. Furthermore, since the selective oxidation method is applied to cover the gate of the MOS or MNOS with an oxide film, a device with favorable characteristics such as interlayer breakdown voltage or interlayer capacitance can be obtained.

In this way, three MNO elements are formed, and in accordance with FIGS.
When the element forming portion is drawn using an enlarged sectional view, it becomes as shown in FIGS. 30 to 33. That is, as shown in Figure 30, 10
A polysilicon layer 91 is partially formed on a Si, N4 film 90 deposited on an extremely thin Sio2 film 88 of less than nm in thickness, and a source/drain is formed within the substrate surface using this polysilicon layer as a mask. Then, as shown in FIG. 31, the surface of this polysilicon layer 910 is oxidized using the Si, N, and film as a mask, and a relatively thick oxide film (Sin2) 102 is formed on the surface. Furthermore, as shown in FIG. 32, the formed oxide film 10
Using 2 as a mask, the Si, N, and film 90 are partially etched away. At this time, the thin 5in2 film 88 is also removed from the substrate surface, but as shown in FIG. 33, an oxide film (Sin2) 104, 105 is formed on the surface of the exposed source/drain region by heat treatment in an oxidizing atmosphere. Form. Depending on the combination of the gate electrode material and the Si or N4 film etching solution (or gas), the gate electrode may also be etched. Since the electrode is covered with an oxide film and the Si and N4 films are etched using this oxide film as a mask, this method can protect the fine gate electrode even when the gate electrode material is etched with Si, N, and etching solution. can. Furthermore, as shown in FIG.
and S io formed on the silicon substrate (well) surface,
Since the Si, N, and film 90 are completely covered with the films 104 and 105, by performing sufficient oxidation treatment in this way, a so-called protected gate is formed.
Since the gate structure can be formed in a self-aligned manner, the gate breakdown voltage of the MNO3 element can be improved and the parasitic capacitance can be reduced.

Furthermore, as can be understood from FIGS. 30 to 33, pixel elements including an MNO8 element and an MO8 element are formed on the same semiconductor substrate, and the Si, N, and film 90 are left only under the gate of the MNO3 element. Therefore, as shown in FIG. 33, in the oxidation treatment performed to improve the gate breakdown voltage of the MNO8 element as described above, the end of the gate electrode of the MO3 element is also oxidized, creating an inverted canopy structure. Since the breakdown voltage can also be improved, the gate breakdown voltage of both types of elements can be improved as a result.

(f) Next, after completing the process in Fig. 11 (b), each of the above oxide films is electrically connected to the underlying n+ layer or polysi layer as shown in Fig. 11 using a photoetching method. If you need to make a connection, for example (106,11
2) Then, a predetermined portion of the S io 2 film that needs to be in contact with the p-type well, for example (110°111), is removed by etching. In this case, about 0.3 μm of S
Since the iO film etching is performed, only a portion of the oxide film in contact with the p-type well is etched, leaving about 0.3 μm of the SiOz film.

0 After that, after removing the photoresist film used in the above step, a 7-osilicate glass (hereinafter referred to as phosphorus glass) 20 with a P2O2 concentration of about 1 mol was removed by CVD.
After that, heat treatment was performed at 900°C for 20 minutes in H7 atmosphere to densify the phosphorus glass and MNO3
Improve the characteristics of the element.

Thereafter, the areas where electrical connections need to be made with the N+ layer, polysilicon layer, p-type well layer, etc. described above are removed by a phosphorus photoetching method. At this time, holes (114 to 118) in the oxide film were opened to the light.
Then, the holes in the phosphor glass share at least a part of the area, and the surface of the Si substrate in that area or the po
Expose the lysi surface. In this state, the film thickness of the parts (116, 117, 60) that make contact with the p-type well decreases slightly due to over-etching during photo-etching, but the film thickness is still approximately 0.2 μm.
Since some of the Sin and film remained, the remaining approximately 0.2 μm was further removed by photoetching so that the hole in the photoresist was placed inside the hole in the phosphor glass that had been previously drilled.
5i02 film is removed by etching.

When making a contact hole in a double layer film of phosphor glass and 5iOz film, the etching speed of phosphor glass is fast <5in.
Since the etching speed of 2 is slow, there are processing problems such as the size of the holes becoming large or the adhesion between the photoresist and the phosphor glass worsening if holes are made in the two-layer film at once. As can be seen from the explanation of (v) and Fig. 11 0) and the partially enlarged views Figs. 119), then depositing phosphor glass (120), and then drilling a hole in the phosphor glass layer 120 so as to share at least a part of the contact hole 119 to form a hole 125. , the pattern hole drilling can be performed more accurately than the design value. In addition, in FIG. 36, the hole 125 of the phosphor glass is SiO, and the hole 119 of the film is SiO.
Although the diagram shows a slightly shifted form, in order to prevent the metal wiring such as aluminum from breaking, the pressure is applied so that all the holes 119 of the 5in2 film are exposed, preferably even the edge surface of the SiO film. It is preferable to form a hole 125 made of phosphor glass.

[F] Next, after removing the photoresist used above, an At vapor deposition film is formed on the entire surface at about 300°C. The film thickness is approximately 0.8 μm.

Next, by photoetching, a wiring pattern is formed on the At film as shown in FIG. 11 to form aluminum electrodes or wiring portions 121, 122, 123.

After forming 124 and removing the photoresist, the above A
In order to ensure contact with the t and n, poly Si or p-type wells, and to reduce surface states, heat treatment is performed at about 450° C. for 60 minutes in an H2 atmosphere.

By completing the steps to [F] described in detail above, as shown in FIG. Together with the depletion type MO3 element, an NPN bipolar transistor consisting of the semiconductor region 97.11.1 can be formed in and on one semiconductor substrate 1 without increasing the number of special photomasks. In addition, 121 in the same figure is EMO
122 is the emitter electrode of the bipolar transistor, 123 is the base electrode of the same transistor and the electrode of the p-type well region 11, 1 is the source or drain electrode of 8 elements,
24 constitutes the region 22 and the electrode of the substrate.

FIG. 15 shows a plan view of the memory array before forming the phosphor glass layer, and FIG. 16 shows a plan view of the memory array after forming the aluminum wiring. Also the first
7, FIG. 18, and FIG. 19 respectively show a section taken along line AA, section taken along line BB, and section taken along line CC of the plane shown in FIG. 16.

The memory array consists of P
It is formed on the mold well region 10a.

In FIG. 15, the source region, drain region, and channel region of the MNOS of the memory cell and the switch MISFET are shown separated by dashed lines. Areas CHI and CH2 surrounded by the dashed line above
A thick silicon oxide film 60 is formed on the other surfaces of the P-type well region 10a.

On the surface of the P-type well region 10a, a plurality of regions CHI and (jI2) are formed through a silicon oxide film in a direction crossing the regions CHI and (jI2), which are used as gate electrodes of MISFETs for switching of memory cells and as first word lines. Polycrystalline silicon layer W
l 1 , W21 , W31°W41 are arranged.

Similarly, a plurality of polycrystalline silicon layers W12 .
W22. W32. W42 is placed.

an area CHI not covered with each of the polycrystalline silicon layers;
An n-type impurity is introduced into the surface of the P-type well region 10a in CH2 by the manufacturing method explained with reference to FIG. has been done.

In area CHI, n+ type region 92a polycrystalline silicon layers Wl 1 , Wl 2 and n+ type region 92a,
A first memory cell is configured. That is, the n+ type region 92a constitutes the drain region of the switching MISFET, and the polycrystalline silicon layer Wll constitutes its gate electrode. Further, the polycrystalline silicon layer W12 constitutes a gate electrode of the MNOS, and the n-type region 94a constitutes its source region.

Within the area CHI, the n+ type region 92b polycrystalline silicon layer W21. is adjacent to the first memory cell. W
22 and n+ type region 94b constitute a second memory cell. That is, 92b above.

W21. W22 and 94b are respectively MIS for switches.
It forms the drain region of the FET, the gate electrode thereof, the gate electrode of the MNOS, and the source region thereof.

Similarly, within said area CHl, 94c.

W32. W31,92c constitutes the third memory cell,
92d, W41. W42 and 94d constitute a fourth memory cell.

In areas adjacent to the area CH1, first to fourth memory cells are also configured, although no symbols are attached thereto.

Each memory cell formed within the area CHI constitutes a first memory cell column, and similarly each memory cell formed within the area CI-I 2 constitutes a second memory cell column.

The polycrystalline silicon layer Wll as the first word line
As shown in FIG. 5, an extended portion Wl extends across the bottom of the polycrystalline silicon layer W12 on the thick silicon oxide film 6°.
I have LA or Wllc.

Since the polycrystalline silicon layer W12 constitutes the second word line as described above, the voltage of +25V is applied when writing the storage information.
will be exposed to high voltages such as Therefore, a parasitic channel may be induced in the surface of the P-type well region 10a under the polycrystalline silicon layer W12. The polycrystalline silicon layer Wll constitutes a first word line and receives a low voltage signal such as +5V mentioned above. Therefore, the parasitic channels induced on the surface of the P-type well region 10a under the polycrystalline silicon layer W12 are blocked under the extensions W11a to W11c of the polycrystalline silicon layer Wll, respectively. become.

As a result, the memory cells in the areas CHI and CH2 are electrically coupled to each other by the parasitic channels, and as a result, it is possible to prevent undesirable operations such as information not being written to the memory cells to be selected. .

A phosphorus glass layer 120 is formed on the surface of the memory array shown in FIG. 15 by the manufacturing method described in FIG. Open hole CNT1 exposing the territory area
to C5 (see FIG. 6) are provided.

Next, aluminum is deposited and selectively etched (as shown in FIG. 16, the aluminum wiring layer ED
1. ED2. DI and D2 are formed.

The wiring layer EDI has the openings CNT1 and CN, respectively.
In T3 and CNT5, the n++ region 94 serves as the source region of the MNOS in the first to fourth memory cells.
a, 94b, 94c and 94d (see FIG. 15). Therefore, this wiring layer EDI constitutes a reference potential line of the memory array.

The wiring layer D1 has the above-mentioned open holes CNT2 and CNT4, respectively.
At this point, the n+ type regions 92a, 92b, 92c, and 92d, which serve as drain regions of switch MISFETs in the first to fourth memory cells, are contacted. Therefore,
This wiring D1 constitutes a digit line of the memory array.

Similarly, wiring layers ED2 and C2 constitute other reference potential lines and digit lines, respectively.

As shown in FIG. 15, the above memory array has an MNOS and a switching M
The arrangement with the I5FET is alternately reversed. Therefore, the n+ type regions of adjacent memory cells, such as 92a and 92b, 94b and 94c, can be shared in common, and compared to the case where the n+ type regions for each memory cell are formed independently, The dimensions of can be reduced.

Also, as shown in FIG. 16, an area C where memory cells are formed
The aluminum wiring layers EDI, ED2, DI, and D2 are placed in the above area C so that the wiring areas are also formed on HI and Cl-12.
Since HI, CH2 are inclined with respect to the direction in which they extend, the dimension in the row direction, that is, in the horizontal direction of the page, can be made smaller than in the case where the wiring area is set independently of the above area. .

In addition, since an aluminum wiring layer is used as the reference potential line and the digit line as shown in the figure instead of using a semiconductor such as an n++ semiconductor wiring area, the resistance thereof can be made sufficiently small. The reduction in interconnect resistance allows the memory array described above to operate at high speeds.

Fig. 20 shows the pattern of the unit X decoder before forming the phosphor glass layer, and Fig. 21 shows the pattern after forming the aluminum wiring layer in the portion corresponding to Fig. 20 above. .

Since each unit X decoder is provided corresponding to a memory cell row of the memory array, each unit X decoder is taken into account so as not to increase the pitch of the memory cell row. Therefore, although not particularly limited, as described below, in FIGS. 20 and 21, the combination of two unit X decoders is substantially one unit.

In FIG. 20, the X decoder consists of an n-type silicon substrate 1
It is formed on the P-type well region 11 formed above. The area for forming each MI 5FET is surrounded by a dashed line in the figure. The surface of the P-type well region 11 other than the above region is covered with a thick silicon oxide film 60 as described above.
is formed.

On the silicon oxide film 60 and the gate oxide film on the region surrounded by the dashed line, a first polycrystalline silicon layer Wl having a pattern as shown by the combination of dots and solid lines is formed.
1, W21, aO, ao'al, and al' are formed. Of the region surrounded by the above-mentioned dashed-dotted line, an n+ type region is formed by the manufacturing method shown in FIG. 11 above except under the above-mentioned polycrystalline silicon layer.

In FIG. 20, under the polycrystalline silicon layer in the diagonally shaded area on the lower left, there is an enhancement type MISF.
This means that the channel region of the ET is formed, and the two diagonal lines on the lower left and lower right are combined, and the channel region of the depletion type MISFET is formed under the polycrystalline silicon layer in the shaded area. This means that a region is formed.

In the upper half of the paper in FIG. 20, the n+ type region VC
Depletion type MISFETQ3 is constituted by Ca, polycrystalline silicon layer Wll, and n+ type region Wllb, and n+ type region Wllc, polycrystalline silicon layer aO' and n
Enhancement type MIS by + type area GNDa
A FETQ4 is configured, and an ennounment type MISFETQ5 is configured by the n+ type region Wllc, the polycrystalline silicon layer al', and the n+ type region GNDb.

Similar MISF in the lower half of the paper in Figure 20
ETQ3', Q4' and Q5' are constructed.

As shown in FIG. 21, a phosphor glass layer 120 is formed on the surface of the decoder shown in FIG. 20, and then holes are formed in the phosphor glass layer and the oxide film thereunder by selective etching.

By aluminum evaporation and selective etching, the 21st
Various aluminum wiring layers are formed as shown in the figure. In addition, in the figure, the openings provided in the phosphor glass layer and the insulating film such as the oxide film are indicated by X marks. Therefore, each aluminum wiring layer contacts the underlying polycrystalline silicon layer or semiconductor region at the X-marked portion.

In FIG. 21, a wiring layer Wlla is a wiring layer for short circuiting, and includes a polycrystalline silicon layer Wll as a gate electrode of MISFETQ3 (see FIG. 20), its source region, and the MISFETQ4. The n+ type region Wl l b serving as a common drain region of Q5 is short-circuited. The wiring layer vCC is a wiring layer for power supply, and MISFETQ3
and Q3' (see FIG. 20) are in contact with the n+ type region VCCa as a common drain region. The wiring layer GND has a wiring layer for grounding, MI 5FETQ4, Q4'
It is in contact with the n+ type region GNDa, which serves as a common source region. In addition, as shown in FIG. 20, MISFETQ5.
The n+ type region GNDb as a common source region of Q5' is continuous with the n+ type region NDa.

The wiring layers aO and aO are a pair of wiring layers that receive address signals of opposite phases to each other, and a selected one of them, that is, aO in the illustrated case, is in contact with the polycrystalline silicon layer aO' and aO''. are doing.

Similarly, wiring layers a1 and al are a pair of wiring layers that receive other address signals having mutually opposite phases. In the case shown, wiring layer a
1 is in contact with the polycrystalline silicon layer al', and the wiring layer a1 is in contact with the polycrystalline silicon layer 31''.

As described above, a unit decoder such as the X decoder XDI of FIG. 1 is configured in the upper half of FIG. 12, and another unit decoder such as XD2 is configured in the lower half.

The unit X decoders are arranged corresponding to memory cell rows. Therefore, the wiring layer VCC, GND.

ao, aO, al, al, etc. are common to a plurality of unit X decoders.

FIG. 22 and FIG. 22B show the pattern of the unit write circuit before forming the phosphor glass layer, and the second
Figure 3 Person and Figure 23 B are the same as Figure 22 A and Figure 2 above, respectively.
2 shows a pattern after forming an aluminum wiring layer in a portion corresponding to FIG. 2B. The right end of the pattern in FIG. 22 is connected to the left end of FIG. 22B, and similarly the right end of FIG. 23 is connected to the left end of FIG. 23B.

Above FIG. 22A, I3. The patterns in FIGS. 23A and I3 are shown using the same notation as in FIGS. 20 and 21.

For the same reason as the X decoder, the two unit write circuits are essentially one unit.

A polycrystalline silicon layer W serving as a first word line is extended over a P-type well region 10b indicated by a two-dot chain line for configuring a memory array through a thick silicon oxide film 60.
ll and W21 are aluminum wiring layers W11C, respectively.
, W21C formed in the P-type well region 11
ISFETQ15. Q15' drain region Wild,
Contact W21d.

As shown in the figure, an aluminum wiring layer e to which a signal from an erase circuit (see FIG. 1) is applied is in contact with the P-type well region 10b.

A signal from a control line We (see FIG. 1) is applied to the polycrystalline silicon layer We serving as the gates of the MISFETs QI 5 and Ql 6.

Polycrystalline silicon layer W12°W22 as second word line
are aluminum wiring layers W12a, respectively.

A common drain region W12b of MISFETs Q16 and Ql7 formed in the P-type well region 11 indicated by the two-dot chain line is connected to the common drain region W12b of the MISFETs Q16' and Q1 through W22a.
7' and the common drain region W22b, and further contact with the polycrystalline silicon layers Wl 2c and W22c, respectively.

Above MISFETQ16. Q17. +5V to the polycrystalline silicon layer VCC as a common gate of Q16'Q17'
power supply voltage is applied.

Common drain region G of MISFETQ18 and Q18'
NDa has an aluminum wiring layer GN that is set to the ground potential.
D is in contact.

The polycrystalline silicon layer W 12 c serves as the gate electrode of the MI 5FET QI 9 formed in the independent P-type well region 11r, and the source region W 12 e of the MISFET Q 19 and the P
It is in contact with the mold well region 11r.

Similarly, the polycrystalline silicon layer W22c connects the MI 5FETQ19' formed in another independent P-type well region IIs.
The aluminum wiring layer W2 serves as the gate electrode of 46
2d, the source region W of the MISFETQ19' is
22e and the P-type well region IIs.

The above MISFETs QL9 and Q19' have the structure as explained in FIG. 9 or FIG.
The above MI 5FETQ extended on the type 7 recon board l
The common drain region VPPa of I 9 and Q19' is in contact with an aluminum wiring layer vPP to which a high voltage for writing and erasing is applied.

For example, the circuit WAI in FIG. 1 is configured by the MI 5FETQI 5 to Ql9,
19' constitutes another circuit WA2.

The unit write circuits shown in FIGS. 22A and 22B and FIGS. 23A and 23B are arranged in correspondence with memory cell rows, similar to the X decoder described above.

FIG. 24 shows the pattern of the Y gate before forming the phosphor glass layer, and FIG. 25 shows the pattern of the portion corresponding to FIG. 24 after forming the aluminum wiring layer.

In the polycrystalline crystal layer CD as a common digit line,
Aluminum wiring layer C for connecting unit gates in parallel
Da is in contact.

The above aluminum wiring layer CDa is MISFETQII
and Ql3 are in contact with the common drain region CDb. The polycrystalline silicon layers 'f 1 a tY2a serving as gate electrodes of the MISFETs QI 1 and Ql 3 are in contact with aluminum wiring layers Yl and Y2 that receive outputs from Y decoders MDI and YD2 (see FIG. 1), respectively.

The source region of MI 5FET QI 1 and the drain region of Ql2 are made into a common n+ type region Dlb, and similarly MI
The source region of 5FET QI3 and the drain region of QI4 are a common n+ type region.

A power supply voltage of +5V is supplied to the polycrystalline silicon layer VCC serving as the gate electrode of the MISFETQ12 and Ql4.

The source region Dla of MISFET Q120 is in contact with an aluminum wiring layer D1 as a digit line, and similarly the source region D2a of MISFET Q14 is in contact with an aluminum wiring layer as another digit line.

FIG. 26A and FIG. 26B show the pattern of the write inhibit circuit before forming the phosphor glass layer, and FIG.
Figures A and 27B show the patterns of the portions corresponding to Figures 26A and 26B, respectively, after the aluminum wiring layer is formed. As a pattern, the lower end of FIG. 26A is connected to the upper end of FIG. 26B, and similarly the lower end of FIG. 27 is connected to the upper end of FIG. 27B.

As shown in FIG. 6, since the wiring region WIR is arranged between the memory array and the write inhibit circuit, the aluminum wiring layer ED1 as the reference potential line explained in FIGS. 15 and 16 is not particularly limited. , ED2 is each MISFE
A polycrystalline silicon layer ED1a formed simultaneously with the polycrystalline silicon layer of T.

ED2a is brought into contact with each other. Above wiring area WT
In R, the polycrystalline silicon layers EDla, ED
Various aluminum wiring layers are formed on la through an oxide film and a phosphorous glass layer.

Note that FIGS. 26A and B and FIGS. 27A and B are shown using the same notation as each of the above figures. Therefore, the second
A description of the structure of the write inhibit circuit in FIGS. 6A and 6B and FIGS. 27A and 13 will be omitted.

According to this invention, as shown in FIG. 6, since the decoder and the write circuit are placed across the memory array, the operating speed, particularly the read operating speed, can be increased. On the other hand, if the decoder and write circuit are placed on one side of the memory array, for example, the wiring from the decoder to the memory cell becomes long, and since multiple circuits are placed on one side of the memory array, it is difficult to The number of well-known cross-wiring locations will increase. As a result, the signal transmission characteristics of the wiring paths that supply signals to the memory array deteriorate, and the operating speed is limited.

As mentioned above, when placing the decoder and write circuit across the memory array, the pitch between the unit decoder and write circuit can be made relatively small, so the size of the memory array does not have to be limited by these circuits. Become good.

Furthermore, since a gate or decoder and a write inhibit circuit are placed across the memory array, high-speed operation can be achieved for the same reason as above.

As mentioned above, the configuration in which a decoder and a write circuit are placed across a memory array, or the configuration in which a gate or a decoder and a write circuit are placed across a memory array, are different from other configurations that use a write circuit or a write-protection circuit. It can be applied to various types of storage devices.

According to the invention, using the well region as described above,
This well region can be effectively used for high voltage circuits.

In the voltage divider circuit in which the enhancement type MISFETs Q37 to Q39 of FIG. 1 are connected in series, MI
Since the highest voltage is applied to the drain of SFE, TQ37, if this MI 5FET Q37 is destroyed by high voltage, a high voltage will be applied to Q3B via this destroyed MI 5FET Q37. As a result, the MI 5FETs connected in series are destroyed one after another. however,
If MISFET Q37, to which a high voltage is applied, is made to have a structure that utilizes the well region as described above to achieve a high breakdown voltage, other MISFETs Q38 to Q39
Even if it has a normal structure, the above type of destruction can be prevented. The voltage divider circuit as described above can be used in circuit devices other than the memory circuit device of the embodiment.

Similarly, circuits such as the erase circuit and write inhibit voltage generation circuit shown in FIG. 1 can be used for other purposes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory circuit, FIGS. 2, 3, and 4 are operation timing charts of the circuit in FIG.
5 is a block diagram of a semiconductor memory circuit, FIG. 6 is a plan view of a semiconductor memory circuit device, FIG. 7 is a plan view of a semiconductor substrate forming the semiconductor memory circuit device of FIG. 6, and FIG. 8 is a plan view of a semiconductor memory circuit device. A cross-sectional view of the AA' part in Fig. 7, and Fig. 9 are MISFET
FIG. 10 is a cross-sectional view of a semiconductor substrate on which a bipolar transistor is formed, FIG. 11 (A) or 0) is a cross-sectional view of a semiconductor substrate in each manufacturing process of a semiconductor memory circuit device, FIG. 12 is a cross-sectional view of MNoS, FIG. 13 is a characteristic curve diagram of MNoS in FIG. 12,
FIG. 14 is an equivalent circuit diagram of the memory cell, FIG. 15 is a plan view of the memory array before forming the phosphor glass layer, and FIG.
The figure is a plan view of the memory array after forming the aluminum wiring layer, and FIGS. 17, 18, and 19 are the AA', BB', and c-c' sections of FIG. 16, respectively. 20 is a cross-sectional view of X before forming the phosphorus glass layer.
A plan view of the decoder, FIG. 21 is a plan view of the X decoder after forming an aluminum wiring layer, FIG.
Figure B is a plan view of the write circuit before forming the phosphor glass layer, Figure 23 and Figure 23B are a plan view of the write circuit after forming the aluminum wiring layer, and Figure 24 is a plan view of the write circuit after forming the phosphor glass layer. FIG. 25 is a plan view of the Y gate before formation, FIG. 26 is a plan view of the Y gate after forming the aluminum wiring layer, and FIG. Plan view of prohibited circuit, figure 27 person and second person
7B is a plan view of the write inhibit circuit after forming the aluminum wiring layer, and FIGS. 28 and 29 are Si 5
FIGS. 30 to 33 and 34 to 36 are state diagrams showing concentration distributions of phosphorus and boron impurities at the ift interface, respectively, and are cross-sectional views of the main parts of the semiconductor device at each manufacturing process. MA...Memory array, XDI, XD2...X decoder, YGO...Y gate, YDI, YD2...
X decoder, WAI, WA2...Writing circuit, IH
Al: write inhibit circuit, I HA 2: write inhibit voltage generation circuit, EnS: erase circuit, CI'
LL...Control circuit, IO8...Sense circuit, IOR
...output buffer circuit, IOW...data input circuit, BO-BIO...input buffer circuit. Fig.2 Figure 8) ha broom lol

Claims (1)

[Claims] 1. A memory array section formed in a matrix in a semiconductor region on the main surface of a semiconductor substrate, each consisting of a plurality of nonvolatile memory elements each capable of electrically erasing stored information; a peripheral circuit section for controlling the operation of the memory array section formed in another semiconductor region on the main surface of the substrate; and a peripheral circuit section for applying a chip selection signal formed on the peripheral section of the main surface of the semiconductor substrate. A semiconductor memory circuit device comprising a first external terminal and a second external terminal for applying an operation control signal, the semiconductor memory circuit device comprising a chip selection signal applied to the first external terminal and a second external terminal for applying an operation control signal. An erase signal is formed based on an operation control signal applied to an external terminal, and information stored in nonvolatile storage elements in the entire memory array section is erased all at once using the erase signal. Memory circuit device.