JPH02301093A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the size of a cell by comprising one bit with one cell by using a dummy cell, and forming the area of the capacitor of the dummy cell formed with a ferrodielectric smaller than that of a memory cell. CONSTITUTION:The dummy cell B is comprised of a selection transistor 20 and a capacitor 21 with the area smaller than the capacitor 16 of the memory cell A and formed with the ferrodielectric. At this time, a device is set so that a current in which the current to charge the capacitor 21 is added on the current required for the branch of polarization can be larger than the current to charge the capacitor 16. Readout is performed by amplifying the level difference of a bit line 17 and an inversion bit line 22 based on the current that flows from the bit line 17 to the cell A and the current that flows from the inversion bit line 22 to the cell B with a sense amplifier 25. Thereby, it is possible to comprise one bit with one selection gate and one cell, which reduces the size of the cell and attains the making of the device into large capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a reading method for a nonvolatile semiconductor memory device using a ferroelectric material as a capacitor.

[Conventional technology]

Figure 5 is from Electronics, February 18, 1988 issue.
Page 94 (Electronics Feb, 18, 19
88, p.

94) is a configuration diagram of the conventional ferroelectric memory shown in FIG.

The memory cell has a configuration similar to that of a DRAM, and consists of a selection transistor and a capacitor made of ferroelectric material. The selection transistor la has a drain connected to the bit line 3, a gate connected to the word line 4, and a source connected to one electrode of the capacitor 2a. The other electrode of the capacitor 2a is connected to the drive line 5. One bit of data is stored in two memory cells, one memory cell 2a is connected to a bit line 3, and the other memory cell 2b is connected to an inverted bit line (hereinafter abbreviated as bit line) 6. Bit line 3. The bit line 6 is input to a sense amplifier 7, and the level difference is differentially amplified. The sense amplifier 7 is connected to the input/output cover sofa 8. Word line 4 is connected to row decoder 9, and drive line 5 is connected to drive line decoder 10. The output of the address buffer 11 is input to the row decoder 9 and the drive line decoder 10, and one word line 4,
Drive line 5 is selected. Furthermore, a control signal input cover sofa 12 is provided, and the output signal of the sense timing generation circuit 13 is outputted from this control signal input cover sofa 12 .

The address buffer 11 and the input/output cover sofa 8 are controlled.

Next, the operation will be explained.

First, the characteristics of a capacitor formed by sandwiching a ferroelectric material between metal electrodes will be explained using FIG. 6. FIG. 6 (at d+, a positive voltage is applied to the first electrode 14a of the capacitance indicated by 14;
Assume that a negative voltage is applied to the second electrode 14b to cause polarization in the ferroelectric material. After removing the applied voltage, the voltage shown in Figure 6 (a
When the voltage shown in 1 is applied, if the direction of the applied voltage is the same as the direction of the first applied voltage, that is, if it is applied in the same direction as the polarization direction of the ferroelectric material, the sixth
As shown in Figure (bl), the current that charges the capacitor simply flows in. On the other hand, if the current is applied in the opposite direction to the polarization direction, in addition to the iIt current that charges the capacitor as shown in Figure 6 (C1), In other words, when a voltage is applied to a capacitor formed of a ferroelectric material, the current that flows into the capacitor differs depending on the direction of polarization.

Next, the write operation will be explained.

As shown in FIG. 7(a), when writing "1", 5■ is applied to the bit line 3 and Ov is applied to the bit line 6.

Ru. 5V to drive line 5 and word line 4 of selected row
Apply. Then, the ferroelectric material of the capacitor 2b on the side connected to the bit line 6 is polarized in the direction of the arrow. Next, as shown in FIG. 7(b), when the drive line 5 is set to Ov, the capacity is 2.
The ferroelectric material a is polarized in the opposite direction to the capacitor 2b. This completes writing.

Next, regarding a read operation, a case will be described in which a cell in which "1" is written is selected.

First, as shown in FIG. 7(C), the bit lines 3 and 6 are precharged to 5■, and the selected word line 4 is raised to 5■. The current that charges the capacitors 2a and 2b flows into the cell, but the applied voltage condition is such that the polarization is reversed with respect to the capacitor 2b, so I2 is larger than 11 as mentioned earlier. Therefore, the potential of the bit line 6 becomes lower than that of the bit line 3. Reading is performed in this manner. As a result, the potential of the bit line 3 is 5V, as shown in FIG. 7(d).
The potential of becomes OV. Next, as shown in FIG. 7(e), the drive line 5 is raised to 5.degree. to restore the polarization direction of the capacitor 2b. Furthermore, as shown in FIG. 7(f), the drive line 5 is set to Ov to strengthen the polarization of the capacitor 2a.

[Problem to be solved by the invention]

Conventional nonvolatile memories using ferroelectric materials are constructed as described above, and one bit consists of two cells, making it extremely difficult to achieve high integration.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can store one bit in one cell and can easily be highly integrated. .

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention includes a memory cell that includes a selection transistor and a capacitor made of ferroelectric material, and the drain of the selection transistor is connected to a bit line or a bit line, and the gate is connected to a word line. Then, connect the source to one electrode of the capacitor, connect the other electrode of the capacitor to the drive cotton, and select a dummy cell. The drain of the selection transistor is connected to the bit line or bit line, the gate is connected to the dummy word line, the source is connected to one electrode of the capacitor, and the other electrode of the capacitor is connected to the dummy drive line. It was designed to do so.

Further, in the non-volatile semiconductor memory device according to the present invention, the memory cell is composed of a selection transistor and a capacitor formed of a ferroelectric material, the drain of the selection transistor is connected to a bit line or a bit line, and the gate is connected to a word line. connect to,
The tooth is connected to one electrode of the capacitor, the other electrode of the capacitor is connected to the drive line, and a dummy cell is formed from a material other than the selection transistor and ferroelectric, and the capacitance value is formed from the ferroelectric of the memory cell. The drain of the selection transistor is connected to the bit line or the bit line, the gate is connected to the dummy word line, the source is connected to one electrode of the capacitor, and the other electrode of the capacitor is connected to the select transistor. The electrode is connected to a dummy drive line.

Further, in addition to the above-described configurations, the nonvolatile semiconductor memory device according to the present invention has its source grounded, its drain connected to a bit line and the bit line, and its gate connected at the end of a write cycle and a read cycle. “H
'' (activated) and then receives a control signal that turns the word line and the dummy word line "L" (inactive).

[Effect]

According to the present invention, as described above, a dummy cell is used and the area of the capacitance formed by the ferroelectric material constituting the dummy cell is made smaller than that of the memory cell, so that one bit can be processed by one cell. Therefore, the cell size of the nonvolatile semiconductor memory device can be reduced, and high integration becomes possible.

Further, according to the present invention, as described above, a dummy cell is used and the capacitance of the dummy cell is formed of a material other than ferroelectric material having a capacitance value larger than that of the memory cell. 1 bit can be configured, high integration is possible, and the number of reads is no longer limited by fatigue of the dummy cell.

Further, according to the present invention, a transistor is further provided as described above, and a reset signal is applied at the end of a write cycle and a read cycle to ground the bit line and the bit line, so that the charge accumulated in the ferroelectric material is removed. Since the word line is brought down after the word line is removed, the capacitance of the memory cell can always be maintained in a state where the charge is removed, and stable reading can be performed at all times regardless of cycle time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In the figure, 15 is a selection transistor, 16 is a capacitor made of ferroelectric material, and the drain of the selection transistor 15 is is bit line 17. The gate is connected to a word line 18, and one electrode of the capacitor 16 is connected to a drive line 19. The dummy cell is composed of a selection transistor 20 and a capacitor 21 made of a ferroelectric material whose area is smaller than that of the capacitor 16. At this time, the current for charging the capacitor 21 of the dummy cell plus the current necessary for reversing polarization is set to be larger than the current for charging the capacitor 16 of the memory cell. The selection transistor 20 has a drain connected to a bit line 22 and a gate connected to a dummy word line 23. One electrode of the capacitor 21 is connected to a dummy drive m24. 25 is a sense amplifier. Additionally, a reset transistor 26 is connected to bit %I22. A reset signal R5T27 is input to the gate of the reset transistor 26.

Next, the operation will be explained.

Write “Hm” to the drive line 19, select word line 18
By applying "H" to the bit line 17, if the write data is "L", applying "H" to the bit line 17, and applying "L" if it is "0°", and then lowering the drive line 19 to "L". At this time, signal R3T27 is set to “H” and bit line 2
Ground 2 and dummy word! With "H" applied to l#I23, the dummy drive line is lowered from H° to "L", and the polarization direction of the capacitance of dummy cell B is set in the same direction as "0" was written.

Read bit line 17. The bit line 22 is precharged to "H", the drive line 19 and the dummy drive line 24 are set to 1L'', and the selected word line 18 and dummy word line 2 are
3 is set to H".If the current flowing from the bit line 17 to the memory cell A is 11, and the current flowing from the bit line 22 to the dummy cell is It, then the area of the capacitor 21 of the dummy cell B is the capacitance of the memory cell A. Since it is smaller than 16, the data written to memory cell A is "1'".
When it is 11<Ig, and when it is 'O', I+>Ig, and the level of the bit line 22 is the same as the level of pin 1-m17 when reading "1" and the level of bit line 17 when reading "O".
be in between the levels of. This level difference is detected by the sense amplifier 2.
Reading is performed by amplifying the signal at step 5. after that,
Drive line 1. Rewriting is performed by changing 9 from "H" to L'.

In FIG. 1, a sumo wrestler has a memory cell A connected to the bit line 17 side and a dummy cell B connected to the bit line 22 side. It may be provided on both sides of the
When a memory cell on the left side is selected, a dummy cell on the right side is selected, and when a memory cell on the right side is selected, a dummy cell on the left side is selected.

As mentioned above, the above 1. According to the second embodiment, since the area of the capacitor formed of the ferroelectric material constituting the dummy cell is halved, one cell composed of one selection gate and one capacitor made of ferroelectric material One bit can be composed of
This has the effect of increasing capacity.

However, in the first and second embodiments, there are two cases in which data is read out immediately after being written into a memory cell;
If the data is read after a sufficient amount of time has elapsed, the amount of charge remaining in the capacitor formed by the ferroelectric material will be different, so the potential of the bit line will be different and the problem of narrowing the read margin may occur. be.

- Therefore, as a third embodiment of the present invention, a nonvolatile semiconductor memory device that further solves the above problems will be described.

The circuit diagram of the embodiment of the wood brush 3 is the same as FIG. 2 of the second embodiment. What concerns this embodiment is the timing of the control signal, which is shown in FIG.

The signal R3T is applied at the end of both the write cycle and the read cycle, the bit vA17 and the bit line 22 are grounded, and the word line falls after the charge accumulated in the ferroelectric is extracted. There is.

According to the third embodiment, since the capacitance of the memory cell is always maintained in a state where the charge is extracted, there is an effect that stable reading can be performed at all times without depending on the cycle time.

Further, a fourth embodiment of the present invention will be shown below. In each of the above embodiments, since the capacitance of the dummy cell is formed of a ferroelectric material, there is a problem that the number of readings is limited due to fatigue of the dummy cell. In other words, the number of times the capacitor formed of ferroelectric material is rewritten is approximately 109 to 10'', but when any memory cell connected to the bit line is read, the dummy cell connected to the bit line is rewritten. Therefore, for example, if 102 memory cells are connected to a bit line, the number of reads is 1.
It decreases to 0' to 1010. The embodiment of the wood brush 4 was made to solve the above problems, and the circuit diagram thereof is shown in FIG. This means that they are doing so. The capacitance value of the capacitor 28 is larger than the capacitor 16 formed of a ferroelectric material of the memory cell, and is set so that the current value flowing into the dummy cell is smaller than the current flowing when polarization is reversed. The operation is similar to that of the first embodiment.

In this embodiment of the wood pen 4, since the capacitance of the dummy cell is formed of a material other than ferroelectric material, there is an effect that the number of readings is not limited by fatigue of the dummy cell.

In the fourth embodiment, one memory cell is provided on one side of the sense amplifier 25 and one dummy cell is provided on the other side of the sense amplifier 25, as shown in FIG. 4, but this is different from the second embodiment. As an example, similar to the configuration shown in FIG. 2, dummy cells and memory cells are provided on both sides of the sense amplifier 25, and when the left memory cell is selected, the right dummy cell is selected, and when the right memory cell is selected, the dummy cell is provided. The dummy cell on the left may be selected.

Furthermore, in the fourth embodiment, as shown in FIG. 3 as the third embodiment, the signal R3T is applied at the end of the write cycle and the read cycle,
The bit line 17 and the bit line 22 may be grounded to draw out the charge accumulated in the capacitance before the word line is brought down. In this case, in addition to the effects of the fourth embodiment, Similar to the effect of the third embodiment, the capacitance of the memory cell is always maintained in a state where the charge is extracted, and there is an effect that stable reading can be performed at all times without depending on the cycle time.

〔Effect of the invention〕

As described above, according to the present invention, a memory cell is composed of a selection transistor and a capacitor formed of a ferroelectric material, and a dummy cell is formed of a selection transistor and a ferroelectric material, and its area is larger than the capacitance of the memory cell. Since the capacitance is made up of small capacitances, one bit can be made up of one cell made up of one select gate and one ferroelectric capacitor, which has the effect of making it possible to increase the capacitance. Also,
According to the present invention, a memory cell is formed of a selection transistor and a capacitor made of a ferroelectric material, and a dummy cell is formed of a selection transistor and a material other than a ferroelectric material, and its capacitance value is the same as that of the ferroelectric material of the memory cell. In addition to the above-mentioned effects, the number of read operations is no longer limited by fatigue of the dummy cells, and stable read operations can be performed at all times. Furthermore, in addition to each of the above configurations, a transistor is provided whose source is grounded, whose drain is connected to the bit line, and whose gate receives a control signal, and which is used at the end of the write cycle and read cycle. Since the word line and dummy word line are set to "H" (active) and the word line and dummy word line are set to "L" (inactive), the capacitance of the memory cell can always be maintained in a state where the charge is extracted. This has the advantage that stable reading can be performed at all times without depending on cycle time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a non-volatile semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a diagram showing a non-volatile semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a diagram showing a non-volatile semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a diagram showing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 5 is a diagram showing a memory cell and configuration of a conventional example. Figure 6 is a diagram showing the current-voltage characteristics of a capacitor formed of ferroelectric material, and Figures 7 (al to (f) are diagrams for explaining read and write operations of a nonvolatile semiconductor memory device. In the figure, 15.15a and 15b are selection transistors of the main T-IJ cell, 16.16a and 16b are memory cell capacitances, 17 is a bit line, 18.18a and 18b are word lines, 19.19a, 19b is a drive line, 20.
20a and 20b are selection transistors of dummy cells; 21
, 21a, 21b are capacitances of dummy cells, 22 is a bit line, and 23.23a. 23b is a dummy word line; 24. 24 a, 24
b is a dummy drive line, 25 is a sense amplifier, 26° 26a and 26b are reset transistors, 27.
. 27a and 27b are reset signals, and 28 is a capacitor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) A first capacitor formed of ferroelectric material, one electrode of which is connected to the drive line, its drain connected to the bit line or inverted bit line, and its gate connected to the word line; a memory cell consisting of a first selection transistor whose source is connected to the other electrode of the first capacitor, and a ferroelectric material, the area of which is
a second capacitor whose one electrode is connected to the dummy drive line, whose drain is connected to the bit line or inverted bit line, whose gate is connected to the dummy word line, and whose source is a dummy cell comprising a second selection transistor connected to the other electrode of the second capacitor. (2) a first capacitor formed of ferroelectric material, one electrode of which is connected to the drive line; its drain connected to the bit line or inverted bit line; and its gate connected to the word line; a memory cell consisting of a first selection transistor whose source is connected to the other electrode of the first capacitor, and a ferroelectric material, the area of which is
a second capacitor whose one electrode is connected to the dummy drive line, whose drain is connected to the bit line or inverted bit line, whose gate is connected to the dummy word line, and whose source is a dummy cell consisting of a second selection transistor connected to the other electrode of the second capacitor, the source of which is grounded, and the drain of which is connected to a bit line and an inverted bit line;
and a transistor whose gate receives a control signal that becomes "H" (active) at the end of a write cycle and a read cycle, and then sets the word line and the dummy word line to "L" (inactive). A nonvolatile semiconductor memory device characterized by: (3) A first capacitor formed of a ferroelectric material and having one electrode connected to the drive line, its drain connected to the bit line or inverted bit line, its gate connected to the word line, and the source a first selection transistor connected to the other electrode of the first capacitor; and a memory cell formed of a material other than ferroelectric, the capacitance of which is
a second capacitor whose one electrode is connected to the dummy drive line, whose drain is connected to the bit line or the inverted bit line, whose gate is connected to the dummy word line, and whose source is connected to the dummy word line. and a second selection transistor connected to the other electrode of the second capacitor. (4) A first capacitor formed of a ferroelectric material and having one electrode connected to the drive line, its drain connected to the bit line or inverted bit line, its gate connected to the word line, and the source a first selection transistor connected to the other electrode of the first capacitor; and a memory cell formed of a material other than ferroelectric, the capacitance of which is
a second capacitor whose one electrode is connected to the dummy drive line, whose drain is connected to the bit line or the inverted bit line, whose gate is connected to the dummy word line, and whose source is connected to the dummy word line. A second selection transistor is connected to the other electrode of the capacitance of 2, its source is grounded, its drain is connected to the bit line and the inverted bit line, and its gate is connected to the terminal at the end of the write cycle and the read cycle. “H” (active)
A non-volatile semiconductor memory device comprising: a transistor to which a control signal for setting the word line and the dummy word line to "L" (inactive) is input.