JPH02209737A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make capacity between a gate and a drain extremely small and to lessen noise and also to make it have high gain up to high frequency by thinning the thickness of a low resistance layer positioned below a drain electrode than that of a low resistance layer positioned below a source electrode. CONSTITUTION:On the main face side of a semiinsulating GaAs substrate 1, an N-type channel layer 2 and an N<+>-type resistance layer 3 are accumulated continuously on the whole face using a usual epitaxial method. As the thickness of the N<+>-type resistance layer 3, it is accumulated from about 0.1mum to about 0.15mum. A source electrode 4 is formed on the N<+>-type resistance layer 3, and also a drain electrode 5 is formed thereon after etching the N<+> type resistance layer 3 by about 0.05mum to about 0.1mum and thinning it than the thickness of the N<+>-type resistance layer 3 below the source electrode 4. Accordingly, the thickness of the N<+>-type resistance layer 3 positioned below the drain electrode 5 is thinner than that of the N<+>-type resistance layer 3 positioned below the source electrode 4. For this reason, the area of the N<+>-type resistance layer 3 of the drain facing the side face of electrode is small and the capacity between gate and drain decreases.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to field effect transistors, particularly semi-insulating GaAs
The present invention relates to a field effect transistor (hereinafter referred to as MESFET) having a Schottky junction formed on a substrate and a method for manufacturing the same.

Conventional technology MESFET uses a semi-insulating GaAs substrate with an N-type channel layer and an N◆-type low resistance layer deposited on the substrate.
It exhibits high gain and low noise even at high frequencies of 10 GHz or higher, and is used as a main element in satellite communications and other applications. Generally, the noise value of MESFET changes depending on parameters such as gate resistance, mutual conductance, and source resistance, but it also changes significantly depending on another important parameter, gate-drain question and answer ft (hereinafter referred to as Cgd). do. In order to further reduce noise,
It is necessary to reduce Cgd to reduce noise feedback from the output side of the MESFET to the input side, that is, noise returning from the drain to the gate. Further, Cgd is an important factor that determines the gain of a transistor together with mutual conductance, and if Cgd can be reduced by half, the gain can be improved by 3 dB.

In MESFETs formed on semi-insulating GaAs substrates, in order to reduce the source resistance and obtain good ohmic contact between the source and drain electrodes and the channel layer, an N◆ low resistance layer made of N◆ type GaAs or the like is used. A commonly used method is to form a layer with a thickness of about 0.1 to 0.15 μm on the top of the substrate and recess-etch this layer only in the vicinity of the gate electrode. In such a structure, C
Generally, more than half of gd is occupied by the capacitance formed between the side surface of the gate electrode and the N4 type low resistance layer.

Therefore, it has been a major challenge to reduce the capacitance formed between the gate electrode and the N4 type low resistance layer to reduce noise and improve gain.

FIG. 3 is a cross-sectional view of a semiconductor device using a conventional N-type channel layer and an N♦-type low resistance layer. As an example of a semiconductor device, a MESFET using GaAs having a recessed structure will be explained. In FIG. 3, on the main surface side of a semi-insulating GaAs substrate 1, an N-type channel layer 2 which becomes a channel of a field effect transistor and an N-type paper resistance layer 3 for reducing source and drain resistance are formed by a normal epitaxial method. Deposited continuously. A source electrode 4 and a drain electrode 5 are formed on the N'low resistance layer 3. The gate electrode 6 is located between the source electrode 4 and the drain electrode 5, and is formed by etching a portion of the N◆ type low resistance layer 3, that is, in a recessed region. A surface protection film 7 such as a nitride film is deposited over the entire surface of the element. In FIG. 3, the thickness of the N-shaped paper resistor layer 3 located under the source electrode 4 and drain electrode 5 is exactly the same.

FIG. 4 is an enlarged view of the gate portion of the conventional structure shown in FIG. 3. In Figure 4, the gate/drain question and answer ff
i(Cgd) 8 is formed between the gate electrode 6 and the N0 type low resistance layer 3 on the drain side. Similarly, a gate-source capacitance (Cgs) 9 is formed between the gate electrode 6 and the N4 type low resistance layer 3 on the source side. In the conventional structure, the gap between the gate electrode 6 and the N-shaped resistor layer 3 on the drain side is narrow, and a nitride film with a high dielectric constant is often used as the surface protective film 7 to increase moisture resistance. It was extremely difficult to reduce the interstitial capacitance (Cgd) 8.

FIG. 5 is a process cross-sectional view showing a conventional method of manufacturing a semiconductor device. As a semiconductor device, the same <M using GaAs
An explanation will be added using ESFET as an example.

In FIG. 5, the same numbers or symbols are used for parts equivalent to those in FIGS. 3 and 4.

FIG. 5(a) shows an N-type channel layer 2, which will become a channel of a field effect transistor, and an N◆-type layer formed on the main surface side of a semi-insulating GaAs substrate 1 by a normal epitaxial method to reduce source and drain resistance. This is a step of forming a source electrode 4 and a drain electrode 5 on the N◆ type low resistance layer 3 after successively depositing the resistance layer 3. Figure 5(b) shows
After depositing insulating IIO on the surface, an opening is provided between the source electrode 4 and the drain electrode 5, and N◆
The mold low resistance layer 3 is selectively etched to form a recessed region 11.
This is the process of forming. Figure 5(c) is Figure 5(b)
In this step, a gate electrode is formed in the recessed region 11 formed in step 1 by a lift-off method. After applying resist 12 to the entire surface, a window for forming a gate is opened using a normal exposure method. A metal film 13 is then deposited over the entire surface. FIG. 5d) shows a step in which after the resist 12 is completely removed, a surface protective film 7 such as a nitride film is deposited over the entire surface to complete the device.

Problems to be Solved by the Invention In the conventional semiconductor devices shown in FIGS. 3 and 4, the capacitance between the gate and the drain is large (the noise appearing on the output side is the feedback capacitance) - the drain Q&A tt (Cg
d) and returns to the input side, making it difficult to reduce noise. Furthermore, the gate-drain capacitance (Cgd) is large, resulting in a very small gain at high frequencies. That is, as shown in FIG.
This was because (Cgd)8 was large.

In addition, in the conventional semiconductor device manufacturing method shown in FIG. 5, since the N◆ type low resistance layer 3 on the drain side is always located near the gate electrode, the gate electrode 6 and the N4 type low resistance layer on the drain side are always located near the gate electrode. The gate-drain capacitance formed between 3 (
Cgd)8 could not be reduced, and only a device with large noise and small gain could be manufactured.

The present invention has been made in view of this point, and the gate
It is an object of the present invention to provide an excellent semiconductor device having a very small drain capacitance ffi (Cgd), low noise, and high gain up to high frequencies, and a method for manufacturing the same.

Means for Solving the Problems In order to solve the above problems, the present invention uses a channel layer and a low resistance layer that are successively deposited on a semiconductor substrate, and a source electrode and a drain electrode are formed on the low resistance layer. In addition, in a Schottky junction field effect transistor in which the gate electrode is provided in a region where the low resistance layer is recess-etched, the thickness of the low resistance layer located under the drain electrode is the same as that of the low resistance layer located under the source electrode. The structure is such that it is thinner than the layer.

In addition, in order to solve the above-mentioned problems, the present invention includes a process of selectively etching only the low resistance layer of the channel layer and the low resistance layer successively deposited on the semiconductor substrate to reduce the thickness. A drain electrode is formed on the etched low resistance layer, a source electrode is formed on the unetched low resistance layer, and a gate electrode is formed between the source electrode and the drain electrode.

Effect of the present invention With the above-described configuration, the thickness of the low resistance layer on the drain side is thinner than that on the source side, and the low resistance layer on the drain side is not located next to the gate electrode, so that there is a gap between the gate electrode and the low resistance layer on the drain side. The gate-drain capacitance (Cg
d) can be significantly reduced. Therefore, noise appearing on the output side does not return to the input side via the gate-drain capacitance (Cgd), which is a feedback capacitance, and it is possible to reduce noise. Furthermore, since the gate-drain capacitance (Cgd) is small, the gain at high frequencies can also be improved by about 3 dB.

Furthermore, the present invention allows the thickness of the low resistance layer on the drain side to be controlled freely regardless of the thickness of the low resistance layer on the source side by sequentially performing the steps of the semiconductor device described above.
Not only can the drain capacitance ffi (Cgd) be reduced, but the breakdown voltage and the like can be easily controlled, making it possible to realize an element with a high drain breakdown voltage while keeping the source resistance low.

Embodiment FIG. 1 is a cross-sectional structural diagram of a semiconductor device of the present invention. In the semiconductor device of the present invention shown in FIG. 1, parts equivalent to those in FIGS. 3, 4, and 5 are designated by the same reference numerals.

An explanation will be added using an example of a MESFET using GaAs as a semiconductor device. An N-type channel layer 2 and an N-type low-resistance layer 3 are successively deposited on the entire surface of the main surface of a semi-insulating GaAs substrate 1 using a normal epitaxial method. The thickness of the N◆ type low resistance layer 3 is approximately 0.1 μm to 0.15 μm.
Deposits of about 1.0 m. The source electrode 4 is on the N-type low-resistance layer 3, and the drain electrode 5 is on the N-type low-resistance layer 3 at 0.05
The N''-type low resistance layer 3 under the source electrode 4 is etched by approximately 0.1 μm (after that, it is formed on top of the N'' type low resistance layer 3).
The thickness of the type low resistance layer 3 is the same as that of the N type low resistance layer 3 located below the source electrode 4.
It is thinner than the thickness of the ゛-type low resistance layer 3.

The gate electrode 6 is formed in a region where the N 4 type low resistance layer 3 is recessed and etched. A surface protective film 7 is deposited on the entire surface of the device to form a padded vane film.

In the semiconductor device of the present invention shown in FIG. 1, the thickness of the N3 type low resistance layer 3 located under the drain electrode 5 is thin due to etching, so that the N◆ of the drain opposing the side surface of the gate electrode is thin. The area of the type low resistance layer 3 is small, and the gate-to-drain capacitance (Cgd) is reduced. As a result, the gate-drain capacitance ffi (Cg
Noise appearing on the output side via d) does not return to the input side (lower element noise can be achieved.In addition, the gain is improved because the gate and drain capacitance ffi (Cgd) has been reduced. In addition, since the N-type low resistance layer 3 on the source side is kept thick and the N-type paper resistance layer on the drain side is made thin, there is no increase in the source resistance.According to experiments, the Noise is 0.15dB at 12GHz
The gain is also 2.5 at 12GHz.
Improved by dB.

FIG. 2 is a process cross-sectional view showing the method for manufacturing a semiconductor device of the present invention. In the method for manufacturing a semiconductor device of the present invention shown in FIG. 2, parts equivalent to those in FIGS. 1, 3, 4, and 5 are denoted by the same reference numerals. In FIG. 2(a), an insulating film 10 is selectively left on the surfaces of an N-type channel layer 2 and an N-type low-resistance layer 3 deposited on a semi-insulating GaAs substrate, and an N◆-type low-resistance layer 3 is formed. 0.0
Etching area 1 from 5μm to 0.1μm
This is the process of forming 4. The thickness of the N◆ type low resistance layer 3 is initially about 0.1 μm to 0.15 μm, but as a result of etching, the N4 type low resistance layer 3 has a thickness of about two plates. Become. A drain electrode will be formed in the region thinned by this etching, and a source electrode will be formed in the unetched region in a subsequent step. FIG. 2(b) shows a step of forming the source electrode 4 and the drain electrode 5. The source electrode 4 is formed on the N4 type low resistance layer 3 which has not been etched, and the drain electrode 5 is formed on the N♦ type low resistance layer 3 which has been thinned by etching. FIG. 3(C) shows a step of forming a gate electrode at a predetermined position by a lift-off method.

After applying resist 12 to the entire surface, a gate window is opened, and a metal film 13 is deposited over the entire surface. When the resist 12 is then removed with a solvent, only the gate electrode remains. FIG. 2(d) shows a step of depositing a surface protective film 7 over the entire surface of the device, and the device is now completed. By using the method of manufacturing a semiconductor device of the present invention shown in FIG. 2, the capacitance between the gate and drain can be reduced without sacrificing the resistance of the source, and a device with low noise and high gain can be realized. be able to. That is, by thinning only the N◆ type low resistance layer on the drain side while keeping the N◆ type paper resistance layer thick on the source side, the side surface of the gate electrode and the drain side, which account for more than half of the capacitance between the gate and drain, are thinned. The capacitance between the N4 type low resistance layers is significantly reduced, making it possible to reduce noise and increase gain.

Further, by using the present invention, it is also possible to improve the controllability of the breakdown voltage between the gate and the drain by changing the thickness of the N◆ type low resistance layer on the drain side.

Effects of the Invention As described above, the present invention brings about the following effects.

(1) By making the low resistance layer located under the drain electrode thinner than the low resistance layer located under the source electrode, the gate electrode, which accounts for more than half of the capacitance between the gate and drain, The capacitance between the side surface and the drain N4 type low resistance layer can be significantly reduced.

Moreover, the source resistance does not become high.

(2) Gate-drain capacitance (Cgd
) The noise that appears on the output side does not return to the input side through the filter, making it possible to reduce the noise of the element. Also, the gain is improved.

(3) Controllability of breakdown voltage between the gate and the drain can be improved by changing the thickness of the N◆ type low resistance layer on the drain side.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram showing an embodiment of a semiconductor device of the present invention, FIG. 2 is a process cross-sectional diagram showing an embodiment of a method for manufacturing a semiconductor device of the present invention, and FIG. 3 is a cross-sectional diagram showing a conventional semiconductor device. FIG. 4 is an enlarged view of the gate portion of the conventional semiconductor device shown in FIG. 3, and FIG. 5 is a process sectional view showing the conventional method of manufacturing the semiconductor device. 1・φφ semi-insulating GaAs substrate, 2・Fist・N type channel layer, 3...N゛ type patterned paper resistance layer 4・Fist・source electrode i,
5-...Drain electrode, 6-Fist/gate electrode, 7...
Surface protective film, 8... Gate-drain capacitance (Cgc
l), 10.-φ insulating film, 12... resist, 13.
...metal film, 141 issues/etching area. Name of agent: Patent attorney Shigetaka Awano

Claims (2)

[Claims] (1) In a Schottky junction field effect transistor in which a channel layer and a low resistance layer are successively deposited on a semiconductor substrate, and a gate electrode is provided in a region where the low resistance layer is recessed and etched, the gate electrode is located below the drain electrode. A semiconductor device characterized in that the thickness of the low resistance layer located under the source electrode is thinner than that of the low resistance layer located under the source electrode. (2) A step of selectively etching only the low resistance layer of the channel layer and low resistance layer successively deposited on the semiconductor substrate to reduce the thickness, and forming a drain electrode on the low resistance layer whose thickness has been reduced. A method for manufacturing a semiconductor device characterized by comprising the steps of: forming a source electrode on the unetched low resistance layer; and forming a gate electrode between the source electrode and the drain electrode. .