JPH02184908A - Information processor - Google Patents

Abstract

PURPOSE:To dispense with manual clock control by individual device and to maintain processing speed to a maximum corresponding to environment by performing the automatic control of the clock of a central processing part. CONSTITUTION:A clock controller 4 controls the clock 2 so that the normal critical speed of information transmission in a delay circuit 3 having a delay condition equivalent to that of a critical path on the hardware of the central processing part 1 can always be set. And the delay condition of a delay simulation circuit 3 is set at the one equivalent to or strict a little than that of the critical path on the hardware of the central processing part 1. Thereby, it is possible to always operate the central processing part 1 at the maximum speed normally by the output of the clock 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock adjustment method for a central processing unit in an information processing device.

[Conventional technology]

Conventionally, the clock adjustment of the central processing unit in information processing equipment was either set to a fixed value with sufficient margin, or set to a value accelerated to the operating limit at the time of factory shipment or on-site adjustment. .

[Problem to be solved by the invention]

However, with the conventional method described above, it is not possible to fully bring out the performance of the device with fixed values, it is time-consuming to set individual limit values, and it may malfunction if the operating environment such as temperature changes. The downside is that it is possible.

[Means to solve the problem]

The configuration of the information processing device of the present invention includes a delay simulating means having a delay condition equivalent to the critical path on the hardware of the central processing unit, and a maximum clock speed within the range where normal information transmission is performed in this delay simulating means. a means to find
The method is characterized in that it includes means for supplying a clock corresponding to the determined maximum clock speed to the central processing section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which is comprised of a central processing section 1, a tarok 2, a delay simulation circuit 3, and a clock regulator 4.

The tarot controller 4 adjusts the clock 2 so that the speed is the limit at which information transmission in the delay simulation circuit 3, which has the same delay conditions as the critical path on the hardware of the central processing unit 1, is always performed normally. Since the delay simulation circuit 3 has a delay condition equal to or slightly stricter than the hardware critical path of the central processing unit 1, the output of the clock 2 is always connected to the central processing unit. 1 to operate normally at maximum speed.

〔Effect of the invention〕

As explained above, the present invention automatically adjusts the clock of the central processing unit in an information processing device, thereby eliminating the need for manual clock adjustment for each device, and adjusting the processing speed of the information processing device depending on the environment. It has an effect that can be maintained at its maximum depending on the situation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Clock, 3...Delay simulation circuit, 4...Clock adjuster.

Claims (1)

[Claims] A delay simulating means having a delay condition equivalent to the critical path on the hardware of the central processing unit, a means for determining the maximum clock speed within the range where normal information transmission is performed in this delay simulating means, and a means for determining the maximum clock speed within the range where normal information transmission is performed in this delay simulating means, An information processing device comprising: means for supplying a clock corresponding to a clock speed to the central processing unit.